On Sun, Nov 13, 2016 at 11:43:01PM -0800, Manasi Navare wrote:
> On Fri, Nov 11, 2016 at 07:42:16PM +, Cheng, Tony wrote:
> > In case of link training failure and requiring user space to set a lower
> > mode, would full mode set address it? How do we make user mode select
> > lower resolutio
The primary operation on the shared fence arrays is insertion and
retrieval. Retrieval is reasonably fast, as we just copy the array, but
insertion into the shared fence array is slow as we must iterate over all
current fences to discard an older fence. (Note also that since the
array is not auto
Hi Chris,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on next-20161114]
[cannot apply to v4.9-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/dma-buf-Replace
The shared fence array is not autopruning and may continue to grow as an
object is shared between new timelines. Take the opportunity when we
think the object is idle (we have to confirm that any external fence is
also signaled) to decouple all the fences.
Fixes: d07f0e59b2c7 ("drm/i915: Move GEM
Generalise the skip for physical and stolen objects by skipping anything
we do not have a valid address inside the sg.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/dr
If the LLC is coherent with the object, we do not need to worry about
whether main memory and cache mismatch when we hand the object back to
the system.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/g
Track the priority of each request and use it to determine the order in
which we submit requests to the hardware via execlists.
The priority of the request is determined by the user (eventually via
the context) but may be overridden at any time by the driver. When we set
the priority of the reques
The start of the scheduler, add a hook into request submission for the
scheduler to see the arrival of new requests and prepare its runqueues.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_gem_request.c |
Defer the transfer from the client's timeline onto the execution
timeline from the point of readiness to the point of actual submission.
For example, in execlists, a request is finally submitted to hardware
when the hardware is ready, and only put onto the hardware queue when
the request is ready.
This emulates execlists on top of the GuC in order to defer submission of
requests to the hardware. This deferral allows time for high priority
requests to gazump their way to the head of the queue, however it nerfs
the GuC by converting it back into a simple execlist (where the CPU has
to wake up
In order to support deferred scheduling, we need to differentiate
between when the request is ready to run (i.e. the submit fence is
signaled) and when the request is actually run (a new execute fence).
This is typically split between the request itself wanting to wait upon
others (for which we use
The execlist_lock is now completely subsumed by the engine->timeline->lock,
and so we can remove the redundant layer of locking.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 8 ++--
dr
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via
Boost the priority of any rendering required to show the next pageflip
as we want to avoid missing the vblank by being delayed by invisible
workload. We prioritise avoiding jank and jitter in the GUI over
starving background tasks.
v2: Descend dma_fence_array when boosting priorities.
Signed-off-
In order to simplify the lockdep annotation, as they become more complex
in the future with deferred execution and multiple paths through the
same functions, create a separate lockclass for the user timeline and
the hardware execution timeline.
We should only ever be locking the user timeline and
Localise the static struct lock_class_key to the caller of
i915_sw_fence_init() so that we create a lock_class instance for each
unique sw_fence rather than all sw_fences sharing the same
lock_class. This eliminate some lockdep false positive when using fences
from within fence callbacks.
Signed-o
Now that the user can opt-out of implicit fencing, we need to give them
back control over the fencing. We employ sync_file to wrap our
drm_i915_gem_request and provide an fd that userspace can merge with
other sync_file fds and pass back to the kernel to wait upon before
future execution.
Testcase
In order to support userspace defining different levels of importance to
different contexts, and in particular the preferred order of execution,
store a priority value on each context. By default, the kernel's
context, which is used for idling and other background tasks, is given
minimum priority (
Userspace is faced with a dilemma. The kernel requires implicit fencing
to manage resource usage (we always must wait for the GPU to finish
before releasing its PTE) and for third parties. However, userspace may
wish to avoid this serialisation if it is either using explicit fencing
between parties
The scheduler needs to know the dependencies of each request for the
lifetime of the request, as it may choose to reschedule the requests at
any time and must ensure the dependency tree is not broken. This is in
additional to using the fence to only allow execution after all
dependencies have been
On 14/11/2016 08:56, Chris Wilson wrote:
Localise the static struct lock_class_key to the caller of
i915_sw_fence_init() so that we create a lock_class instance for each
unique sw_fence rather than all sw_fences sharing the same
lock_class. This eliminate some lockdep false positive when using f
On Mon, Nov 14, 2016 at 09:01:00AM +, Tvrtko Ursulin wrote:
>
> On 14/11/2016 08:56, Chris Wilson wrote:
> >Localise the static struct lock_class_key to the caller of
> >i915_sw_fence_init() so that we create a lock_class instance for each
> >unique sw_fence rather than all sw_fences sharing t
Hi Chris,
[auto build test WARNING on drm/drm-next]
[also build test WARNING on next-20161114]
[cannot apply to v4.9-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/dma-buf
[corrected my email in cc]
On 12/11/2016 02:21, Jeff McGee wrote:
On Wed, Nov 09, 2016 at 11:11:07AM -0800, Anusha Srivatsa wrote:
Replace i915.enable_guc_loading and i915.enable_guc_submission
with a single parameter - i915.enable_guc. Where:
-1 : Platform default (Only load GuC)
0 : Do not
On Fri, Nov 11, 2016 at 02:17:44PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Drivers like i915 benefit from being able to control the maxium
> size of the sg coallesced segment while building the scatter-
> gather list.
>
> Introduce and export the __sg_alloc_table_from_pages funct
On Fri, Nov 11, 2016 at 12:36:13PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> With the addition of __sg_alloc_table_from_pages we can control
> the maximum coallescing size and eliminate a separate path for
> allocating backing store here.
>
> Similar to 871dfbd67d4e ("drm/i915: All
On Fri, Nov 11, 2016 at 08:50:17AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Scatterlist entries have an unsigned int for the offset so
> correct the sg_alloc_table_from_pages function accordingly.
>
> Since these are offsets withing a page, unsigned int is
> wide enough.
>
> Also
From: Gustavo Padovan
Support the virtio GPU on drmtest.
Signed-off-by: Gustavo Padovan
---
lib/drmtest.c | 9 +
lib/drmtest.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 9f3ac7f..b374006 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic_transition.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index e693c88..8b26b53 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/
From: Gustavo Padovan
Now other gpus are supported too.
Signed-off-by: Gustavo Padovan
---
lib/drmtest.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 884fe7c..9f3ac7f 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -263,7 +263,7 @@ i
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
lib/igt_kms.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 989704e..aa9fd16 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -153,23 +153,6 @
From: Gustavo Padovan
Hi,
That is the first version of the igt tests for DRM fences[1]. The
first four patches are just fix/improvements on the kms_atomic
infrastructure.
These patches depends on Robert Foss tests for sw_sync and a branch
with those tests included can be seen here:
https://git
From: Gustavo Padovan
If the event never arrives we can timeout with select and end the test.
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic_transition.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 1977993
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic.c | 123 -
1 file changed, 37 insertions(+), 86 deletions(-)
diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index 1441fdf..8b648eb 100644
--- a/tests/kms_atomic.c
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
lib/igt_kms.c | 6 +++---
lib/igt_kms.h | 5 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index aa9fd16..8aaff5b 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -153,7 +153,7 @@ cons
From: Gustavo Padovan
Add support for the OUT_FENCE_PTR property to enable setting out fences for
atomic commits.
Signed-off-by: Gustavo Padovan
---
lib/igt_kms.c | 20 +++-
lib/igt_kms.h | 3 +++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/l
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic_transition.c | 92 ++-
1 file changed, 82 insertions(+), 10 deletions(-)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 507f526..54fc9da 100644
--
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic_transition.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 8b26b53..8bef85d 100644
--- a/tests/kms_atomic_transition.c
+
From: Robert Foss
Add support dor the IN_FENCE_FD property to enable setting in fences for atomic
commits.
Signed-off-by: Robert Foss
---
lib/igt_kms.c | 20
lib/igt_kms.h | 5 +
2 files changed, 25 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 8aaff
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic.c | 124 +
1 file changed, 115 insertions(+), 9 deletions(-)
diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index 8b648eb..58fc0dd 100644
--- a/tests/kms_atomic.c
Hi Chris,
Am 14.11.2016 um 09:31 schrieb Chris Wilson:
The primary operation on the shared fence arrays is insertion and
retrieval. Retrieval is reasonably fast, as we just copy the array, but
insertion into the shared fence array is slow as we must iterate over all
current fences to discard an
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
lib/igt_kms.c | 22 ++
tests/kms_atomic_transition.c | 30 --
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index f25e1eb..927
From: Gustavo Padovan
Signed-off-by: Gustavo Padovan
---
tests/kms_atomic_transition.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 54fc9da..3022e04 100644
--- a/tests/kms_atomic_t
== Series Details ==
Series: drm/i915: Prune the reservation shared fence array
URL : https://patchwork.freedesktop.org/series/15254/
State : warning
== Summary ==
Series 15254v1 drm/i915: Prune the reservation shared fence array
https://patchwork.freedesktop.org/api/1.0/series/15254/revisions
== Series Details ==
Series: dma-buf: Replace reservation shared fence array with a compressed radix
tree
URL : https://patchwork.freedesktop.org/series/15252/
State : success
== Summary ==
Series 15252v1 dma-buf: Replace reservation shared fence array with a
compressed radix tree
https://pa
== Series Details ==
Series: series starting with [1/2] drm/i915: Skip clflushes for all non-page
backed objects
URL : https://patchwork.freedesktop.org/series/15255/
State : warning
== Summary ==
Series 15255v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/1525
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/kms_flip.c | 185 ++-
1 file changed, 4 insertions(+), 181 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 2a9fe2e..79cb783 100644
--- a/tests/kms
A lot of igt testcases need some GPU workload to make sure a race
window is big enough. Unfortunately having a fixed amount of
workload leads to spurious test failures or overtly long runtimes
on some fast/slow platforms. This library contains functionality
to submit GPU workloads that should consu
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/gem_wait.c | 125 ---
1 file changed, 7 insertions(+), 118 deletions(-)
diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index b4127de..785bb14 100644
--- a/tests/gem
On 11.11.2016 18:16, Daniel Vetter wrote:
> On Fri, Nov 11, 2016 at 07:41:10PM +0200, Abdiel Janulgue wrote:
>> A lot of igt testcases need some GPU workload to make sure a race
>> window is big enough. Unfortunately having a fixed amount of
>> workload leads to spurious test failures or overtly lo
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/kms_busy.c | 75 +++-
1 file changed, 4 insertions(+), 71 deletions(-)
diff --git a/tests/kms_busy.c b/tests/kms_busy.c
index b555f99..d0fe412 100644
--- a/tests/kms_
From: Tom O'Rourke
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLP
From: Tom O'Rourke
The SLPC interface is dependent on GuC version.
Only GuC versions known to be compatible are supported here.
On SKL, BXT, KBL, GuC firmware v9 is supported. Other
platforms and versions can be added here later.
v1: Updated with modified sanitize_slpc_option in earlier patch
From: Tom O'Rourke
SLPC shared data is used to pass information
to/from SLPC in GuC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v1: Update for SLPC interface version 2015.2.4
intel_sl
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v1: fix whitespace (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Aru
With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handlin
SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in firmware on GuC.
This series has been tested with SKL and APL GuC firmware v9 (not released
yet). Current GuC firmware's SLPC interfaces are updated in v9.
The graphi
From: Tom O'Rourke
Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host
From: Tom O'Rourke
Adds debugfs hooks for enabling/disabling each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo mer
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers an
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
v2-v4: Rebase.
v5: Removed typecasting the frequency values to u32
From: Tom O'Rourke
Communication with SLPC is via Host to GuC interrupt.
This patch defines the data structure to be passed as input
and received as output from SLPC. This patch also defines the
events to be sent as input and status values output by GuC
on processing SLPC events.
v1: fix whitesp
From: Tom O'Rourke
On platforms with SLPC support: call intel_slpc_*() functions from
intel_*_gt_powersave() functions and GuC setup functions and do not
use rps functions. intel_slpc_enable is tied to GuC setup.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. inte
From: Tom O'Rourke
Expose host2guc_action for use by SLPC in intel_slpc.c.
Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.
v1: Updated function names as they need to be made extern. (ChrisW)
v2-v4: Rebase
v5: Commit subject update.
Signe
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.
v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)
v2-v3: Rebase.
v4: Commit message update.
v5: Rebase.
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
From: Tom O'Rourke
This patch adds has_slpc to skylake info.
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Move slpc_
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Rebase. Replaced H2G interrupts for parameter override with memory
setup with required parameters.
Signed-off-by: Sagar Arun Kamble
---
d
v2: Removing checks for vma obj and kmap_atomic validity. (Chris)
v3: Rebase.
v4: Updated to make sure SLPC enable keeps min/max freq softlimits
unchanged after initializing once. (Chris)
v5: s/first_enable/i915_load_enable. Updating freq softlimits after
checking that SLPC has indicated
From: Tom O'Rourke
SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch add parameter values and
events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers
This tests whether SLPC in GuC is configured properly through shared data.
It checks whether GTPERF is running in default state, post reset and post
system suspend/resume.
This test will be extended further based on enablement of other SLPC tasks.
Signed-off-by: Sagar Arun Kamble
---
lib/igt_pm.
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.
v2-v4: Rebase.
v5: Sanitizing SLPC option based on capabilities earlier in
driver l
On Thu, 06 Oct 2016, Tomeu Vizoso wrote:
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 23a6c7213eca..7412a05fa5d9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14636,6 +14636,7 @@ stati
On 14/11/2016 08:56, Chris Wilson wrote:
Localise the static struct lock_class_key to the caller of
i915_sw_fence_init() so that we create a lock_class instance for each
unique sw_fence rather than all sw_fences sharing the same
lock_class. This eliminate some lockdep false positive when using f
On 14/11/2016 08:56, Chris Wilson wrote:
Defer the transfer from the client's timeline onto the execution
timeline from the point of readiness to the point of actual submission.
For example, in execlists, a request is finally submitted to hardware
when the hardware is ready, and only put onto th
On 14/11/2016 08:56, Chris Wilson wrote:
The scheduler needs to know the dependencies of each request for the
lifetime of the request, as it may choose to reschedule the requests at
any time and must ensure the dependency tree is not broken. This is in
additional to using the fence to only allow
Hello Chris Wilson,
The patch 871dfbd67d4e: "drm/i915: Allow compaction upto SWIOTLB max
segment size" from Oct 11, 2016, leads to the following static
checker warning:
drivers/gpu/drm/i915/i915_gem.c:2357 i915_gem_object_get_pages_gtt()
error: we previously assumed 'sg' could be
On 14/11/2016 08:56, Chris Wilson wrote:
Track the priority of each request and use it to determine the order in
which we submit requests to the hardware via execlists.
The priority of the request is determined by the user (eventually via
the context) but may be overridden at any time by the dr
== Series Details ==
Series: Add support for GuC-based SLPC (rev6)
URL : https://patchwork.freedesktop.org/series/2691/
State : success
== Summary ==
Series 2691v6 Add support for GuC-based SLPC
https://patchwork.freedesktop.org/api/1.0/series/2691/revisions/6/mbox/
fi-bdw-5557u total:24
On 14/11/2016 08:56, Chris Wilson wrote:
In order to support userspace defining different levels of importance to
different contexts, and in particular the preferred order of execution,
store a priority value on each context. By default, the kernel's
context, which is used for idling and other b
On Mon, Nov 14, 2016 at 02:14:56PM +0300, Dan Carpenter wrote:
> Hello Chris Wilson,
>
> The patch 871dfbd67d4e: "drm/i915: Allow compaction upto SWIOTLB max
> segment size" from Oct 11, 2016, leads to the following static
> checker warning:
>
> drivers/gpu/drm/i915/i915_gem.c:2357 i915_gem
On the DMA mapping error path, sg may be NULL (it has already been
marked as the last scatterlist entry), and we should avoid dereferencing
it again.
Reported-by: Dan Carpenter
Fixes: e227330223a7 ("drm/i915: avoid leaking DMA mappings")
Signed-off-by: Chris Wilson
Cc: Imre Deak
Cc: sta...@vger
On 14/11/2016 08:57, Chris Wilson wrote:
This emulates execlists on top of the GuC in order to defer submission of
requests to the hardware. This deferral allows time for high priority
requests to gazump their way to the head of the queue, however it nerfs
the GuC by converting it back into a si
On 14/11/2016 08:57, Chris Wilson wrote:
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. Th
On Mon, Nov 14, 2016 at 11:15:52AM +, Tvrtko Ursulin wrote:
> On 14/11/2016 08:56, Chris Wilson wrote:
> >+static void execlists_schedule(struct drm_i915_gem_request *request, int
> >prio)
> >+{
> >+struct intel_engine_cs *engine = NULL;
> >+struct i915_dependency *dep, *p;
> >+str
Hi Andrew,
On 11/11/2016 08:50, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Userptr backing store with SWIOTBL active is currently allocated in the same
inefficient manner, with one sg entry per object page, as what the commit
871dfbd67d4e ("drm/i915: Allow compaction upto SWIOTLB max segment
On 14/11/2016 11:41, Chris Wilson wrote:
On Mon, Nov 14, 2016 at 11:15:52AM +, Tvrtko Ursulin wrote:
On 14/11/2016 08:56, Chris Wilson wrote:
+static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
+{
+ struct intel_engine_cs *engine = NULL;
+ struct i91
The current code is subject to a race where we may try to acquire a
reference on a stale fence:
[13703.335118] WARNING: CPU: 1 PID: 14975 at ./include/linux/kref.h:46
i915_gem_object_wait+0x1a3/0x1c0
[13703.335184] Modules linked in:
[13703.335202] CPU: 1 PID: 14975 Comm: gem_concurrent_ Not tain
Would be great if everony could add
$ make DOCBOOKS="" htmldocs
to their build scripts to catch these. 0day should also report them,
not sure why it failed to spot this.
Fixes: f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
Cc: Chris Wilson
Cc: Gustavo Padovan
Cc: Sumit Semwal
Cc:
Just code movement, doc cleanup will follow up later.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/Makefile| 3 +-
drivers/gpu/drm/drm_crtc.c | 109 -
drivers/gpu/drm/drm_crtc_internal.h | 18 ++---
drivers/gpu/drm/drm_dumb_buffers.c | 135
I want to move dumb buffer documentation into the right vfuncs, and
for that I first need to be able to pull that into kerneldoc without
having to clean up all of drmP.h. Also, header-splitting is nice.
While at it shuffle all the function declarations for drm_drv.c into
the right spots, and drop
Hi all,
Final bits, finally, leaving really only CRTC related code and structures in
drm_crtc.[hc].
I guess next up is a bit of polish for atomic code, that has grown a lot and I
think it'd be useful to split at least the helpers a bit. And a recent
discussion with Rob Clark showed me that we've
kerneldoc expects the comment next to definitions, otherwise it can't
pick up exported vs. internal stuff.
This fixes a warning from the doc build done with:
$ make DOCBOOKS="" htmldocs
Fixes: d8187177b0b1 ("drm: add helper for printing to log or seq_file")
Cc: Rob Clark
Cc: Sean Paul
Signed-o
Would be great if everony could add
$ make DOCBOOKS="" htmldocs
to their build scripts to catch these. 0day should also report them,
not sure why it failed to spot this.
Fixes: b42fe9ca0a1e ("drm/i915: Split out i915_vma.c")
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-b
Just cleans up what's there, still plenty missing.
Signed-off-by: Daniel Vetter
---
Documentation/gpu/drm-internals.rst | 3 +
include/drm/drm_drv.h | 168 +++-
2 files changed, 109 insertions(+), 62 deletions(-)
diff --git a/Documentation/gpu/drm
And also put the overview section into the KMS Properties part of the
docs, instead of randomly-placed within the helpers - this is part of
the uabi.
With this patch I think drm_crtc.[hc] is cleaned up and entirely
documented.
Signed-off-by: Daniel Vetter
---
Documentation/gpu/drm-kms-helpers.r
And shuffle the kernel-doc structure a bit since drm_crtc.[hc] now
only contains CRTC-related functions and structures.
Signed-off-by: Daniel Vetter
---
Documentation/gpu/drm-kms.rst | 32 +-
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/drm_crtc.c | 379 +
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