Re: [Intel-gfx] [PATCH] drm/i915: check if execlist_port is empty before using its content

On Fri, Dec 23, 2016 at 01:46:36PM +0800, changbin...@intel.com wrote: > From: "Du, Changbin" > > This patch fix a crash in function reset_common_ring. In this case, > the port[0].request is null when reset the render ring, so a null > dereference exception is raised. We

Re: [Intel-gfx] [PATCH i-g-t v3] tools: Add intel_dp_compliance for DisplayPort 1.2 compliance automation

I have addressed review comments that Petri, Jim had for this patch along with making some small changes for error handling. The functionality is mostly unchanged from Manasi's version. -DK From: Pandiyan, Dhinakaran Sent: Thursday, December 22, 2016

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: request ring to be pinned above GUC_WOPCM_TOP

On Thu, Dec 22, 2016 at 03:15:03PM -0800, Daniele Ceraolo Spurio wrote: > > > On 22/12/16 14:23, Patchwork wrote: > >== Series Details == > > > >Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP > >URL : https://patchwork.freedesktop.org/series/17147/ > >State : failure > > > >==

[Intel-gfx] [PATCH i-g-t v3] tools: Add intel_dp_compliance for DisplayPort 1.2 compliance automation

From: "Navare, Manasi D" This is the userspace component of the Displayport Compliance testing software required for compliance testing of the I915 Display Port driver. This must be running in order to successfully complete Display Port compliance testing. This app and

Re: [Intel-gfx] [PATCH] drm/i915: check if execlist_port is empty before using its content

On Fri, 23 Dec 2016, changbin...@intel.com wrote: > From: "Du, Changbin" > > This patch fix a crash in function reset_common_ring. In this case, > the port[0].request is null when reset the render ring, so a null > dereference exception is raised. We need to check

Re: [Intel-gfx] [PATCH] drm/915: Parsing the missed out DTD fields from the VBT

On Thu, 22 Dec 2016, Ville Syrjälä wrote: > On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote: >> From: Vincente Tsou >> >> The upper bits of the vsync width, vsync offset and hsync width >> were not parsed form the VBT. Parse

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Respect num_pipes when install or reset display IRQ

== Series Details == Series: drm/i915: Respect num_pipes when install or reset display IRQ URL : https://patchwork.freedesktop.org/series/17164/ State : warning == Summary == Series 17164v1 drm/i915: Respect num_pipes when install or reset display IRQ

Re: [Intel-gfx] drm_mm crash with multi threads

On 2016年12月23日 13:57, Rob Clark wrote: On Thu, Dec 22, 2016 at 11:07 PM, Mark yao wrote: Hi Chris Wilson We port drm_mm to my internal kernel, with high load test, found following crash: [49451.856244]

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: check if execlist_port is empty before using its content

== Series Details == Series: drm/i915: check if execlist_port is empty before using its content URL : https://patchwork.freedesktop.org/series/17162/ State : success == Summary == Series 17162v1 drm/i915: check if execlist_port is empty before using its content

[Intel-gfx] [PATCH v4] drm/i915: Respect num_pipes when install or reset display IRQ

From: Elaine Wang Some platforms don't have display. To avoid accessing the non-existent display interrupt registers, check whether num_pipes isn't zero before invoking display IRQ install or reset function. Cc: Chris Wilson Cc: Joonas Lahtinen

Re: [Intel-gfx] drm_mm crash with multi threads

On Thu, Dec 22, 2016 at 11:07 PM, Mark yao wrote: > Hi Chris Wilson > > We port drm_mm to my internal kernel, with high load test, found following > crash: > > [49451.856244] > == > [49451.856350] BUG: KASAN:

[Intel-gfx] [PATCH 2/2] drm/i915/psr: program vsc header for psr2

Function hsw_psr_setup handles vsc header setup for psr1 and skl_psr_setup_vsc handles vsc header setup for psr2. Setup VSC header in function skl_psr_setup_vsc for psr2 support, as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2 operation. v2: (Jani) - Initialize variables to 0 -

[Intel-gfx] [PATCH] drm/i915: check if execlist_port is empty before using its content

From: "Du, Changbin" This patch fix a crash in function reset_common_ring. In this case, the port[0].request is null when reset the render ring, so a null dereference exception is raised. We need to check execlist_port status first. [ 35.748034] BUG: unable to handle

[Intel-gfx] drm_mm crash with multi threads

Hi Chris Wilson We port drm_mm to my internal kernel, with high load test, found following crash: [49451.856244] == [49451.856350] BUG: KASAN: wild-memory-access on address

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Check num_pipes before initializing or calling display hooks

> -Original Message- > From: Jani Nikula [mailto:jani.nik...@linux.intel.com] > Sent: Thursday, December 22, 2016 6:48 PM > To: Wang, Elaine ; intel-gfx@lists.freedesktop.org; > Wang, Elaine > Cc: Chris Wilson ;

Re: [Intel-gfx] [PATCH v3 1/3] drm: Create new structure for HDMI info

Regards Shashank On 12/22/2016 5:26 PM, Ville Syrjälä wrote: On Thu, Dec 22, 2016 at 10:02:26AM +, Jose Abreu wrote: Hi Shashank, On 21-12-2016 15:29, Shashank Sharma wrote: [snip] + + /** +* @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding. +* various

[Intel-gfx] ✓ Fi.CI.BAT: success for HuC Loading Patches

== Series Details == Series: HuC Loading Patches URL : https://patchwork.freedesktop.org/series/17150/ State : success == Summary == Series 17150v1 HuC Loading Patches https://patchwork.freedesktop.org/api/1.0/series/17150/revisions/1/mbox/ fi-bdw-5557u total:246 pass:232 dwarn:0

Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote: > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = _priv->guc; > + struct intel_huc *huc = _priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > +

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: request ring to be pinned above GUC_WOPCM_TOP

On 22/12/16 14:23, Patchwork wrote: == Series Details == Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP URL : https://patchwork.freedesktop.org/series/17147/ State : failure == Summary == Series 17147v1 drm/i915: request ring to be pinned above GUC_WOPCM_TOP

[Intel-gfx] [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check

From: Peter Antoine Add debugfs entry for HuC loading status check. v2: rebase on-top of drm-intel-nightly. v3: rebased again. v7: rebased. v8: rebased. v9: rebased. v10: rebased. v11: rebased on top of drm-tip v12: rebased. v13: rebased. Tested-by: Xiang Haihao

[Intel-gfx] [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

This patch adds the support to load HuC on KBL Version 2.0 v2: rebased. v3: rebased on top of drm-tip v4: rebased. v5: rebased. Rename KBL_FW_ to KBL_HUC_FW_ v6: rebased. Remove old checks. Cc: Tvrtko Ursulin Signed-off-by: Anusha Srivatsa

[Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

From: Peter Antoine The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed

[Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

From: Peter Antoine This patch will allow for getparams to return the status of the HuC. As the HuC has to be validated by the GuC this patch uses the validated status to show when the HuC is loaded and ready for use. You cannot use the loaded status as with the GuC as

[Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is used for both cases. HuC loading needs to be before GuC loading. The WOPCM setting must be done early before loading any of them. v2: rebased on-top of drm-intel-nightly. removed if(HAS_GUC()) before the guc call.

[Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

This patch adds the HuC Loading for the BXT by using the updated file construction. Version 1.7 of the HuC firmware. v2: rebased. v3: rebased on top of drm-tip v4: rebased. v5: rebased. Rename BXT_FW_MAJOR to BXT_HUC_FW_ v6: rebased. Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

From: Peter Antoine Rename some of the GuC fw loading code to make them more general. We will utilise them for HuC loading as well. s/intel_guc_fw/intel_uc_fw/g s/GUC_FIRMWARE/UC_FIRMWARE/g Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,

[Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

From: Peter Antoine HuC firmware css header has almost exactly same definition as GuC firmware except for the sw_version. Also, add a new member fw_type into intel_uc_fw to indicate what kind of fw it is. So, the loader will pull right sw_version from header. v2:

[Intel-gfx] [PATCH 0/8] HuC Loading Patches

These patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: request ring to be pinned above GUC_WOPCM_TOP

== Series Details == Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP URL : https://patchwork.freedesktop.org/series/17147/ State : failure == Summary == Series 17147v1 drm/i915: request ring to be pinned above GUC_WOPCM_TOP

Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Kill the 830 MI_OVERLAY_OFF workaround

On Thu, Dec 22, 2016 at 09:52:22PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Now that we're disabling L2 clock gating MI_OVERLAY_OFF actually works > on 830, so let's use it. > > v2: Nuke the unused dev_priv variable > > Signed-off-by:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/915: Parsing the missed out DTD fields from the VBT (rev2)

== Series Details == Series: drm/915: Parsing the missed out DTD fields from the VBT (rev2) URL : https://patchwork.freedesktop.org/series/17142/ State : success == Summary == Series 17142v2 drm/915: Parsing the missed out DTD fields from the VBT

Re: [Intel-gfx] [PATCH] drm/i915: Revoke partial fences when installing on the scanout

On Thu, Dec 22, 2016 at 06:39:39PM -0200, Paulo Zanoni wrote: > Em Qui, 2016-12-22 às 13:52 +, Chris Wilson escreveu: > > In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT > > writes") partial mmaps were updated to indicate that writes through > > them > > were not tracked

Re: [Intel-gfx] [PATCH] drm/i915: request ring to be pinned above GUC_WOPCM_TOP

>-Original Message- >From: Ceraolo Spurio, Daniele >Sent: Thursday, December 22, 2016 11:55 AM >To: intel-gfx@lists.freedesktop.org >Cc: Ceraolo Spurio, Daniele ; Chris Wilson >; Wajdeczko, Michal ;

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,01/38] drm/i915: Use the MRU stack search after evicting (rev2)

== Series Details == Series: series starting with [v4,01/38] drm/i915: Use the MRU stack search after evicting (rev2) URL : https://patchwork.freedesktop.org/series/17123/ State : success == Summary == Series 17123v2 Series without cover letter

[Intel-gfx] [PATCH igt 4/6] kms_frontbuffer_tracking: refactor sink CRC reliability handling

What I'm currently seeing is that sometimes the first check during setup_sink_crc() returns valid sink CRC, but then the subsequent checks return ETIMEDOUT. In these cases, we keep getting flooded by messages saying that our sink CRC is unreliable and that the results differ. This is annoying for

[Intel-gfx] [PATCH igt 5/6] kms_frontbuffer_tracking: destroy all FBs from all formats

Don't just destroy the ones from the default format. Signed-off-by: Paulo Zanoni --- tests/kms_frontbuffer_tracking.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c index

[Intel-gfx] [PATCH igt 6/6] kms_frontbuffer_tracking: fix compression checking

Ever since Kernel's "drm/i915: don't report compression when fbc is disabled" we've been wrongly assuming that the Kernel doesn't support compression information due to the fact that it doesn't print that specific line when FBC is not active. Fix this by just assuming that the Kernel supports it,

[Intel-gfx] [PATCH igt 3/6] kms_frontbuffer_tracking: move more code to get_sink_crc()

Make it check for the supported flag and decide what to do. This change will make the next patches much easier, and it's probably better to move more sink CRC logic to the sink CRC function. Signed-off-by: Paulo Zanoni --- tests/kms_frontbuffer_tracking.c | 11

[Intel-gfx] [PATCH igt 1/6] tests/kms_draw_crc: remove unnecessary mode unset calls

I couldn't think of a reason why we would need to unset the CRTCs before doing the modesets on this test, so remove all the mode unset calls. Before: $ time -p sudo ./kms_draw_crc real 44.74 $ time -p for i in $(sudo ./kms_draw_crc --list-subtests); do sudo ./kms_draw_crc --run-subtest $i; done

[Intel-gfx] [PATCH igt 2/6] kms_frontbuffer_tracking: fix sink CRC assertion

If we already detected an error, don't try to assert the size of what we didn't read. In machines where the sink CRC is unreliable, this was failing tests where the sink CRC is not mandatory (FBC tests). With this change we won't fail anymore, we'll just print error messages saying that the sink

Re: [Intel-gfx] [PATCH] drm/i915: Revoke partial fences when installing on the scanout

Em Qui, 2016-12-22 às 13:52 +, Chris Wilson escreveu: > In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT > writes") partial mmaps were updated to indicate that writes through > them > were not tracked automatically by the hardware and that the expected > subsequent manual

[Intel-gfx] [PATCH] drm/i915: request ring to be pinned above GUC_WOPCM_TOP

From: Daniele Ceraolo Spurio GuC will validate the ring offset and fail if it is in the [0, GUC_WOPCM_TOP) range. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Michal Wajdeczko

Re: [Intel-gfx] [PATCH 08/11] drm/i915: Reorganize overlay filter coeffs into a nicer form

On Thu, Dec 08, 2016 at 04:26:41PM +, Chris Wilson wrote: > On Thu, Dec 08, 2016 at 06:17:28PM +0200, Ville Syrjälä wrote: > > On Thu, Dec 08, 2016 at 08:45:31AM +, Chris Wilson wrote: > > > On Wed, Dec 07, 2016 at 07:28:10PM +0200, ville.syrj...@linux.intel.com > > > wrote: > > > > From:

[Intel-gfx] [PATCH v2 11/11] drm/i915: Kill the 830 MI_OVERLAY_OFF workaround

From: Ville Syrjälä Now that we're disabling L2 clock gating MI_OVERLAY_OFF actually works on 830, so let's use it. v2: Nuke the unused dev_priv variable Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_overlay.c | 19

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state()

== Series Details == Series: series starting with [1/2] drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state() URL : https://patchwork.freedesktop.org/series/17135/ State : success == Summary == Series 17135v1 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Daniele Ceraolo Spurio >Sent: Thursday, December 22, 2016 10:45 AM >To: intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the >Global

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt

== Series Details == Series: drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt URL : https://patchwork.freedesktop.org/series/17134/ State : success == Summary == Series 17134v1 drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On 22/12/16 08:38, Arkadiusz Hiler wrote: On Thu, Dec 22, 2016 at 03:18:08PM +, Chris Wilson wrote: On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote: On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote: With enable_guc_loading=2 and enable_guc_submission=0 I

Re: [Intel-gfx] [PATCH] drm/915: Parsing the missed out DTD fields from the VBT

On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote: > From: Vincente Tsou > > The upper bits of the vsync width, vsync offset and hsync width > were not parsed form the VBT. Parse these fields in this patch. > > V2: Renamed lvds dvo timing structure members

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/3] drm/i915: Repeat flush of idle work during suspend

== Series Details == Series: series starting with [1/3] drm/i915: Repeat flush of idle work during suspend URL : https://patchwork.freedesktop.org/series/17131/ State : warning == Summary == Series 17131v1 Series without cover letter

[Intel-gfx] [PATCH] drm/915: Parsing the missed out DTD fields from the VBT

From: Vincente Tsou The upper bits of the vsync width, vsync offset and hsync width were not parsed from the VBT. Parse these fields in this patch. V2: Renamed lvds dvo timing structure members and code identation fix (Jani's review comments) V3: Corrected commit

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Assert that the partial VMA fits within the object

== Series Details == Series: series starting with [1/5] drm/i915: Assert that the partial VMA fits within the object URL : https://patchwork.freedesktop.org/series/17130/ State : failure == Summary == Series 17130v1 Series without cover letter

[Intel-gfx] [PATCH] drm/915: Parsing the missed out DTD fields from the VBT

From: Vincente Tsou The upper bits of the vsync width, vsync offset and hsync width were not parsed form the VBT. Parse these fields in this patch. V2: Renamed lvds dvo timing structure members and code identation fix (Jani's review comments) Signed-off-by: Vincente

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use atomic page flip for intel again.

== Series Details == Series: drm/i915: Use atomic page flip for intel again. URL : https://patchwork.freedesktop.org/series/17129/ State : success == Summary == Series 17129v1 drm/i915: Use atomic page flip for intel again.

[Intel-gfx] [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format

PSR2 vsc revision number hb2( as per table 6-11)is updated to 4 or 5 based on Y cordinate and Colorimetry Format as below 04h = 3D stereo + PSR/PSR2 + Y-coordinate. 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format indication. A DP Source device is allowed to indicate

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On Thu, Dec 22, 2016 at 03:18:08PM +, Chris Wilson wrote: > On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote: > > On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote: > > > With enable_guc_loading=2 and enable_guc_submission=0 I get HuC > > > authentication failure

Re: [Intel-gfx] [PATCH v3 1/2] drm: Wrap the check for atomic_commit implementation

Hi Dhinakaran, [auto build test ERROR on drm/drm-next] [also build test ERROR on next-20161222] [cannot apply to v4.9] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Dhinakaran-Pandiyan/drm

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

> -Original Message- > From: Nikula, Jani > Sent: Thursday, December 22, 2016 7:13 PM > To: Chauhan, Madhav ; intel- > g...@lists.freedesktop.org > Cc: Conselvan De Oliveira, Ander ; > Saarinen, Jani

Re: [Intel-gfx] [PATCH] drm/i915: Revoke partial fences when installing on the scanout

On Thu, Dec 22, 2016 at 01:52:24PM +, Chris Wilson wrote: > In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT > writes") partial mmaps were updated to indicate that writes through them > were not tracked automatically by the hardware and that the expected > subsequent manual

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote: > On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote: > > With enable_guc_loading=2 and enable_guc_submission=0 I get HuC > > authentication failure and with enable_guc_loading and > > enable_guc_submisssion both set to

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote: > With enable_guc_loading=2 and enable_guc_submission=0 I get HuC > authentication failure and with enable_guc_loading and > enable_guc_submisssion both set to 2 the device does not show any > display. Sadly "the fix" fixes the

[Intel-gfx] [PATCH v10] lib: Add a simple prime number generator

Prime numbers are interesting for testing components that use multiplies and divides, such as testing DRM's struct drm_mm alignment computations. v2: Move to lib/, add selftest v3: Fix initial constants (exclude 0/1 from being primes) v4: More RCU markup to keep 0day/sparse happy v5: Fix RCU

Re: [Intel-gfx] [PATCH v2 07/14] drm/i915: Start moving the cdclk stuff into a distinct state structure

On Thu, Dec 22, 2016 at 04:14:40PM +0200, Ander Conselvan De Oliveira wrote: > On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Introduce intel_cdclk state which for now will track the cdclk > > frequency, the

Re: [Intel-gfx] [PATCH v2 07/14] drm/i915: Start moving the cdclk stuff into a distinct state structure

On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Introduce intel_cdclk state which for now will track the cdclk > frequency, the vco frequency and the reference frequency (not sure we > want the last one, but I put

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove the double handling of 'flags from intel_mode_from_pipe_config()

On Thu, Dec 22, 2016 at 04:04:42PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We're trying to copy the flags from the adjusted mode to the > passed in mode twice. Once is enough. > > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Move the min_pixclk[] handling to the end of readout

On Thu, Dec 22, 2016 at 02:10:25PM +0100, Maarten Lankhorst wrote: > Op 20-12-16 om 16:39 schreef ville.syrj...@linux.intel.com: > > From: Ville Syrjälä > > > > Trying to determine the pixel rate of the pipe can't be done until we > > know the clock, which means it

[Intel-gfx] [PATCH 2/2] drm/i915: Remove the double handling of 'flags from intel_mode_from_pipe_config()

From: Ville Syrjälä We're trying to copy the flags from the adjusted mode to the passed in mode twice. Once is enough. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 1 - 1 file changed, 1 deletion(-) diff

[Intel-gfx] [PATCH 1/2] drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state()

From: Ville Syrjälä crtc->config is on its way out. Let's reduce our dependence on it a little bit by removing it from intel_modeset_readout_hw_state(). Also replace crtc->acttive checks with crtc_state->base.active checks. Cc: Maarten Lankhorst

[Intel-gfx] [PATCH] drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt

Since commit db6c2b4151f2 ("drm/i915: Store the vma in an rbtree under the object") the vma are once again sorted into GGTT first, then ppGTT so that the typical case of walking the GGTT vma can stop as soon as we find a non-ppGTT. Apply that optimisation. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Thu, Dec 22, 2016 at 01:57:26PM +0200, David Weinehall wrote: > On Thu, Dec 22, 2016 at 01:49:39PM +0200, Ville Syrjälä wrote: > > On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote: > > > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com > > > wrote: > > > >

[Intel-gfx] [PATCH] drm/i915: Revoke partial fences when installing on the scanout

In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT writes") partial mmaps were updated to indicate that writes through them were not tracked automatically by the hardware and that the expected subsequent manual invalidations by the application (on calling dirtyfb at the end of

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

On Thu, 22 Dec 2016, "Chauhan, Madhav" wrote: >> -Original Message- >> From: Nikula, Jani >> Sent: Thursday, December 22, 2016 5:09 PM >> To: Chauhan, Madhav ; intel- >> g...@lists.freedesktop.org >> Cc: Conselvan De Oliveira, Ander

Re: [Intel-gfx] [PATCH 06/14] drm/i915: Pass computed vco to bxt_set_cdclk()

On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rather than compute the vco inside bxt_set_cdclk() let's precompute it > outside and pass it in. A small step towards a fully precomputed cdclk > state. > >

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

> -Original Message- > From: Nikula, Jani > Sent: Thursday, December 22, 2016 5:09 PM > To: Chauhan, Madhav ; intel- > g...@lists.freedesktop.org > Cc: Conselvan De Oliveira, Ander ; > Saarinen, Jani

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c

On to, 2016-12-22 at 15:10 +0200, Ander Conselvan De Oliveira wrote: > > On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > > > > From: Ville Syrjälä > > > > Let's try to shrink intel_display.c a bit by moving the cdclk/rawclk > > stuff to a

Re: [Intel-gfx] [PATCH] drm/i915: Move the min_pixclk[] handling to the end of readout

Op 20-12-16 om 16:39 schreef ville.syrj...@linux.intel.com: > From: Ville Syrjälä > > Trying to determine the pixel rate of the pipe can't be done until we > know the clock, which means it can't be done until the encoder > .get_config() hooks have been called. So

Re: [Intel-gfx] [PATCH] drm/i915: Move the min_pixclk[] handling to the end of readout

On Tue, 2016-12-20 at 17:39 +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Trying to determine the pixel rate of the pipe can't be done until we > know the clock, which means it can't be done until the encoder > .get_config() hooks have been

Re: [Intel-gfx] [PATCH] drm/i915: Prevent timeline updates whilst performing reset

Chris Wilson writes: > As the fence may be signaled concurrently from an interrupt on another > device, it is possible for the list of requests on the timeline to be > modified as we walk it. Take both (the context's timeline and the global > timeline) locks to prevent

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Don't clflush before release phys object

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > When we teardown the backing storage for the phys object, we copy from > the coherent contiguous block back to the shmemfs object, clflushing as > we go. Trying to clflush the invalid sg beforehand just oops and would > be redundant (due to

Re: [Intel-gfx] [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

On Thu, 22 Dec 2016, Ville Syrjälä wrote: > On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote: >> From: Deepak M >> >> Program the clk lane and tlpx time count registers >> to configure DSI PHY. >> >> v2: Addressed Jani's Review

Re: [Intel-gfx] [PATCH v2] drm/i915/ddi: Rely on VBT DDI port info for eDP detection

On Thu, 2016-12-22 at 11:12 +0200, David Weinehall wrote: > On Wed, Dec 21, 2016 at 12:17:24PM +0200, Imre Deak wrote: > > There is at least one APL based system using port A in DP mode > > (connecting to an on-board DP->VGA adaptor). Atm we'll configure port A > > unconditionally as eDP which is

Re: [Intel-gfx] [PATCH] drm/i915: moved edid read from _force() to _get_modes()

On Wed, Dec 21, 2016 at 02:49:10PM -0800, Anitha Chrisanthus wrote: > From: "Chrisanthus, Anitha" > > When the connector is forced ON and firmware EDID is provided, > driver still tries to read the EDID from the sink device, this can increase > the driver's start up

Re: [Intel-gfx] [PATCH] drm/i915: Beef up the IPS vs. CRC workaround

On Wed, Dec 21, 2016 at 03:04:43PM -0200, Paulo Zanoni wrote: > Em Qua, 2016-12-21 às 11:31 +0200, ville.syrj...@linux.intel.com > escreveu: > > From: Ville Syrjälä > > > > Oneshot disabling of IPS when CRC capturing is started is > > insufficient. > > IPS may get

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Repeat flush of idle work during suspend

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > The idle work handler is self-arming - if it detects that it needs to > run again it will queue itself from its work handler. Take greater care > when trying to drain the idle work, and double check that it is flushed. > > The free worker

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Silence allocation failure during sg_trim()

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > As trimming the sg table is merely an optimisation that gracefully fails > if we cannot allocate a new table, we do not need to report the failure > either. > > Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table") > Signed-off-by:

Re: [Intel-gfx] [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote: > From: Deepak M > > Program the clk lane and tlpx time count registers > to configure DSI PHY. > > v2: Addressed Jani's Review comments(renamed bit field macros) > > Signed-off-by: Deepak M

[Intel-gfx] [PATCH 3/3] drm/i915: Silence allocation failure during sg_trim()

As trimming the sg table is merely an optimisation that gracefully fails if we cannot allocate a new table, we do not need to report the failure either. Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 2/3] drm/i915: Don't clflush before release phys object

When we teardown the backing storage for the phys object, we copy from the coherent contiguous block back to the shmemfs object, clflushing as we go. Trying to clflush the invalid sg beforehand just oops and would be redundant (due to it already being coherent, and clflushed afterwards).

[Intel-gfx] [PATCH 1/3] drm/i915: Repeat flush of idle work during suspend

The idle work handler is self-arming - if it detects that it needs to run again it will queue itself from its work handler. Take greater care when trying to drain the idle work, and double check that it is flushed. The free worker has a similar issue where it is armed by an RCU task which may be

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Thu, Dec 22, 2016 at 01:49:39PM +0200, Ville Syrjälä wrote: > On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote: > > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > >

Re: [Intel-gfx] [PATCH v3 1/3] drm: Create new structure for HDMI info

On Thu, Dec 22, 2016 at 10:02:26AM +, Jose Abreu wrote: > Hi Shashank, > > > On 21-12-2016 15:29, Shashank Sharma wrote: > > [snip] > > > + > > + /** > > +* @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding. > > +* various sinks can support 10/12/16 bit per channel deep >

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Assert that the partial VMA fits within the object

Hi Chris, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20161222] [cannot apply to v4.9] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote: > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Apparently some VLV BIOSen like to leave the VDD force bit enabled > > even for power

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

On Thu, 15 Dec 2016, Madhav Chauhan wrote: > From: Vincente Tsou > > The upper bits of the vsync width, vsync offset and hsync width > were not parsed form the VBT. Parse these fields in this patch. > > Signed-off-by: Madhav Chauhan

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Convert i915_ggtt_view to use an anonymous union

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > Save a lot of characters by making the union anonymous, with the > side-effect of ignoring unset bits when comparing views. > > Signed-off-by: Chris Wilson Daniel could A-b, as he specifically wanted all the bits

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > It is only being used to clear a struct and set the type, after which it > is overwritten. Since we no longer check the unset bits of the union, > skipping the clear is permissible. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v3] drm/i915: Check HAS_PCH_NOP when install or reset dispaly IRQ

On Thu, Dec 22, 2016 at 10:52:29AM +0200, Jani Nikula wrote: > On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > >> > >> On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > >> > Hi Jani, Ville, > >> > > >> > Any comment about the "PCH_NOP" vs "num_pipes == 0"?

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Extact compute_partial_view()

Patch title, s/Extact/Extract/ On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > In order to reuse the partial view for selftesting, extract the common > function for computing the view. > > Signed-off-by: Chris Wilson With that; Reviewed-by: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: program vsc header for psr2

On Wed, 21 Dec 2016, vathsala nagaraju wrote: > Function hsw_psr_setup handles vsc header setup for psr1 and > skl_psr_setup_vsc handles vsc header setup for psr2. > > Setup VSC header in function skl_psr_setup_vsc for psr2 support, > as per edp 1.4 spec, table

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Eliminate superfluous i915_ggtt_view_normal

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only > one user of i915_ggtt_view_normal rodate. Just treat NULL as no special > view in pin_to_display() like everywhere else. > > Signed-off-by: Chris Wilson

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