On Fri, Dec 23, 2016 at 01:46:36PM +0800, changbin...@intel.com wrote:
> From: "Du, Changbin"
>
> This patch fix a crash in function reset_common_ring. In this case,
> the port[0].request is null when reset the render ring, so a null
> dereference exception is raised. We need to check execlist_po
I have addressed review comments that Petri, Jim had for this patch along with
making some small changes for error handling. The functionality is mostly
unchanged from Manasi's version.
-DK
From: Pandiyan, Dhinakaran
Sent: Thursday, December 22, 2016 11:4
On Thu, Dec 22, 2016 at 03:15:03PM -0800, Daniele Ceraolo Spurio wrote:
>
>
> On 22/12/16 14:23, Patchwork wrote:
> >== Series Details ==
> >
> >Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP
> >URL : https://patchwork.freedesktop.org/series/17147/
> >State : failure
> >
> >==
From: "Navare, Manasi D"
This is the userspace component of the Displayport Compliance
testing software required for compliance testing of the I915
Display Port driver. This must be running in order to successfully
complete Display Port compliance testing. This app and the kernel
code that accomp
On Fri, 23 Dec 2016, changbin...@intel.com wrote:
> From: "Du, Changbin"
>
> This patch fix a crash in function reset_common_ring. In this case,
> the port[0].request is null when reset the render ring, so a null
> dereference exception is raised. We need to check execlist_port status
> first.
>
>
On Thu, 22 Dec 2016, Ville Syrjälä wrote:
> On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote:
>> From: Vincente Tsou
>>
>> The upper bits of the vsync width, vsync offset and hsync width
>> were not parsed form the VBT. Parse these fields in this patch.
>>
>> V2: Renamed lvds dvo
== Series Details ==
Series: drm/i915: Respect num_pipes when install or reset display IRQ
URL : https://patchwork.freedesktop.org/series/17164/
State : warning
== Summary ==
Series 17164v1 drm/i915: Respect num_pipes when install or reset display IRQ
https://patchwork.freedesktop.org/api/1.0/
On 2016年12月23日 13:57, Rob Clark wrote:
On Thu, Dec 22, 2016 at 11:07 PM, Mark yao wrote:
Hi Chris Wilson
We port drm_mm to my internal kernel, with high load test, found following
crash:
[49451.856244]
==
[49451.856350] BUG: KASA
== Series Details ==
Series: drm/i915: check if execlist_port is empty before using its content
URL : https://patchwork.freedesktop.org/series/17162/
State : success
== Summary ==
Series 17162v1 drm/i915: check if execlist_port is empty before using its
content
https://patchwork.freedesktop.o
From: Elaine Wang
Some platforms don't have display. To avoid accessing the
non-existent display interrupt registers, check whether num_pipes
isn't zero before invoking display IRQ install or reset function.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jani Nikula
Signed-off-by: Elaine Wang
---
On Thu, Dec 22, 2016 at 11:07 PM, Mark yao wrote:
> Hi Chris Wilson
>
> We port drm_mm to my internal kernel, with high load test, found following
> crash:
>
> [49451.856244]
> ==
> [49451.856350] BUG: KASAN: wild-memory-access on add
Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.
Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.
v2: (Jani)
- Initialize variables to 0
-
From: "Du, Changbin"
This patch fix a crash in function reset_common_ring. In this case,
the port[0].request is null when reset the render ring, so a null
dereference exception is raised. We need to check execlist_port status
first.
[ 35.748034] BUG: unable to handle kernel NULL pointer derefe
Hi Chris Wilson
We port drm_mm to my internal kernel, with high load test, found
following crash:
[49451.856244] ==
[49451.856350] BUG: KASAN: wild-memory-access on address dead
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, December 22, 2016 6:48 PM
> To: Wang, Elaine ; intel-gfx@lists.freedesktop.org;
> Wang, Elaine
> Cc: Chris Wilson ; Joonas Lahtinen
>
> Subject: Re: [PATCH v2 2/2] drm/i915: Check num_pipes bef
Regards
Shashank
On 12/22/2016 5:26 PM, Ville Syrjälä wrote:
On Thu, Dec 22, 2016 at 10:02:26AM +, Jose Abreu wrote:
Hi Shashank,
On 21-12-2016 15:29, Shashank Sharma wrote:
[snip]
+
+ /**
+* @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding.
+* various
== Series Details ==
Series: HuC Loading Patches
URL : https://patchwork.freedesktop.org/series/17150/
State : success
== Summary ==
Series 17150v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/17150/revisions/1/mbox/
fi-bdw-5557u total:246 pass:232 dwarn:0 dfa
On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote:
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
On 22/12/16 14:23, Patchwork wrote:
== Series Details ==
Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP
URL : https://patchwork.freedesktop.org/series/17147/
State : failure
== Summary ==
Series 17147v1 drm/i915: request ring to be pinned above GUC_WOPCM_TOP
https://patchw
From: Peter Antoine
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased on top of drm-tip
v12: rebased.
v13: rebased.
Tested-by: Xiang Haihao
Signed-off-by: Anusha Srivatsa
This patch adds the support to load HuC on KBL
Version 2.0
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
v5: rebased. Rename KBL_FW_ to KBL_HUC_FW_
v6: rebased. Remove old checks.
Cc: Tvrtko Ursulin
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_loader.c | 13 +
From: Peter Antoine
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5:
From: Peter Antoine
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after i
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon
This patch adds the HuC Loading for the BXT by using
the updated file construction.
Version 1.7 of the HuC firmware.
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
v5: rebased. Rename BXT_FW_MAJOR to BXT_HUC_FW_
v6: rebased.
Cc: Tvrtko Ursulin
Signed-off-by: Anusha Srivatsa
---
drive
From: Peter Antoine
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw'
From: Peter Antoine
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drm-intel-nigh
These patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if
== Series Details ==
Series: drm/i915: request ring to be pinned above GUC_WOPCM_TOP
URL : https://patchwork.freedesktop.org/series/17147/
State : failure
== Summary ==
Series 17147v1 drm/i915: request ring to be pinned above GUC_WOPCM_TOP
https://patchwork.freedesktop.org/api/1.0/series/17147
On Thu, Dec 22, 2016 at 09:52:22PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Now that we're disabling L2 clock gating MI_OVERLAY_OFF actually works
> on 830, so let's use it.
>
> v2: Nuke the unused dev_priv variable
>
> Signed-off-by: Ville Syrjälä
Does what it sa
== Series Details ==
Series: drm/915: Parsing the missed out DTD fields from the VBT (rev2)
URL : https://patchwork.freedesktop.org/series/17142/
State : success
== Summary ==
Series 17142v2 drm/915: Parsing the missed out DTD fields from the VBT
https://patchwork.freedesktop.org/api/1.0/serie
On Thu, Dec 22, 2016 at 06:39:39PM -0200, Paulo Zanoni wrote:
> Em Qui, 2016-12-22 às 13:52 +, Chris Wilson escreveu:
> > In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT
> > writes") partial mmaps were updated to indicate that writes through
> > them
> > were not tracked au
>-Original Message-
>From: Ceraolo Spurio, Daniele
>Sent: Thursday, December 22, 2016 11:55 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Ceraolo Spurio, Daniele ; Chris Wilson
>; Wajdeczko, Michal ;
>Hiler, Arkadiusz ; Srivatsa, Anusha
>; Winiarski, Michal
>Subject: [PATCH] drm/i915: req
== Series Details ==
Series: series starting with [v4,01/38] drm/i915: Use the MRU stack search
after evicting (rev2)
URL : https://patchwork.freedesktop.org/series/17123/
State : success
== Summary ==
Series 17123v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series
What I'm currently seeing is that sometimes the first check during
setup_sink_crc() returns valid sink CRC, but then the subsequent
checks return ETIMEDOUT. In these cases, we keep getting flooded by
messages saying that our sink CRC is unreliable and that the results
differ. This is annoying for t
Don't just destroy the ones from the default format.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 8aa6362..b85f56b 100644
--- a/te
Ever since Kernel's "drm/i915: don't report compression when fbc is
disabled" we've been wrongly assuming that the Kernel doesn't support
compression information due to the fact that it doesn't print that
specific line when FBC is not active. Fix this by just assuming that
the Kernel supports it, a
Make it check for the supported flag and decide what to do. This
change will make the next patches much easier, and it's probably
better to move more sink CRC logic to the sink CRC function.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 11 ++-
1 file changed, 6 inse
I couldn't think of a reason why we would need to unset the CRTCs
before doing the modesets on this test, so remove all the mode unset
calls.
Before:
$ time -p sudo ./kms_draw_crc
real 44.74
$ time -p for i in $(sudo ./kms_draw_crc --list-subtests); do sudo
./kms_draw_crc --run-subtest $i; done
re
If we already detected an error, don't try to assert the size of what
we didn't read.
In machines where the sink CRC is unreliable, this was failing tests
where the sink CRC is not mandatory (FBC tests). With this change we
won't fail anymore, we'll just print error messages saying that the
sink C
Em Qui, 2016-12-22 às 13:52 +, Chris Wilson escreveu:
> In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT
> writes") partial mmaps were updated to indicate that writes through
> them
> were not tracked automatically by the hardware and that the expected
> subsequent manual in
From: Daniele Ceraolo Spurio
GuC will validate the ring offset and fail if it is in the
[0, GUC_WOPCM_TOP) range.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Arkadiusz Hiler
Cc: Anusha Srivatsa
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/intel_ringbuf
On Thu, Dec 08, 2016 at 04:26:41PM +, Chris Wilson wrote:
> On Thu, Dec 08, 2016 at 06:17:28PM +0200, Ville Syrjälä wrote:
> > On Thu, Dec 08, 2016 at 08:45:31AM +, Chris Wilson wrote:
> > > On Wed, Dec 07, 2016 at 07:28:10PM +0200, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From:
From: Ville Syrjälä
Now that we're disabling L2 clock gating MI_OVERLAY_OFF actually works
on 830, so let's use it.
v2: Nuke the unused dev_priv variable
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_overlay.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletio
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove crtc->config usage from
intel_modeset_readout_hw_state()
URL : https://patchwork.freedesktop.org/series/17135/
State : success
== Summary ==
Series 17135v1 Series without cover letter
https://patchwork.freedesktop.org/ap
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Daniele Ceraolo Spurio
>Sent: Thursday, December 22, 2016 10:45 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the
>Global
== Series Details ==
Series: drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt
URL : https://patchwork.freedesktop.org/series/17134/
State : success
== Summary ==
Series 17134v1 drm/i915: Break after walking all GGTT vma in bump_inactive_ggtt
https://patchwork.freedesktop.org/ap
On 22/12/16 08:38, Arkadiusz Hiler wrote:
On Thu, Dec 22, 2016 at 03:18:08PM +, Chris Wilson wrote:
On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote:
On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote:
With enable_guc_loading=2 and enable_guc_submission=0 I ge
On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote:
> From: Vincente Tsou
>
> The upper bits of the vsync width, vsync offset and hsync width
> were not parsed form the VBT. Parse these fields in this patch.
>
> V2: Renamed lvds dvo timing structure members and code identation
> fix
== Series Details ==
Series: series starting with [1/3] drm/i915: Repeat flush of idle work during
suspend
URL : https://patchwork.freedesktop.org/series/17131/
State : warning
== Summary ==
Series 17131v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17131/revi
From: Vincente Tsou
The upper bits of the vsync width, vsync offset and hsync width
were not parsed from the VBT. Parse these fields in this patch.
V2: Renamed lvds dvo timing structure members and code identation
fix (Jani's review comments)
V3: Corrected commit message, used "from the VBT"
Si
== Series Details ==
Series: series starting with [1/5] drm/i915: Assert that the partial VMA fits
within the object
URL : https://patchwork.freedesktop.org/series/17130/
State : failure
== Summary ==
Series 17130v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/
From: Vincente Tsou
The upper bits of the vsync width, vsync offset and hsync width
were not parsed form the VBT. Parse these fields in this patch.
V2: Renamed lvds dvo timing structure members and code identation
fix (Jani's review comments)
Signed-off-by: Vincente Tsou
Signed-off-by: Madhav
== Series Details ==
Series: drm/i915: Use atomic page flip for intel again.
URL : https://patchwork.freedesktop.org/series/17129/
State : success
== Summary ==
Series 17129v1 drm/i915: Use atomic page flip for intel again.
https://patchwork.freedesktop.org/api/1.0/series/17129/revisions/1/mbo
PSR2 vsc revision number hb2( as per table 6-11)is updated to
4 or 5 based on Y cordinate and Colorimetry Format as below
04h = 3D stereo + PSR/PSR2 + Y-coordinate.
05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
Format indication. A DP Source device is allowed to indicate
On Thu, Dec 22, 2016 at 03:18:08PM +, Chris Wilson wrote:
> On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote:
> > On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote:
> > > With enable_guc_loading=2 and enable_guc_submission=0 I get HuC
> > > authentication failure a
Hi Dhinakaran,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on next-20161222]
[cannot apply to v4.9]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Dhinakaran-Pandiyan/drm
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, December 22, 2016 7:13 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander ;
> Saarinen, Jani ; Konduru, Chandra
> ; Shankar, Uma ;
> Mukherjee, Indranil ; Kumar, Shobhit
> ; Tsou, Vinc
On Thu, Dec 22, 2016 at 01:52:24PM +, Chris Wilson wrote:
> In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT
> writes") partial mmaps were updated to indicate that writes through them
> were not tracked automatically by the hardware and that the expected
> subsequent manual
On Thu, Dec 22, 2016 at 03:53:15PM +0100, Arkadiusz Hiler wrote:
> On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote:
> > With enable_guc_loading=2 and enable_guc_submission=0 I get HuC
> > authentication failure and with enable_guc_loading and
> > enable_guc_submisssion both set to
On Wed, Dec 21, 2016 at 07:35:04PM +0100, Srivatsa, Anusha wrote:
> With enable_guc_loading=2 and enable_guc_submission=0 I get HuC
> authentication failure and with enable_guc_loading and
> enable_guc_submisssion both set to 2 the device does not show any
> display.
Sadly "the fix" fixes the issu
Prime numbers are interesting for testing components that use multiplies
and divides, such as testing DRM's struct drm_mm alignment computations.
v2: Move to lib/, add selftest
v3: Fix initial constants (exclude 0/1 from being primes)
v4: More RCU markup to keep 0day/sparse happy
v5: Fix RCU unwin
On Thu, Dec 22, 2016 at 04:14:40PM +0200, Ander Conselvan De Oliveira wrote:
> On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Introduce intel_cdclk state which for now will track the cdclk
> > frequency, the vco frequency and the reference
On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Introduce intel_cdclk state which for now will track the cdclk
> frequency, the vco frequency and the reference frequency (not sure we
> want the last one, but I put it there anyway). We'll also make
On Thu, Dec 22, 2016 at 04:04:42PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We're trying to copy the flags from the adjusted mode to the
> passed in mode twice. Once is enough.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Int
On Thu, Dec 22, 2016 at 02:10:25PM +0100, Maarten Lankhorst wrote:
> Op 20-12-16 om 16:39 schreef ville.syrj...@linux.intel.com:
> > From: Ville Syrjälä
> >
> > Trying to determine the pixel rate of the pipe can't be done until we
> > know the clock, which means it can't be done until the encoder
From: Ville Syrjälä
We're trying to copy the flags from the adjusted mode to the
passed in mode twice. Once is enough.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/dr
From: Ville Syrjälä
crtc->config is on its way out. Let's reduce our dependence on it a
little bit by removing it from intel_modeset_readout_hw_state().
Also replace crtc->acttive checks with crtc_state->base.active checks.
Cc: Maarten Lankhorst
Suggested-by: Maarten Lankhorst
Signed-off-by:
Since commit db6c2b4151f2 ("drm/i915: Store the vma in an rbtree under
the object") the vma are once again sorted into GGTT first, then ppGTT
so that the typical case of walking the GGTT vma can stop as soon as we
find a non-ppGTT. Apply that optimisation.
Signed-off-by: Chris Wilson
Cc: Tvrtko U
On Thu, Dec 22, 2016 at 01:57:26PM +0200, David Weinehall wrote:
> On Thu, Dec 22, 2016 at 01:49:39PM +0200, Ville Syrjälä wrote:
> > On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote:
> > > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com
> > > wrote:
> > > >
In commit 50349247ea80 ("drm/i915: Drop ORIGIN_GTT for untracked GTT
writes") partial mmaps were updated to indicate that writes through them
were not tracked automatically by the hardware and that the expected
subsequent manual invalidations by the application (on calling dirtyfb at
the end of the
On Thu, 22 Dec 2016, "Chauhan, Madhav" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, December 22, 2016 5:09 PM
>> To: Chauhan, Madhav ; intel-
>> g...@lists.freedesktop.org
>> Cc: Conselvan De Oliveira, Ander ;
>> Saarinen, Jani ; Konduru, Chandra
>> ; Shankar, Uma
On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Rather than compute the vco inside bxt_set_cdclk() let's precompute it
> outside and pass it in. A small step towards a fully precomputed cdclk
> state.
>
> Signed-off-by: Ville Syrjälä
Reviewed-b
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, December 22, 2016 5:09 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander ;
> Saarinen, Jani ; Konduru, Chandra
> ; Shankar, Uma ;
> Mukherjee, Indranil ; Kumar, Shobhit
> ; Tsou, Vinc
On to, 2016-12-22 at 15:10 +0200, Ander Conselvan De Oliveira wrote:
> > On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote:
> >
> > From: Ville Syrjälä
> >
> > Let's try to shrink intel_display.c a bit by moving the cdclk/rawclk
> > stuff to a new file. It's all reasonably s
Op 20-12-16 om 16:39 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> Trying to determine the pixel rate of the pipe can't be done until we
> know the clock, which means it can't be done until the encoder
> .get_config() hooks have been called. So let's move the min_pixclk[]
> stuf
On Tue, 2016-12-20 at 17:39 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Trying to determine the pixel rate of the pipe can't be done until we
> know the clock, which means it can't be done until the encoder
> .get_config() hooks have been called. So let's move the min_pi
Chris Wilson writes:
> As the fence may be signaled concurrently from an interrupt on another
> device, it is possible for the list of requests on the timeline to be
> modified as we walk it. Take both (the context's timeline and the global
> timeline) locks to prevent such modifications.
>
> Fix
On to, 2016-12-22 at 12:00 +, Chris Wilson wrote:
> When we teardown the backing storage for the phys object, we copy from
> the coherent contiguous block back to the shmemfs object, clflushing as
> we go. Trying to clflush the invalid sg beforehand just oops and would
> be redundant (due to it
On Thu, 22 Dec 2016, Ville Syrjälä wrote:
> On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote:
>> From: Deepak M
>>
>> Program the clk lane and tlpx time count registers
>> to configure DSI PHY.
>>
>> v2: Addressed Jani's Review comments(renamed bit field macros)
>>
>> Signed-off-
On Thu, 2016-12-22 at 11:12 +0200, David Weinehall wrote:
> On Wed, Dec 21, 2016 at 12:17:24PM +0200, Imre Deak wrote:
> > There is at least one APL based system using port A in DP mode
> > (connecting to an on-board DP->VGA adaptor). Atm we'll configure port A
> > unconditionally as eDP which is i
On Wed, Dec 21, 2016 at 02:49:10PM -0800, Anitha Chrisanthus wrote:
> From: "Chrisanthus, Anitha"
>
> When the connector is forced ON and firmware EDID is provided,
> driver still tries to read the EDID from the sink device, this can increase
> the driver's start up time by ~25ms per attempt.
> T
On Wed, Dec 21, 2016 at 03:04:43PM -0200, Paulo Zanoni wrote:
> Em Qua, 2016-12-21 às 11:31 +0200, ville.syrj...@linux.intel.com
> escreveu:
> > From: Ville Syrjälä
> >
> > Oneshot disabling of IPS when CRC capturing is started is
> > insufficient.
> > IPS may get re-enabled by any plane update,
On to, 2016-12-22 at 12:00 +, Chris Wilson wrote:
> The idle work handler is self-arming - if it detects that it needs to
> run again it will queue itself from its work handler. Take greater care
> when trying to drain the idle work, and double check that it is flushed.
>
> The free worker has
On to, 2016-12-22 at 12:00 +, Chris Wilson wrote:
> As trimming the sg table is merely an optimisation that gracefully fails
> if we cannot allocate a new table, we do not need to report the failure
> either.
>
> Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
> Signed-off-by: Chris
On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote:
> From: Deepak M
>
> Program the clk lane and tlpx time count registers
> to configure DSI PHY.
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
>
> Signed-off-by: Deepak M
> Signed-off-by: Madhav Chauhan
> ---
As trimming the sg table is merely an optimisation that gracefully fails
if we cannot allocate a new table, we do not need to report the failure
either.
Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c
When we teardown the backing storage for the phys object, we copy from
the coherent contiguous block back to the shmemfs object, clflushing as
we go. Trying to clflush the invalid sg beforehand just oops and would
be redundant (due to it already being coherent, and clflushed
afterwards).
Reported-
The idle work handler is self-arming - if it detects that it needs to
run again it will queue itself from its work handler. Take greater care
when trying to drain the idle work, and double check that it is flushed.
The free worker has a similar issue where it is armed by an RCU task
which may be r
On Thu, Dec 22, 2016 at 01:49:39PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote:
> > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > Apparently some VLV BIOSen like to leave
On Thu, Dec 22, 2016 at 10:02:26AM +, Jose Abreu wrote:
> Hi Shashank,
>
>
> On 21-12-2016 15:29, Shashank Sharma wrote:
>
> [snip]
>
> > +
> > + /**
> > +* @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding.
> > +* various sinks can support 10/12/16 bit per channel deep
>
Hi Chris,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20161222]
[cannot apply to v4.9]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm
On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote:
> On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Apparently some VLV BIOSen like to leave the VDD force bit enabled
> > even for power seqeuncers that aren't properly h
On Thu, 15 Dec 2016, Madhav Chauhan wrote:
> From: Vincente Tsou
>
> The upper bits of the vsync width, vsync offset and hsync width
> were not parsed form the VBT. Parse these fields in this patch.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Vincente Tsou
The author Signed-off-by shoul
On to, 2016-12-22 at 10:56 +, Chris Wilson wrote:
> Save a lot of characters by making the union anonymous, with the
> side-effect of ignoring unset bits when comparing views.
>
> Signed-off-by: Chris Wilson
Daniel could A-b, as he specifically wanted all the bits initialized.
> +++ b/dri
On to, 2016-12-22 at 10:56 +, Chris Wilson wrote:
> It is only being used to clear a struct and set the type, after which it
> is overwritten. Since we no longer check the unset bits of the union,
> skipping the clear is permissible.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtin
On Thu, Dec 22, 2016 at 10:52:29AM +0200, Jani Nikula wrote:
> On Thu, 22 Dec 2016, "Wang, Elaine" wrote:
> >>
> >> On Thu, 22 Dec 2016, "Wang, Elaine" wrote:
> >> > Hi Jani, Ville,
> >> >
> >> > Any comment about the "PCH_NOP" vs "num_pipes == 0"?
> >> >
> >> > Thanks,
> >> > Elaine
> >> >> On
Patch title, s/Extact/Extract/
On to, 2016-12-22 at 10:56 +, Chris Wilson wrote:
> In order to reuse the partial view for selftesting, extract the common
> function for computing the view.
>
> Signed-off-by: Chris Wilson
With that;
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas
On Wed, 21 Dec 2016, vathsala nagaraju wrote:
> Function hsw_psr_setup handles vsc header setup for psr1 and
> skl_psr_setup_vsc handles vsc header setup for psr2.
>
> Setup VSC header in function skl_psr_setup_vsc for psr2 support,
> as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for ps
On to, 2016-12-22 at 10:56 +, Chris Wilson wrote:
> Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only
> one user of i915_ggtt_view_normal rodate. Just treat NULL as no special
> view in pin_to_display() like everywhere else.
>
> Signed-off-by: Chris Wilson
I had this qu
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