On Sat, 07 Jan 2017, Yadav Jyoti wrote:
> From: Jenkins Val
>
This place here is for the commit message, where you should explain
*why* we need this change.
Where do you get the XML file? Do you write it manually? How do you
manage them? The kernel will execute the sequences from the VBT, not
f
From: Uma Shankar
In case of DSI, DDI PLL is not required.
Handle the same as part of DDI PLL handling.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
mode change 100644 => 100755 drivers/gpu/drm/
Fix the Sequence to program BXT DSI Latch and ULPS.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 23 +--
1 file changed, 5 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 27d8f95..5fa0
From: Uma Shankar
Panel GPIO control should be done based on platform. Add a check
to restrict VLV and CHT specific GPIO confirguration, so that
they dont apply to other platforms.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
Panel Power On/Off sequences are part of Panel spec.
Enabling the support of same in DRM layer for fine grained
panel control.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_
From: Uma Shankar
MIPI Video Mode for high res panels (requiring dual link), need a
8X/3 divider to be programmed as 0x2. Modifying the same
in this patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
di
From: Uma Shankar
Disable device ready before MIPI port shutdown command.
This helps to avoid mipi split screen issues.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gp
Panel Power On/Off sequences are part of Panel spec.
These are present in VBT v3 of the Intel VBT spec.
Enabling the support of same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i9
Add the call back for MIPI reset sequence in drm for
fine grained panel control. This is needed to
reset the panel based on the panel schematics.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/
From: Uma Shankar
Enable support for BXT DSI dual link mode.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_dsi.c | 27 ++-
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_
From: Uma Shankar
Fix BXT DSI disable sequence as per latest updates in BSpec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/dr
Enable the call back for MIPI reset sequence. This is needed to
reset the panel, and is part of the VBT spec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 6 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 9 -
2 files changed, 14 insertions(+), 1 delet
From: Uma Shankar
Enable MIPI IO WA for BXT DSI as per bspec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_dsi.c | 9 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg
Add the support for backlight sequences in drm layer
to configure the backlight settings during
backlight on/off sequences.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_pan
Enable the support for backlight sequences to configure
backlight settings based on VBT Backlight on/off sequence.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16
2 files changed, 18 insertions(+
Check if ppgtt is valid for context when init reg state. For gvt
context which has no i915 allocated ppgtt, failed to check that
would cause kernel null ptr reference error.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/intel_lrc.c | 28 +++-
1 file changed, 15 inse
Hi all,
More 4.11 stuff, holidays edition (i.e. not much):
- docs and cleanups for shared dpll code (Ander)
- some kerneldoc work (Chris)
- fbc by default on gen9+ too, yeah! (Paulo)
- fixes, polish and other small things all over gem code (Chris)
- and a few small things on top
Plus a backmerge
== Series Details ==
Series: series starting with [1/3] drm/i915/DMC/GLK: Load DMC on GLK
URL : https://patchwork.freedesktop.org/series/16926/
State : success
== Summary ==
Series 16926v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/16926/revisions/1/mbox/
fi
On Thu, Jan 05, 2017 at 11:03:44AM -0800, Dave Hansen wrote:
> My Thinkpad x260 doesn't like to be unplugged from its dock. I don't
> think this is a new bug. It's happening on my distro's 4.4 kernel
> as well.
>
> The actual oops is in device_del(). It appears to have been passed a
> null 'str
On Mon, 09 Jan 2017, Vidya Srinivas wrote:
> From: Uma Shankar
>
> Panel GPIO control should be done based on platform. Add a check
> to restrict VLV and CHT specific GPIO confirguration, so that
> they dont apply to other platforms.
There are no code paths that would have
dev_priv->vbt.dsi.conf
On Mon, 09 Jan 2017, Vidya Srinivas wrote:
> Panel Power On/Off sequences are part of Panel spec.
> Enabling the support of same in DRM layer for fine grained
> panel control.
http://lkml.kernel.org/r/20160302152549.ga21...@ulmo.nvidia.com
>
> Signed-off-by: Uma Shankar
> ---
> include/drm/drm
On a non-llc system, the objects are created with .cache_level =
CACHE_NONE and so the transition to uncached for scanout is a no-op.
However, if the object was never written to, it will still be in the CPU
domain (having been zeroed out by shmemfs). Those cachelines need to be
flushed prior to dis
On Mon, Jan 09, 2017 at 10:24:01AM +, Chris Wilson wrote:
> On a non-llc system, the objects are created with .cache_level =
> CACHE_NONE and so the transition to uncached for scanout is a no-op.
> However, if the object was never written to, it will still be in the CPU
> domain (having been ze
On a non-llc system, the objects are created with .cache_level =
CACHE_NONE and so the transition to uncached for scanout is a no-op.
However, if the object was never written to, it will still be in the CPU
domain (having been zeroed out by shmemfs). Those cachelines need to be
flushed prior to dis
On to, 2016-12-22 at 13:58 +, Chris Wilson wrote:
> Since commit db6c2b4151f2 ("drm/i915: Store the vma in an rbtree under
> the object") the vma are once again sorted into GGTT first, then ppGTT
> so that the typical case of walking the GGTT vma can stop as soon as we
> find a non-ppGTT. Apply
Patch subject still needs s/Extact/Extract/.
Regards, Joonas
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> In order to reuse the partial view for selftesting, extract the common
> function for computing the view.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Joonas Lahtinen
--
Joon
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Restricting the fence to the end of the previous tile-row breaks access
> to the final portion of the object. On gen2/3 we employed lazy fencing
> to pad out the fence with scratch page to provide access to the tail,
> and now we also pad out
== Series Details ==
Series: drm/i915: check ppgtt validity when init reg state
URL : https://patchwork.freedesktop.org/series/17691/
State : success
== Summary ==
Series 17691v1 drm/i915: check ppgtt validity when init reg state
https://patchwork.freedesktop.org/api/1.0/series/17691/revisions
On Mon, Jan 09, 2017 at 05:16:01PM +0800, Zhenyu Wang wrote:
> Check if ppgtt is valid for context when init reg state. For gvt
> context which has no i915 allocated ppgtt, failed to check that
> would cause kernel null ptr reference error.
>
> Signed-off-by: Zhenyu Wang
Bah, we could remove the
On Mon, Jan 09, 2017 at 01:46:52PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> > Restricting the fence to the end of the previous tile-row breaks access
> > to the final portion of the object. On gen2/3 we employed lazy fencing
> > to pad out the fence wi
Hi,
On 20/12/2016 13:42, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Rather than freeing and re-allocating the pages when DMA mapping
in large chunks fails, we can just rebuild the sg table with no
coalescing.
Also change back the page counter to unsigned int because that
is what the sg API s
On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 20/12/2016 13:42, Tvrtko Ursulin wrote:
> >From: Tvrtko Ursulin
> >
> >Rather than freeing and re-allocating the pages when DMA mapping
> >in large chunks fails, we can just rebuild the sg table with no
> >coalescing.
-Srinivas/drm-i915-Check-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
On 09/01/2017 12:28, Chris Wilson wrote:
On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
Hi,
On 20/12/2016 13:42, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Rather than freeing and re-allocating the pages when DMA mapping
in large chunks fails, we can just rebuild the sg ta
-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
rule.
includ
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_S
On 01/09/2017 02:15 AM, Daniel Vetter wrote:
...
> Can you pls do some printk tracing to make sure that without your patch
> we're indeed releasing the same connector twice from this loop? I suspect
> you're just ever-so-slightly shifting the timing and things blow up
> somewhre else. But no idea w
== Series Details ==
Series: drm/i915: Flush untouched framebuffers before display on !llc
URL : https://patchwork.freedesktop.org/series/17694/
State : failure
== Summary ==
^
drivers/gpu/drm/i915/i915_gem.c:2301:2: note: in expansion of macro ‘GEM_BUG_ON’
GEM_BUG_
On Mon, Jan 09, 2017 at 12:40:07PM +, Tvrtko Ursulin wrote:
>
> On 09/01/2017 12:28, Chris Wilson wrote:
> >On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
> >>
> >>Hi,
> >>
> >>On 20/12/2016 13:42, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin
> >>>
> >>>Rather than freeing
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
psr2 enable sequence.
Program Transcoder EDP VSC DIP header with a valid setting for PSR2
and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header
packet.
Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
v2
Check if ppgtt is valid for context when init reg state. For gvt
context which has no i915 allocated ppgtt, failed to check that
would cause kernel null ptr reference error.
v2: remove !48bit ppgtt case as we'll always update before submit (Chris)
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Ensure the view occupies the full tile row so that reads/writes into the
> VMA do not escape (via fenced detiling) into neighbouring objects - we
> will pad the object with scratch pages to satisfy the fence. This
> applies the lazy-tiling we
On Mon, Jan 09, 2017 at 09:14:53PM +0800, Zhenyu Wang wrote:
> Check if ppgtt is valid for context when init reg state. For gvt
> context which has no i915 allocated ppgtt, failed to check that
> would cause kernel null ptr reference error.
>
> v2: remove !48bit ppgtt case as we'll always update b
On Mon, Jan 09, 2017 at 03:21:43PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> > Ensure the view occupies the full tile row so that reads/writes into the
> > VMA do not escape (via fenced detiling) into neighbouring objects - we
> > will pad the object wi
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> All of these conditions are prechecked by i915_tiling_ok() before we
> allow setting the tiling/stride on the object and so we should never
> fail asserting those conditions before writing the register.
>
> Signed-off-by: Chris Wilson
Spott
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm_connector_register(), which
fails to add the kobject (warning below). But, it does zero error
checking on the drm_connector_register() call and leaves the
partially-constructed connector in place.
The next time
-Srinivas/drm-i915-Check-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
On 01/09/2017 05:40 AM, Dave Hansen wrote:
> Is there some stable code to go back to here? Or, is there something
> about my configuration that's unique? I really wonder why nobody else
> is running into this.
Here are a couple of similar-looking reports, if that helps:
https://bugzilla.redhat.
-untouched-framebuffers-before-display-on-llc/20170109-190816
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s3-01092001 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
== Series Details ==
Series: drm/i915: check ppgtt validity when init reg state (rev2)
URL : https://patchwork.freedesktop.org/series/17691/
State : warning
== Summary ==
Series 17691v2 drm/i915: check ppgtt validity when init reg state
https://patchwork.freedesktop.org/api/1.0/series/17691/re
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
Commit message missing.
> Signed-off-by: Chris Wilson
> @@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct
> drm_i915_gem_object *obj,
> int i915_gem_open(struct drm_device *dev, struct drm_file *file);
> void i915_gem_relea
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> The VMA is later clipped against the vm_area_struct before insertion of
> the faulting PTE so we are free to create the partial view as we desire.
> If we use the object as the extents rather than the area, this partial
> can then be used for
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Since the partial offset must be page aligned, we can use those low 12
> bits to encode the size of the partial view (which then cannot be larger
> than 8MiB in pages).
>
> Signed-off-by: Chris Wilson
Lets just not, it makes the code unnece
On Mon, Jan 09, 2017 at 04:05:01PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
>
> Commit message missing.
>
> > Signed-off-by: Chris Wilson
>
>
>
> > @@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct
> > drm_i915_gem_object *obj,
> > i
Hi Chris,
On 4 January 2017 at 19:42, Chris Wilson wrote:
> The dma_fence.error field (formerly known as dma_fence.status) is an
> optional field that may be set by drivers before calling
> dma_fence_signal(). The field can be used to indicate that the fence was
> completed in err rather than wit
On ti, 2016-12-13 at 19:15 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915:
> s/gen8_setup_page_directory/gen8_setup_pdpe/
> URL : https://patchwork.freedesktop.org/series/16751/
> State : success
>
Merged the series. Thanks for the patches and r
From: Michel Thierry
Commit cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
missed a few of occurences of IS_BROXTON() that should have been
coverted to IS_GEN9_LP().
v2: Cite the right commit. (Ander)
Fixes: cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
Cc:
On Mon, Jan 09, 2017 at 08:13:11PM +0530, Sumit Semwal wrote:
> Hi Chris,
>
> On 4 January 2017 at 19:42, Chris Wilson wrote:
> > The dma_fence.error field (formerly known as dma_fence.status) is an
> > optional field that may be set by drivers before calling
> > dma_fence_signal(). The field can
On 20 December 2016 at 13:08, Chris Wilson wrote:
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 109
> +++
> drivers/gpu/drm/i915/selftests/mock_gem_device.h | 8 ++
> dr
Hey,
Op 26-12-16 om 19:45 schreef Paulo Zanoni:
> Ville pointed out that intel_fbc_choose_crtc() is iterating over all
> planes instead of just the primary planes. There are no real
> consequences of this problem for HSW+, and for the other platforms it
> just means that in some obscure multi-scre
On 31/12/2016 12:06, Chris Wilson wrote:
Make it clear that these functions are the user entry points for
the tiling/fence registers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c| 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 8
drivers/gpu/drm/i915/i9
On 20 December 2016 at 13:08, Chris Wilson wrote:
> A very simple mockery, just a random manager and timeline. Useful for
> inserting objects and ordering retirement; and not much else.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++
> drivers/gp
On 31/12/2016 12:06, Chris Wilson wrote:
Expose an interface for changing the tiling and stride on an object,
that includes the complexity of checking for conflicting bindings and
fence registers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_object.h | 3 +
drivers/gpu/drm/
== Series Details ==
Series: series starting with [1/3] drm/i915/DMC/GLK: Load DMC on GLK (rev2)
URL : https://patchwork.freedesktop.org/series/16926/
State : warning
== Summary ==
Series 16926v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/16926/revisions/2/mbo
On Mon, Jan 09, 2017 at 03:43:46PM +, Tvrtko Ursulin wrote:
>
> On 31/12/2016 12:06, Chris Wilson wrote:
> >Expose an interface for changing the tiling and stride on an object,
> >that includes the complexity of checking for conflicting bindings and
> >fence registers.
> >
> >Signed-off-by: Ch
On 09/01/2017 15:58, Chris Wilson wrote:
On Mon, Jan 09, 2017 at 03:43:46PM +, Tvrtko Ursulin wrote:
On 31/12/2016 12:06, Chris Wilson wrote:
Expose an interface for changing the tiling and stride on an object,
that includes the complexity of checking for conflicting bindings and
fence re
All of these conditions are prechecked by i915_tiling_ok() before we
allow setting the tiling/stride on the object and so we should never
fail asserting those conditions before writing the register.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_fence
Computing the tile row size of a tiled object (for use with fence
registers) is repeated, so extract it to a common helper.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 7 +--
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++
drivers/gpu/drm/i915/i915_gem
Restricting the fence to the end of the previous tile-row breaks access
to the final portion of the object. On gen2/3 we employed lazy fencing
to pad out the fence with scratch page to provide access to the tail,
and now we also pad out the object on gen4+ we can apply the same fix.
Fixes: af1a730
The fence size/alignment is a combination of the vma size plus object
tiling parameters. Those parameters are rarely changed, making the fence
size/alignemnt roughly constant for the lifetime of the VMA. We can
simplify subsequent calculations by precalculating the size/alignment
required for GGTT
Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.
Suggested-by: Joonas Lahtinen
Signed-off-by: C
Ensure the view occupies the full tile row so that reads/writes into the
VMA do not escape (via fenced detiling) into neighbouring objects - we
will pad the object with scratch pages to satisfy the fence. This
applies the lazy-tiling we employed on gen2/3 to gen4+.
Signed-off-by: Chris Wilson
Rev
On 31/12/2016 12:07, Chris Wilson wrote:
Start converting over from the byte count to its semantic macro, either
we want to allocate the size of a physical page in main memory or we
want the size of a virtual page in the GTT. 4096 could mean either, but
PAGE_SIZE and I915_GTT_PAGE_SIZE are expli
On Mon, Jan 09, 2017 at 04:19:03PM +, Tvrtko Ursulin wrote:
> >diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >index a5fe299da1d3..c6922a5f0514 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >+++ b/drivers/gpu/drm/i915/i9
On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
> Well, now I found where the -2 comes from.
> intel_dp_register_mst_connector() calls drm_connector_register(), which
> fails to add the kobject (warning below). But, it does zero error
> checking on the drm_connector_register() call and leaves
On 01/09/2017 08:41 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
>> Well, now I found where the -2 comes from.
>> intel_dp_register_mst_connector() calls drm_connector_register(), which
>> fails to add the kobject (warning below). But, it does zero error
>> checki
Hi,
Now when the blocking problems with iommu layer have been
solved by commits 910170442944e1f8674fd5ddbeeb8ccd1877ea98
and 65ca7f5f7d1cdde6c25172fe6107cd16902f826f it is possible
to test and experiment with this code on KBL.
I have tried to accomodate all the review feedback that
was given by t
From: Jesse Barnes
Use David's new IOMMU layer functions for supporting SVM in i915.
TODO:
error record collection for failing SVM contexts
callback handling for fatal faults
scheduling
v2: integrate David's core IOMMU support
make sure we don't clobber the PASID in the context reg st
From: Jesse Barnes
We just need to pass in an address to execute and some flags, since we
don't have to worry about buffer relocation or any of the other usual
stuff. Takes in a fance and returns a fence to be used for
synchronization.
v2: add a request after batch submission (Jesse)
v3: add a
Move the invariant parts of context desc setup from execlist init
to context creation. This is advantageous when we need to
create different templates based on the context parametrization,
ie. for svm capable contexts.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_
On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
>>> Well, now I found where the -2 comes from.
>>> intel_dp_register_mst_connector() calls drm_connector_register(), which
>>> fails to add the k
When the display resolution changes, the drm disables the
display pipes due to which audio rendering stops. At this
time, we need to ensure the existing audio pointers and
buffers are cleared out so that the playback can restarted
once the display pipe is enabled with a different N/CTS values
Sign
Legacy (CherryTrail/ Baytrail) HDMI audio drivers added
Legacy hdmi audio-Gfx interaction/ interfacing is updated to use
irq chip framework
This patch series has only been tested on hardware with
a single HDMI connector/pipe and additional work may be needed for newer
machines with 2 connectors
Notifiations like mode change, hot plug and edid to
the audio driver are added. This is inturn used by the
audio driver for its functionality.
A new interface file capturing the notifications needed by the
audio driver is added
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
This will allow i915 to perform a wait on pending modeset using the
same code.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic_helper.c | 51 +++--
include/drm/drm_atomic_helper.h | 1 +
2 files changed, 38 insertions(+), 14 deletions(-)
diff
On Baytrail and Cherrytrail, HDaudio may be fused out or disabled
by the BIOS. This driver enables an alternate path to the i915
display registers and DMA.
Although there is no hardware path between i915 display and LPE/SST
audio clusters, this HDMI capability is referred to in the documentation
a
We're protected by the connection_mutex lock against blocking modesets,
but nonblocking modesets are performed without any locking. This is
causing WARN in drm_wait_for_vblank and in general it's better to wait
before modeset completes before trying anything.
Signed-off-by: Maarten Lankhorst
---
Enable support for HDMI LPE audio mode on Baytrail and
Cherrytrail when HDaudio controller is not detected
Setup minimum required resources during i915_driver_load:
1. Create a platform device to share MMIO/IRQ resources
2. Make the platform device child of i915 device for runtime PM.
3. Create IR
Hdmi audio driver based on the child platform device
created by gfx driver is implemented.
This audio driver is derived from legacy intel
hdmi audio driver.
The interfaces for interaction between gfx and audio
are updated and the driver implementation updated to
derive interrupts in its own addres
It seems that nouveau requires this, so best to do this in the helper.
This allows nouveau to use the atomic suspend helper.
Cc: nouv...@lists.freedesktop.org
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic_helper.c | 51 ++
drivers/gpu/drm/nouveau/nouveau_disp
Fix hw_done in i915 and make nouveau use drm_atomic_helper_disable_all()
after fixing it to properly disable everything.
Maarten Lankhorst (3):
drm/atomic: move waiting for hw_done to a helper
drm/i915: Wait for pending modesets to complete before trying link
training
drm/atomic: Make di
Hi Jani,
Thanks for finding time to review the patch. Please find my comments inline.
Regards
Jyoti
-Original Message-
From: Nikula, Jani
Sent: Monday, January 9, 2017 2:30 PM
To: Yadav, Jyoti R ; intel-gfx@lists.freedesktop.org
Cc: Kahola, Mika ; Syrjala, Ville
; mi-jenkins-ci
Subjec
Reviewed-by: Rodrigo Vivi
On Mon, 2017-01-09 at 16:51 +0200, Ander Conselvan de Oliveira wrote:
> From: Michel Thierry
>
> Commit cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
> missed a few of occurences of IS_BROXTON() that should have been
> coverted to IS_GEN9_LP().
>
>
On Mon, 2017-01-09 at 18:26 +0530, vathsala nagaraju wrote:
> Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
> psr1 should be disabled.When psr2 is exited , bit 31 of reg
> PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
> (psr1 control register)is set to 0.
> Also ,PSR2_ID
On 01/09/2017 08:59 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
>> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm
== Series Details ==
Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
URL : https://patchwork.freedesktop.org/series/17709/
State : success
== Summary ==
Series 17709v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/
On 01/09/2017 08:59 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
>> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm
== Series Details ==
Series: SVM for kbl
URL : https://patchwork.freedesktop.org/series/17710/
State : failure
== Summary ==
Series 17710v1 SVM for kbl
https://patchwork.freedesktop.org/api/1.0/series/17710/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-connector-sta
== Series Details ==
Series: Add support for Legacy HDMI audio drivers (rev4)
URL : https://patchwork.freedesktop.org/series/16254/
State : success
== Summary ==
Series 16254v4 Add support for Legacy HDMI audio drivers
https://patchwork.freedesktop.org/api/1.0/series/16254/revisions/4/mbox/
T
== Series Details ==
Series: drm/atomic: Add helper for hw_done and fix suspend.
URL : https://patchwork.freedesktop.org/series/17712/
State : success
== Summary ==
Series 17712v1 drm/atomic: Add helper for hw_done and fix suspend.
https://patchwork.freedesktop.org/api/1.0/series/17712/revisio
1 - 100 of 125 matches
Mail list logo
