Hi Gerd,
>-Original Message-
>From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
>Behalf Of Gerd Hoffmann
>Sent: Thursday, May 11, 2017 9:28 PM
>To: Chen, Xiaoguang
>Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; zhen...@linux.i
Hi,
If my previous reply is not persuasive enough.
Let me do that in a different way.
> From: linux-acpi-ow...@vger.kernel.org
> [mailto:linux-acpi-ow...@vger.kernel.org] On Behalf Of Zheng,
> Lv
> Subject: RE: [PATCH v2 5/5] ACPI: button: Obselete acpi_lid_open() invocations
>
> Hi,
>
> > Fro
On Thu, 2017-05-11 at 16:02 -0700, Puthikorn Voravootivat wrote:
> There are some panel that
> (1) does not support display backlight enable via AUX
> (2) support display backlight adjustment via AUX
> (3) support display backlight enable via eDP BL_ENABLE pin
>
> The current driver required that
On 11/05/17 23:08, Pavel Machek wrote:
> On Mon 2017-01-23 10:39:27, Juergen Gross wrote:
>> On 13/01/17 15:41, Juergen Gross wrote:
>>> On 12/01/17 10:21, Chris Wilson wrote:
On Thu, Jan 12, 2017 at 07:03:25AM +0100, Juergen Gross wrote:
> On 11/01/17 18:08, Chris Wilson wrote:
>> On
On Thu, 2017-05-11 at 16:02 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravoot
>-Original Message-
>From: Alex Williamson [mailto:alex.william...@redhat.com]
>Sent: Friday, May 12, 2017 10:58 AM
>To: Chen, Xiaoguang
>Cc: Gerd Hoffmann ; Tian, Kevin ;
>intel-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org;
>zhen...@linux.intel.com; Lv, Zhiyuan ; intel-gvt-
>
Thanks.
Best Regards.
Weinan, LI
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> Sent: Thursday, May 11, 2017 8:56 PM
> To: Li, Weinan Z ; intel-gfx@lists.freedesktop.org;
> intel-
> gvt-...@lists.freedesktop.org
> Cc: Chris Wilson
> Subject: Re
On Fri, 12 May 2017 02:12:10 +
"Chen, Xiaoguang" wrote:
> Hi Alex and Gerd,
>
> >-Original Message-
> >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> >Behalf Of Alex Williamson
> >Sent: Thursday, May 11, 2017 11:45 PM
> >To: Gerd Hoffmann
> >Cc: Tian,
Hi Alex and Gerd,
>-Original Message-
>From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
>Behalf Of Alex Williamson
>Sent: Thursday, May 11, 2017 11:45 PM
>To: Gerd Hoffmann
>Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; zhen.
Hi,
> From: Benjamin Tissoires [mailto:benjamin.tissoi...@gmail.com]
> Subject: Re: [PATCH v2 5/5] ACPI: button: Obselete acpi_lid_open() invocations
>
> On Tue, May 9, 2017 at 9:02 AM, Lv Zheng wrote:
> > Since notification side has been changed to always notify kernel listeners
> > using _LID
On Mon, May 08, 2017 at 05:18:58PM +0530, Mahesh Kumar wrote:
> DDB minimum requirement may exceed the allocated DDB for CRTC/Pipe. This
> patch make changes to fail the flip if minimum requirement for pipe
> exceeds the total ddb allocated to the pipe.
> Previously it succeeded but making alloc_si
On Mon, May 08, 2017 at 05:18:59PM +0530, Mahesh Kumar wrote:
> This patch cleanup/reorganises the watermark calculation functions.
> This patch also make use of already available macro
> "drm_atomic_crtc_state_for_each_plane_state" to walk through
> plane_state list instead of calculating plane_st
On Mon, May 08, 2017 at 05:18:57PM +0530, Mahesh Kumar wrote:
> We are already doing memset of ddb structure at the begining of
> skl_allocate_pipe_ddb
> function, No need to again do a memset.
>
> Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c |
On Mon, May 08, 2017 at 05:18:55PM +0530, Mahesh Kumar wrote:
> This patch make changes to calculate adjusted plane pixel rate &
> plane downscale amount using fixed_point functions available.
> This patch will give uniformity in code, & will help to avoid mixing of
> 32bit uint32_t variable for fi
On Mon, May 08, 2017 at 05:31:30PM +0530, Mahesh Kumar wrote:
> Hi,
>
>
> On Monday 08 May 2017 05:18 PM, Lankhorst, Maarten wrote:
> > Mahesh Kumar schreef op ma 08-05-2017 om 17:18 [+0530]:
> > > Fail the flip if no FB is present but plane_state is set as visible.
> > > Above is not a valid com
On Mon, May 08, 2017 at 05:18:53PM +0530, Mahesh Kumar wrote:
> This patch adds few wrapper to perform fixed_point_16_16 operations
> mul_u32_fixed_16_16_round_up : Multiplies u32 and fixed_16_16_t
> variables & returns u32 result with
> r
On Mon, May 08, 2017 at 05:18:54PM +0530, Mahesh Kumar wrote:
> Don't use fixed_16_16 structure members directly, instead use wrapper to
> perform fixed_16_16 division operation.
>
> Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file
On Mon, May 08, 2017 at 05:18:52PM +0530, Mahesh Kumar wrote:
> fixed_16_16_div_round_up(_u64), wrapper for fixed_16_16 division
> operation don't really round_up the result. Wrapper round_up only the
> fraction part of the result to make it 16-bit.
> This patch eliminates round_up keyword from the
On Mon, May 08, 2017 at 05:18:51PM +0530, Mahesh Kumar wrote:
> This series implements new DDB allocation algorithm to solve the cases,
> where we have sufficient DDB available to enable multiple planes, But
> due to the current algorithm not dividing it properly among planes, we
> end-up failing t
Hi Weinan,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.11 next-20170511]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Weinan-Li/drm-i915-gvt-return-the
== Series Details ==
Series: Enhancement to intel_dp_aux_backlight driver (rev6)
URL : https://patchwork.freedesktop.org/series/21086/
State : success
== Summary ==
Series 21086v6 Enhancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/6/mb
This patch adds option to enable dynamic backlight for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/i915_params.c| 5
drivers/g
We should set backlight mode register before set register to
enable the backlight.
Signed-off-by: Puthikorn Voravootivat
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
Add option to allow choosing how to adjust brightness if
panel supports both PWM pin and AUX channel.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/i915_params.c| 8 +---
drivers/gpu/drm/i915/i915_params.h| 2 +-
drivers/gpu/drm/i915/intel_dp_aux_ba
Some panel will default to zero brightness when turning the
panel off and on again. This patch restores last brightness
level back when panel is turning back on.
Signed-off-by: Puthikorn Voravootivat
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 +
1 fil
There are some panel that
(1) does not support display backlight enable via AUX
(2) support display backlight adjustment via AUX
(3) support display backlight enable via eDP BL_ENABLE pin
The current driver required that (1) must be support to enable (2).
This patch drops that requirement.
Signed
This patch adds the following definition
- Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap
register which only use bit 0:4
- Base frequency (27 MHz) for backlight PWM frequency
generator.
Signed-off-by: Puthikorn Voravootivat
Reviewed-by: Dhinakaran Pandiyan
---
include/drm/drm_dp_helper.
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency is still within 25%
of the desired frequency.
Signed-off-by: Puthikorn Vorav
intel_dp_aux_backlight driver should check for the
DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP before enable the driver.
Signed-off-by: Puthikorn Voravootivat
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drive
intel_dp_aux_enable_backlight() assumed that the register
BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01
(DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize.
This patch fixed that by handling all cases of that register.
Signed-off-by: Puthikorn Voravootivat
Reviewed-by: Dhinakaran Pa
This patch set contain 9 patches.
- First five patches fix bug in the driver and allow choosing which
way to adjust brightness if both PWM pin and AUX are supported
- Next patch adds enable DBC by default
- Next patch makes the driver restore last brightness level after
turning display off and
On Mon 2017-01-23 10:39:27, Juergen Gross wrote:
> On 13/01/17 15:41, Juergen Gross wrote:
> > On 12/01/17 10:21, Chris Wilson wrote:
> >> On Thu, Jan 12, 2017 at 07:03:25AM +0100, Juergen Gross wrote:
> >>> On 11/01/17 18:08, Chris Wilson wrote:
> On Wed, Jan 11, 2017 at 05:33:34PM +0100, Jue
On Wed, May 10, 2017 at 5:39 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Tue, 2017-05-09 at 16:40 -0700, Puthikorn Voravootivat wrote:
> > There are some panel that
> > (1) does not support display backlight enable via AUX
> > (2) support display backlight adjustment via
Fair enough. Will add kernel switch in next version.
On Wed, May 10, 2017 at 6:26 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Wed, 2017-05-03 at 17:28 -0700, Puthikorn Voravootivat wrote:
> > This patch enables dynamic backlight by default for eDP
> > panel that supports
== Series Details ==
Series: series starting with [01/12] drm/i915: Remove kref from i915_sw_fence
URL : https://patchwork.freedesktop.org/series/24314/
State : success
== Summary ==
Series 24314v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/24314/revisions/1/m
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the set of priorities. This should keep
the heigh
Rebrand the current (pointer | bits) pack/unpack utility macros as
explicit bit twiddling for PAGE_SIZE so that we can use the more
flexible underlying macros for different bits.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
drivers
Since we coordinate with the execlists tasklet using a locked schedule
operation that ensures that after we set the engine->irq_posted we
always have an invocation of the tasklet, we do not need to use a locked
operation to set the engine->irq_posted itself.
Signed-off-by: Chris Wilson
---
drive
The i915_priolist are allocated within an atomic context on a path where
we wish to minimise latency. If we use a dedicated kmem_cache, we have
the advantage of a local freelist from which to service new requests
that should keep the latency impact of an allocation small. Though
currently we expect
As the handler is now quite complex, involving a few atomics, the cost
of the function preamble is negligible in comparison and so we should
leave the function out-of-line for better I$.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file ch
If we do not require to perform priority bumping, and we haven't yet
submitted the request, we can update its priority in situ and skip
acquiring the engine locks -- thus avoiding any contention between us
and submit/execute.
v2: Remove the stack element from the list if we can do the early
assign
My original intention was for i915_sw_fence to be the base class and
provide the reference count for the container. This was from starting
with a design to handle async_work. In practice, for i915 we embed
fences into structs which have their own independent reference counting,
making the i915_sw_f
A long time ago, I wrote some selftests for the struct kfence idea. Now
that we have infrastructure in i915/igt for running kselftests, include
some for i915_sw_fence.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 12 +
drivers/gpu/drm/i915/i915_sw_fence.c
If we *know* that the engine is idle, i.e. we have not more contexts in
flight, we can skip any spurious CSB idle interrupts. These spurious
interrupts seem to arrive long after we assert that the engines are
completely idle, triggering later assertions:
[ 178.896646] intel_engine_is_idle(bcs): i
ptr_unpack_bits() is a function-like macro, as such it is meant to be
replaceable by a function. In this case, we should be passing in the
out-param as a pointer.
Bizarrely this does affect code generation:
function old new delta
i915_gem_object_pin_map
Explicitly assign the default priority, and give it a name. After much
discussion, we have chosen to call it I915_PRIORITY_NORMAL!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/i915_gem_request.h | 1 +
2 files changed, 2 insertions(+)
diff
add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187)
function old new delta
execlists_submit_ports 262 471+209
port_assign.isra - 136+136
capture 63
On Thu, May 11, 2017 at 12:57:20PM +0300, Jani Nikula wrote:
> Face the fact, there are Display Port sink and branch devices out there
> in the wild that don't follow the Display Port specifications, or they
> have bugs, or just otherwise require special treatment. Start a common
> quirk database t
On 17-05-03 14:15:15, Liviu Dudau wrote:
On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
Updated blob layout (Rob, Daniel, Kristian, xerpi)
Cc: Rob Clark
Cc: Daniel Stone
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_mode_config.c | 7 +++
d
On 05/11/2017 03:03 AM, Jani Nikula wrote:
On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced N and M values when
to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9.
I'm not happy, but I al
On 05/11/2017 02:57 AM, Jani Nikula wrote:
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
Fixes: 9a
On 05/11/2017 02:57 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query b
== Series Details ==
Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev11)
URL : https://patchwork.freedesktop.org/series/20084/
State : success
== Summary ==
Series 20084v11 Enable OA unit for Gen 8 and 9 in i915 perf
https://patchwork.freedesktop.org/api/1.0/series/20084/revisions/11/m
On Thu, 11 May 2017 15:27:53 +0200
Gerd Hoffmann wrote:
> Hi,
>
> > While read the framebuffer region we have to tell the vendor driver which
> > framebuffer we want to read? There are two framebuffers now in KVMGT that
> > is primary and cursor.
> > There are two methods to implement this:
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_oa_glk.c | 2600
drivers/gpu/drm/i915/i915_oa_glk.h | 38 +
drivers/gpu/drm/i915/i915_perf.c | 15 +-
4 files changed, 2654 insertions(+), 2 dele
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9df52031eae..88906c79f982 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i
From: Robert Bragg
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop
Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mechanism to allow more than one set of registers
to be programmed.
Signed-off-b
From: Robert Bragg
In earlier iterations of the i915-perf driver we had a number of
callbacks/hooks from other parts of the i915 driver to e.g. notify us
when a legacy context was pinned and these could run asynchronously with
respect to the stream file operations and might also run in atomic
con
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
From: Robert Bragg
An oa_exponent_to_ns() utility and per-gen timebase constants where
recently removed when updating the tail pointer race condition WA, and
this restores those so we can update the _PROP_OA_EXPONENT validation
done in read_properties_unlocked() to not assume we have a 12.5MHz
ti
From: Robert Bragg
Assuming a uniform mask across all slices, this enables userspace to
determine the specific sub slices enabled. This information is required,
for example, to be able to analyse some OA counter reports where the
counter configuration depends on the HW sub slice configuration.
S
From: Robert Bragg
Enables userspace to determine the number of slices enabled and also
know what specific slices are enabled. This information is required, for
example, to be able to analyse some OA counter reports where the counter
configuration depends on the HW slice configuration.
Signed-of
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; curren
From: Robert Bragg
If I'm going to complain about a back-to-front convention then the least
I can do is not muddle the comment up too.
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Robert Bragg
If the function for checking whether there is OA buffer data available
(during a poll or blocking read) has false positives then we want to
avoid a situation where the subsequent read() returns EAGAIN (after
a more accurate check) followed by a poll() immediately reporting
the
From: Robert Bragg
This change is pre-emptively aiming to avoid a potential cause of kernel
logging noise in case some condition were to result in us seeing invalid
OA reports.
The workaround for the OA unit's tail pointer race condition is what
avoids the primary known cause of invalid reports
From: Robert Bragg
A minor improvement to debugging output
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
i
From: Robert Bragg
There's a HW race condition between OA unit tail pointer register
updates and writes to memory whereby the tail pointer can sometimes get
ahead of what's been written out to the OA buffer so far (in terms of
what's visible to the CPU).
Although this can be observed explicitly
From: Robert Bragg
This avoids redundantly passing an (inout) head and tail pointer to
gen7_append_oa_reports() from gen7_oa_read which doesn't need to
reference either itself.
Moving the head/tail reads and writes into gen7_append_oa_reports should
have no functional effect except to avoid some
From: Chris Wilson
In the next patch, we will expose the ability to reconfigure the slices,
subslice and eu per context. To facilitate that, store the current
configuration on the context, which is initially set to the device
default upon creation.
Signed-off-by: Chris Wilson
---
drivers/gpu/d
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
From: Robert Bragg
This updates the tail pointer race workaround handling to updating the
'aged' pointer before looking to start aging a new one. There's the
possibility that there is already new data available and so we can
immediately start aging a new pointer without having to first wait for a
From: Robert Bragg
There's no need for the driver to keep reading back the head pointer
from hardware since the hardware doesn't update it automatically. This
way we can treat any invalid head pointer value as a software/driver
bug instead of spurious hardware behaviour.
This change is also a sm
Hi all,
Here are the changes from the previous series :
* Included patches 9, 10 & 11 from Chris to have sseu configuration
stored per context (but not exposed to userspace)
* In patches 12 & 13 querying the slice/subslice configuration now
returns the configuration locked in by the OA u
On Thu, Apr 06, 2017 at 12:15:07PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni
>
> We're going to use it in the next commits.
>
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Jim Bride
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> 1 file changed, 6 ins
== Series Details ==
Series: Implement DDB algorithm and WM cleanup (rev6)
URL : https://patchwork.freedesktop.org/series/20376/
State : success
== Summary ==
Series 20376v6 Implement DDB algorithm and WM cleanup
https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/6/mbox/
Test ge
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> Sent: Thursday, May 11, 2017 8:50 PM
> To: Dong, Chuanxiao ; intel-gvt-
> d...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: disable GVT-g i
Hi,
> While read the framebuffer region we have to tell the vendor driver which
> framebuffer we want to read? There are two framebuffers now in KVMGT that is
> primary and cursor.
> There are two methods to implement this:
> 1) write the plane id first and then read the framebuffer.
> 2) crea
== Series Details ==
Series: drm/i915: Consistent ordering of tracepoint binary data
URL : https://patchwork.freedesktop.org/series/24293/
State : success
== Summary ==
Series 24293v1 drm/i915: Consistent ordering of tracepoint binary data
https://patchwork.freedesktop.org/api/1.0/series/24293
On 11/05/2017 14:07, Chris Wilson wrote:
On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
For userspace receiving binary data it is easier if all related
request tracepoints emit the binary data in the same order of
dev, ring, ctx, seqno, ...
We decided t
On Thu, May 11, 2017 at 02:07:35PM +0100, Chris Wilson wrote:
> On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > For userspace receiving binary data it is easier if all related
> > request tracepoints emit the binary data in the same order of
> > de
On ke, 2017-05-10 at 08:33 +, Oscar Mateo wrote:
>
>
> On 05/10/2017 01:28 PM, Daniel Vetter wrote:
> >
> > On Wed, May 10, 2017 at 2:59 PM, Joonas Lahtinen
> > wrote:
> > >
> > > >
> > > > @@ -841,6 +847,11 @@ static int gen9_init_workarounds(struct
> > > > intel_engine_cs *engine)
> > >
On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> For userspace receiving binary data it is easier if all related
> request tracepoints emit the binary data in the same order of
> dev, ring, ctx, seqno, ...
We decided that dev, ctx, ring, seqno was the ri
On ke, 2017-05-10 at 13:13 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Do not sync RCU during shrinking (rev3)
> URL : https://patchwork.freedesktop.org/series/24008/
> State : success
Merged the patch, thanks for review and testing.
Regards, Joonas
--
Joonas Lahtinen
A display resolution is only supported if it meets all the restrictions
below for Maximum Pipe Pixel Rate.
The display resolution must fit within the maximum pixel rate output
from the pipe. Make sure that the display pipe is able to feed pixels at
a rate required to support the desired resolution
From: Tvrtko Ursulin
For userspace receiving binary data it is easier if all related
request tracepoints emit the binary data in the same order of
dev, ring, ctx, seqno, ...
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_trace.h | 4 ++
On to, 2017-05-11 at 06:51 +, Li, Weinan Z wrote:
> >
> > -Original Message-
> > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> > Sent: Wednesday, May 10, 2017 6:43 PM
> > To: Li, Weinan Z ; intel-gfx@lists.freedesktop.org;
> > intel-
> > gvt-...@lists.freedesktop.or
On to, 2017-05-11 at 02:33 +, Dong, Chuanxiao wrote:
>
> >
> > -Original Message-
> > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> > Sent: Wednesday, May 10, 2017 8:48 PM
> > To: Dong, Chuanxiao ; intel-gvt-
> > d...@lists.freedesktop.org; intel-gfx@lists.freedeskt
== Series Details ==
Series: drm/i915: set initialised only when init_context callback is NULL
URL : https://patchwork.freedesktop.org/series/24286/
State : success
== Summary ==
Series 24286v1 drm/i915: set initialised only when init_context callback is NULL
https://patchwork.freedesktop.org/
On Thursday 11 May 2017 03:18 PM, Maarten Lankhorst wrote:
Op 11-05-17 om 10:36 schreef Mahesh Kumar:
Hi,
Thanks for review.
On Wednesday 10 May 2017 06:52 PM, Maarten Lankhorst wrote:
Op 08-05-17 om 13:49 schreef Mahesh Kumar:
A display resolution is only supported if it meets all the res
== Series Details ==
Series: series starting with [1/2] drm/dp: start a DPCD based DP sink/branch
device quirk database
URL : https://patchwork.freedesktop.org/series/24282/
State : warning
== Summary ==
Series 24282v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/seri
initialised is fixup by the GVT shadow context as true to avoid the init
from the host because it cannot take the settings from the host. Add a
check to let host driver only overwrite it when the init callback is NULL
Cc: Chris Wilson
Signed-off-by: Chuanxiao Dong
---
drivers/gpu/drm/i915/intel
On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> The Analogix 7737 DP to HDMI converter requires reduced N and M values when
> to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9.
I'm not happy, but I also see no alternative than to go this
rou
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
Fixes: 9a86cda07af2 ("drm/i915/dp: reduce link M/N param
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on OUI (with the option of
expanding to de
Op 11-05-17 om 10:36 schreef Mahesh Kumar:
> Hi,
>
> Thanks for review.
>
> On Wednesday 10 May 2017 06:52 PM, Maarten Lankhorst wrote:
>> Op 08-05-17 om 13:49 schreef Mahesh Kumar:
>>> A display resolution is only supported if it meets all the restrictions
>>> below for Maximum Pipe Pixel Rate.
>>
Op 11-05-17 om 11:23 schreef Daniel Vetter:
> On Thu, May 11, 2017 at 10:28:43AM +0200, Maarten Lankhorst wrote:
>> We shouldn't inspect crtc->state, instead grab the crtc state.
>> At this point the hw state verifier should be able to run even if
>> crtc->state has been updated (which cannot curre
On ke, 2017-05-10 at 12:59 +, Michal Wajdeczko wrote:
> Prepare for alternate GuC notification mechanism.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Daniele Ceraolo Spurio
> Reviewed-by: Daniele Ceraolo Spurio
> @@ -233,6 +236,10 @@ static inline int intel_guc_send(
== Series Details ==
Series: Implement DDB algorithm and WM cleanup (rev5)
URL : https://patchwork.freedesktop.org/series/20376/
State : success
== Summary ==
Series 20376v5 Implement DDB algorithm and WM cleanup
https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/5/mbox/
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