[Intel-gfx] [PATCH 05/11] drm/i915: Implement .get_format_info() hook for CCS

From: Ville Syrjälä SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are

[Intel-gfx] [PATCH 02/11] drm/i915: Fix scaling check for 90/270 degree plane rotation

From: Ville Syrjälä Starting from commit b63a16f6cd89 ("drm/i915: Compute display surface offset in the plane check hook for SKL+") we've already rotated the src coordinates by 270 degrees by the time we check if a scaler is needed or not, so we must not account

[Intel-gfx] [PATCH 07/11] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function and made it available for both primary and sprite planes v2: -Use intel_ prefix for format_is_yuv (Ville) Link: https://patchwork.kernel.org/patch/6426181/ Signed-off-by: Chandra Konduru

[Intel-gfx] [PATCH 04/11] drm/i915: Fix 90/270 rotated coordinates for FBC

From: Ville Syrjälä The clipped src coordinates have already been rotated by 270 degrees for when the plane rotation is 90/270 degrees, hence the FBC code should no longer swap the width and height. Cc: sta...@vger.kernel.org Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 09/11] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) Link: https://patchwork.kernel.org/patch/6426201/ Signed-off-by: Chandra Konduru Signed-off-by:

[Intel-gfx] [PATCH 10/11] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) Link: https://patchwork.kernel.org/patch/6426211/ Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti

[Intel-gfx] [PATCH 03/11] drm/i915: Fix SKL+ watermarks for 90/270 rotation

From: Ville Syrjälä skl_check_plane_surface() already rotates the clipped plane source coordinates to match the scanout direction because that's the way the GTT mapping is set up. Thus we no longer need to rotate the coordinates in the watermark code. For cursors

[Intel-gfx] [PATCH 06/11] drm/i915: Set scaler mode for NV12

From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling Link: https://patchwork.kernel.org/patch/6426161/ Signed-off-by: Chandra Konduru

[Intel-gfx] [PATCH 08/11] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 Link: https://patchwork.kernel.org/patch/6426191/ Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya

[Intel-gfx] [PATCH 00/11] Adding NV12 support for SKL display

This patch series is adding NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Feature has been currently tested with custom linux based test tool IGT

[Intel-gfx] [PATCH 11/11] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) Link: https://patchwork.kernel.org/patch/6426221/ Signed-off-by: Chandra

[Intel-gfx] [PATCH 01/11] drm/i915: Add render decompression support

From: Ville Syrjälä SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are

Re: [Intel-gfx] [Intel-wired-lan] [PATCH v2 1/1] e1000e: Undo e1000e_pm_freeze if __e1000_shutdown fails

> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On Behalf > Of Jeff Kirsher > Sent: Tuesday, June 6, 2017 1:46 PM > To: David Miller ; Nikula, Jani > > Cc: Ursulin, Tvrtko ; daniel.vet...@ffwll.ch; intel- >

Re: [Intel-gfx] [PATCH 3/3] drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.

On Tue, 2017-06-06 at 15:08 -0700, Anusha Srivatsa wrote: > Add PCI Ids for H Sku by following the BSpec. > > Cc: Rodrigo Vivi > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/i915_pci.c | 1 + > include/drm/i915_pciids.h |

[Intel-gfx] [PATCH 2/3] drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.

Add PCI Ids for S Sku following the BSpec. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_pci.c | 1 + include/drm/i915_pciids.h | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.

Add PCI Ids for U Skus of Coffeelake. v2: Use intel_coffeelake_gt3_info, in accordance to- Rodrigo's patch: https://patchwork.freedesktop.org/patch/160148/ Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_pci.c |

[Intel-gfx] [PATCH 3/3] drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.

Add PCI Ids for H Sku by following the BSpec. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_pci.c | 1 + include/drm/i915_pciids.h | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git

Re: [Intel-gfx] [PATCH] drm/i915: Unify GT* and GT3 definitions

>-Original Message- >From: Vivi, Rodrigo >Sent: Tuesday, June 6, 2017 9:06 AM >To: intel-gfx@lists.freedesktop.org >Cc: Vivi, Rodrigo ; Chris Wilson wilson.co.uk>; Srivatsa, Anusha >Subject: [PATCH] drm/i915: Unify GT*

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Tue, Jun 6, 2017 at 2:48 PM, Pandiyan, Dhinakaran wrote: > On Tue, 2017-06-06 at 11:12 -0700, Rodrigo Vivi wrote: >> On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi wrote: >> > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran >> >

Re: [Intel-gfx] [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

When addressing Imre's comments I noticed: error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function] static void cnl_set_cdclk(struct drm_i915_private *dev_priv, ^ cc1: all warnings being treated as errors Ville, since the original is yours I'd like your advise on how to

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Tue, 2017-06-06 at 11:12 -0700, Rodrigo Vivi wrote: > On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi wrote: > > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran > > wrote: > >> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote: >

Re: [Intel-gfx] [PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

>-Original Message- >From: Vivi, Rodrigo >Sent: Tuesday, June 6, 2017 12:20 PM >To: intel-gfx@lists.freedesktop.org >Cc: Vivi, Rodrigo ; Srivatsa, Anusha > >Subject: [PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition. >

[Intel-gfx] [PATCH] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

Let's inherit workarounds from previous platforms that according to wa_database and BSpec are still valid for Cannonlake. v2: Add missed workarounds. v3: Rebase v4: Remove bad chunk that was added to rc6 disable. (Ander) Also remove A0 W/a that are not needed anymore. Cc: Ander Conselvan De

Re: [Intel-gfx] [PATCH v2 1/1] e1000e: Undo e1000e_pm_freeze if __e1000_shutdown fails

On Fri, 2017-06-02 at 14:14 -0400, David Miller wrote: > From: Jani Nikula > Date: Wed, 31 May 2017 18:50:43 +0300 > > > From: Chris Wilson > > > > An error during suspend (e100e_pm_suspend), > > ... > > lead to complete failure: > > ... > >

[Intel-gfx] [PATCH 11/11] drm/i915/cnl: Also need power well sanitize.

The workaround added in commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well equests left on by DMC/KVMR") needs to be applied on Cannonlake as well. So let's assume any platform using this power well setup will also need and let's just go ahead and remove if condition. Cc: Imre Deak

[Intel-gfx] [PATCH 02/11] drm/i915/cnl: Cannonlake uses CNP PCH.

Avoid warning when CNP is detected with CNL. Also let's force it on the virtual detection. Signed-off-by: Rodrigo Vivi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_drv.c | 4 1 file changed, 4 insertions(+) diff --git

[Intel-gfx] [PATCH 04/11] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.

By the Spec all CNL Y skus are 2+2, i.e. GT2. v2: Really include the PCI IDs to the picidlist[]; Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 12 +++- 1 file changed, 11 insertions(+), 1

[Intel-gfx] [PATCH 06/11] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

From: James Irwin Issue: VIZ-4525 Reviewed-by: Damien Lespiau Signed-off-by: James Irwin Signed-off-by: Damien Lespiau Reviewed-by: Ander Conselvan de Oliveira ---

[Intel-gfx] [PATCH 10/11] drm/i915/cnl: Add power wells for CNL

From: Ville Syrjälä CNL power wells are very similar to SKL, with the exception that the misc IO well has been split into separate AUX IO wells. Not sure if DMC is supposed to manage the AUX wells for us or not. Let's assume so for now. v2: DDI A power well wants

[Intel-gfx] [PATCH 01/11] drm/i915/cnl: Introduce Cannonlake platform defition.

Cannonlake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen10. Let's start by adding the platform definition based on previous platforms but yet as alpha_support. On following patches we will start adding PCI IDs and the platform specific changes. CNL has an

[Intel-gfx] [PATCH 08/11] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

All registers and default configuration are the same for Skylake and Cannonlake. v2: Don't apply Wa for platforms without MOCS. (Paulo) v3: Removed WaDisableSkipCaching that Joonas noticed that according to spec it is not applicable to CNL. Cc: Paulo Zanoni

[Intel-gfx] [PATCH 07/11] drm/i915/cnl: Configure EU slice power gating.

Cannonlake also supports slice power gating on devices with more than one slice as SKL. Let's assume that this is the same for SKL+ and exclude BXT only. v2: Also remove KBL. Signed-off-by: Rodrigo Vivi Reviewed-by: Joonas Lahtinen ---

[Intel-gfx] [PATCH 09/11] drm/i915/gen10: Set value of Indirect Context Offset for gen10

From: Michel Thierry Indirect Context Offset Pointer has changed for Cannonlake. INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec. v2: rebased to intel_lr_indirect_ctx_offset v3: Commit message added per Tvrtko request. Signed-off-by: Michel Thierry

[Intel-gfx] [PATCH 05/11] drm/i915/cnl: add IS_CNL_REVID macro

From: Paulo Zanoni We're going to use it in the next commits. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Jim Bride --- drivers/gpu/drm/i915/i915_drv.h | 6 ++

[Intel-gfx] [PATCH 03/11] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also the new Spec style what makes the review much more easy and straightforward. v2: Really include the PCI IDs to the

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Clear enable_guc_loading in case of init failure (rev2)

On 6/5/2017 10:32 AM, Patchwork wrote: == Series Details == Series: drm/i915/guc: Clear enable_guc_loading in case of init failure (rev2) URL : https://patchwork.freedesktop.org/series/25228/ State : success == Summary == Series 25228v2 drm/i915/guc: Clear enable_guc_loading in case of init

[Intel-gfx] [PATCH 4/5] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

The whole Display engine for Coffee Lake is pretty much identical to the Kabylake. For this reason let's reuse all display related production workardounds here even though CFL is not explicit listed at Display workarounds page at Spec. Cc: Arthur Runyan Cc: Dhinakaran

[Intel-gfx] [PATCH 5/5] drm/i915/cfl: Introduce Coffee Lake workardounds.

Coffee Lake inherit most of Kabylake production workardounds. Only difference identified so far is: - WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 2/5] drm/i915/cfl: Coffee Lake uses CNP PCH.

So let's force it on the virtual detection. Also it is still the only silicon for now on this PCH, so WARN otherwise. Signed-off-by: Rodrigo Vivi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_drv.c | 4 1 file changed, 4

[Intel-gfx] [PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

All here is pretty much like Kabylake. Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

Coffee Lake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. Let's start by adding the platform definition based on previous platforms but yet as preliminary_hw_support. On following patches we will start adding PCI

Re: [Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

On 6/6/2017 3:16 AM, Chris Wilson wrote: I didn't think it was sensible to advertise reset-engine support without global reset (or the hangcheck to detect the error), and for the time being we can keep thinking of this as an integer rather than a set of flags. So I was just thinking of value =

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi wrote: > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran > wrote: >> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote: >>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran >>>

Re: [Intel-gfx] [PATCH] drm/i915: Remove unecessary PORT3 definition.

Just a very tiny nitpick about correction in the spelling of "unnecessary" in the title. Other than that Reviewed-by: Manasi Navare On Tue, Jun 06, 2017 at 09:06:36AM -0700, Rodrigo Vivi wrote: > Let's be picky and just use PICK directly. > So we can extend this

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran wrote: > On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote: >> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran >> wrote: >> > On Mon, 2017-06-05 at 19:55 +0300, Ville

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On Tue, Jun 06, 2017 at 02:30:15PM +0200, Vlastimil Babka wrote: > On 06/06/2017 02:14 PM, Michal Hocko wrote: > > On Tue 06-06-17 13:04:36, Chris Wilson wrote: > >> Similar in principle to the treatment of get_user_pages, pages that > >> i915.ko acquires from shmemfs are not immediately

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote: > On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran > wrote: > > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote: > >> On Mon, Jun 05, 2017 at 04:41:07PM +, Vivi, Rodrigo wrote: > >> > On Mon,

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On Tue, Jun 06, 2017 at 02:14:18PM +0200, Michal Hocko wrote: > That is certainly desirable. Peter has proposed a generic pin_page (or > similar) API. What happened with it? I got stuck on converting IB ... and I think someone thereafter made an ever bigger mess of the pinning stuff. I don't

Re: [Intel-gfx] [PATCH v2 0/7] Add Y-tiling support into IGTs

Em Sáb, 2017-04-29 às 08:44 +0530, Praveen Paneri escreveu: > HI Paulo, > > > > On Sat, Apr 29, 2017 at 12:51 AM, Paulo Zanoni com> wrote: > > Em Sex, 2017-04-28 às 20:07 +0530, Praveen Paneri escreveu: > > > This series adds Y-tiled buffer creation support into IGT > >

Re: [Intel-gfx] [PATCH] drm/i915: s/fbc_fc/fbc_false_color/

On Tue, Jun 06, 2017 at 03:15:09PM +, Vivi, Rodrigo wrote: > On Tue, 2017-06-06 at 15:44 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > We're not that short on characters that we can't spell out > > "false_color". Saves me from

Re: [Intel-gfx] [PATCH v2] drm/i915: Implement fbc_status "Compressing" info for all platforms

On Tue, Jun 06, 2017 at 03:43:18PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The number of compressed segments has been available ever since > FBC2 was introduced in g4x, it just moved from the STATUS register > into STATUS2 on IVB. > >

Re: [Intel-gfx] [PATCH] drm/i915: Restore has_fbc=1 for ILK-M

On Tue, Jun 06, 2017 at 03:11:32PM +, Vivi, Rodrigo wrote: > Reviewed-by: Rodrigo Vivi Thanks. Pushed to dinq. > > On Tue, 2017-06-06 at 16:32 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Restore the

Re: [Intel-gfx] [PATCH 0/3] drm/i915: Fix SKL+ 90/270 degree rotated scanout

On Tue, Jun 06, 2017 at 05:15:30PM +0200, Maarten Lankhorst wrote: > Hey, > > Op 06-06-17 om 10:29 schreef Tvrtko Ursulin: > > > > On 06/06/2017 09:06, Maarten Lankhorst wrote: > >> Op 05-04-17 om 15:49 schreef Ville Syrjälä: > >>> On Fri, Mar 31, 2017 at 10:23:18PM +0100, Chris Wilson wrote: >

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On 06/06/2017 05:34 AM, Chris Wilson wrote: > With respect to i915, we may not be the sole owner of the page at the > point where we call shmem_read_mapping_page_gfp() as it can mmapped or > accessed directly via the mapping internally. It is just at this point > we know that the page will not be

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On 06/06/2017 05:14 AM, Michal Hocko wrote: > On Tue 06-06-17 13:04:36, Chris Wilson wrote: >> Similar in principle to the treatment of get_user_pages, pages that >> i915.ko acquires from shmemfs are not immediately reclaimable and so >> should be excluded from the mm accounting and vmscan until

[Intel-gfx] [PATCH] drm/i915: Remove unecessary PORT3 definition.

Let's be picky and just use PICK directly. So we can extend this later without creating a new PORT_X por every new number of ports we have to handle. Cc: Manasi Navare Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 6 ++

[Intel-gfx] [PATCH] drm/i915: Unify GT* and GT3 definitions

This patch clean up a bit the platform definition block in a way to avoid duplications and to let clear that GT3 for the current platform only have the extra Media engine (BSD2). v2: Kabylake IS_KABYLAKE as Anusha noticed. v3: Avoid EXTRA_ENGINE_MASK and list rings out on GT3 to make it more

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP

On Tue, Jun 06, 2017 at 05:58:43PM +0300, Bloomfield, Jon wrote: > > -Original Message- > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > > Of Imre Deak > > Sent: Tuesday, June 6, 2017 5:34 AM > > To: Jani Nikula > > Cc:

Re: [Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran wrote: > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote: >> On Mon, Jun 05, 2017 at 04:41:07PM +, Vivi, Rodrigo wrote: >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote: >> > > On Thu, Apr 06,

Re: [Intel-gfx] [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

On Tue, 2017-06-06 at 07:48 +0100, Tvrtko Ursulin wrote: > On 05/06/2017 18:11, Vivi, Rodrigo wrote: > > On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote: > >> On 06/04/2017 20:15, Rodrigo Vivi wrote: > >>> From: Michel Thierry > >>> > >> > >> Some commit message

Re: [Intel-gfx] [PATCH] drm/i915: Unify GT* and GT3 definitions

On Tue, 2017-06-06 at 10:47 +0300, Jani Nikula wrote: > On Mon, 05 Jun 2017, Rodrigo Vivi wrote: > > This patch clean up a bit the platform definition block in > > a way to avoid duplications and to let clear that GT3 for > > the current platform only have the extra Media

Re: [Intel-gfx] [PATCH 0/3] drm/i915: Fix SKL+ 90/270 degree rotated scanout

Hey, Op 06-06-17 om 10:29 schreef Tvrtko Ursulin: > > On 06/06/2017 09:06, Maarten Lankhorst wrote: >> Op 05-04-17 om 15:49 schreef Ville Syrjälä: >>> On Fri, Mar 31, 2017 at 10:23:18PM +0100, Chris Wilson wrote: On Fri, Mar 31, 2017 at 09:00:53PM +0300, ville.syrj...@linux.intel.com

Re: [Intel-gfx] [PATCH] drm/i915: s/fbc_fc/fbc_false_color/

On Tue, 2017-06-06 at 15:44 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We're not that short on characters that we can't spell out > "false_color". Saves me from figuring out what "fc" means > the next time look at the code. Yeap, even I

Re: [Intel-gfx] [PATCH] drm/i915: Remove unecessary PORT3 definition.

On Mon, 2017-06-05 at 16:57 -0700, Manasi Navare wrote: > On Mon, Jun 05, 2017 at 03:12:02PM -0700, Rodrigo Vivi wrote: > > Let's be picky and just use PICK directly. > > So we can extend this later without creating > > a new PORT_X por every new number of ports we > > have to handle. > > > > Cc:

Re: [Intel-gfx] [PATCH] drm/i915: Restore has_fbc=1 for ILK-M

Reviewed-by: Rodrigo Vivi On Tue, 2017-06-06 at 16:32 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Restore the lost has_fbc flag for mobile ILK. > > Cc: Carlos Santa > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Imre Deak > Sent: Tuesday, June 6, 2017 5:34 AM > To: Jani Nikula > Cc: intel-gfx@lists.freedesktop.org; Mustaffa, Mustamin B >

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

Quoting Vlastimil Babka (2017-06-06 13:30:15) > On 06/06/2017 02:14 PM, Michal Hocko wrote: > > On Tue 06-06-17 13:04:36, Chris Wilson wrote: > >> Similar in principle to the treatment of get_user_pages, pages that > >> i915.ko acquires from shmemfs are not immediately reclaimable and so > >>

[Intel-gfx] [PATCH] drm/i915: Restore has_fbc=1 for ILK-M

From: Ville Syrjälä Restore the lost has_fbc flag for mobile ILK. Cc: Carlos Santa Cc: Rodrigo Vivi Fixes: a13233804686 ("drm/i915: Introduce GEN5_FEATURES for device info") Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: Reset GPU before running subtests

Quoting Mika Kahola (2017-06-06 13:33:14) > On Tue, 2017-06-06 at 15:27 +0300, Ville Syrjälä wrote: > > On Tue, Jun 06, 2017 at 03:20:46PM +0300, Mika Kahola wrote: > > > > > > It has been noticed by our CI BAT testing that in some 1%-3% > > > probability > > > kms_pipe_crc_basic subtest

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_setmode: Dynamic crtc/connector combinations

On 2017-06-06 03:43 AM, Petri Latvala wrote: On Mon, Jun 05, 2017 at 03:59:37PM -0400, Harry Wentland wrote: On 2017-06-05 03:50 PM, Alex Deucher wrote: On Mon, Jun 5, 2017 at 2:43 PM, Harry Wentland wrote: Create crtc/connector combinations based on actual adapter

Re: [Intel-gfx] [PATCH v9] drm/i915: Modify error handler for per engine hang recovery

Hi Michel, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.12-rc4 next-20170606] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Michel-Thierry/drm-i915-Modify

Re: [Intel-gfx] [PATCH v9] drm/i915: Modify error handler for per engine hang recovery

Hi Michel, [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v4.12-rc4 next-20170606] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Michel-Thierry/drm-i915

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement fbc_status "Compressing" info for all platforms (rev2)

== Series Details == Series: drm/i915: Implement fbc_status "Compressing" info for all platforms (rev2) URL : https://patchwork.freedesktop.org/series/25176/ State : success == Summary == Series 25176v2 drm/i915: Implement fbc_status "Compressing" info for all platforms

[Intel-gfx] [PATCH] drm/i915: s/fbc_fc/fbc_false_color/

From: Ville Syrjälä We're not that short on characters that we can't spell out "false_color". Saves me from figuring out what "fc" means the next time look at the code. Cc: Rodrigo Vivi Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH v2] drm/i915: Implement fbc_status "Compressing" info for all platforms

From: Ville Syrjälä The number of compressed segments has been available ever since FBC2 was introduced in g4x, it just moved from the STATUS register into STATUS2 on IVB. For FBC1 if we really wanted the number of compressed segments we'd have to trawl through

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: Reset GPU before running subtests

On Tue, 2017-06-06 at 15:27 +0300, Ville Syrjälä wrote: > On Tue, Jun 06, 2017 at 03:20:46PM +0300, Mika Kahola wrote: > > > > It has been noticed by our CI BAT testing that in some 1%-3% > > probability > > kms_pipe_crc_basic subtest read-crc-pipe-x-frame-sequence fails > > when > > comparing

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

Quoting Michal Hocko (2017-06-06 13:14:18) > On Tue 06-06-17 13:04:36, Chris Wilson wrote: > > Similar in principle to the treatment of get_user_pages, pages that > > i915.ko acquires from shmemfs are not immediately reclaimable and so > > should be excluded from the mm accounting and vmscan until

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP

On Tue, Jun 06, 2017 at 12:24:30PM +0300, Jani Nikula wrote: > On Tue, 06 Jun 2017, Mustamin B Mustaffa > wrote: > > [...] > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index d1670b8..124f58b 100644 > > ---

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On 06/06/2017 02:14 PM, Michal Hocko wrote: > On Tue 06-06-17 13:04:36, Chris Wilson wrote: >> Similar in principle to the treatment of get_user_pages, pages that >> i915.ko acquires from shmemfs are not immediately reclaimable and so >> should be excluded from the mm accounting and vmscan until

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: Reset GPU before running subtests

On Tue, Jun 06, 2017 at 03:20:46PM +0300, Mika Kahola wrote: > It has been noticed by our CI BAT testing that in some 1%-3% probability > kms_pipe_crc_basic subtest read-crc-pipe-x-frame-sequence fails when > comparing gathered CRC frames. However, running kms_pipe_crc_basic > subtests alone i.e.

[Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: Reset GPU before running subtests

It has been noticed by our CI BAT testing that in some 1%-3% probability kms_pipe_crc_basic subtest read-crc-pipe-x-frame-sequence fails when comparing gathered CRC frames. However, running kms_pipe_crc_basic subtests alone i.e. outside BAT I was unable to replicate the issue. The patch proposes

Re: [Intel-gfx] [PATCH] drm/i915: Implement fbc_status "Compressing" info for all platforms

On Mon, Jun 05, 2017 at 05:23:17PM -0300, Paulo Zanoni wrote: > Em Qui, 2017-06-01 às 21:02 +0300, ville.syrj...@linux.intel.com > escreveu: > > From: Ville Syrjälä > > > > The number of compressed segments has been available ever since > > FBC2 was introduced in

Re: [Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

On Tue 06-06-17 13:04:36, Chris Wilson wrote: > Similar in principle to the treatment of get_user_pages, pages that > i915.ko acquires from shmemfs are not immediately reclaimable and so > should be excluded from the mm accounting and vmscan until they have > been returned to the system via

[Intel-gfx] [RFC] mm, drm/i915: Mark pinned shmemfs pages as unevictable

Similar in principle to the treatment of get_user_pages, pages that i915.ko acquires from shmemfs are not immediately reclaimable and so should be excluded from the mm accounting and vmscan until they have been returned to the system via shrink_slab/i915_gem_shrink. By moving the unreclaimable

Re: [Intel-gfx] [RFC] drm/i915: Start writeback from the shrinker

[CC linux-mm and some mm guys] On Tue 06-06-17 10:56:34, Chris Wilson wrote: > When we are called to relieve mempressue via the shrinker, the only way > we can make progress is either by discarding unwanted pages (those > objects that userspace has marked MADV_DONTNEED) or by reclaiming the >

Re: [Intel-gfx] [PATCH 4/4] lib/igt_debugfs: Only use valid values in igt_crc_to_str()

On Mon, Jun 05, 2017 at 02:28:40PM +0100, Liviu Dudau wrote: > From: Brian Starkey > > Not all elements in the crc array may be valid, so only use the valid > ones to generate the string. > > Signed-off-by: Brian Starkey Reviewed-by: Arkadiusz

Re: [Intel-gfx] [PATCH 2/4] lib/igt_kms: Fix override_mode handling

On Tue, Jun 06, 2017 at 01:30:28PM +0300, Arkadiusz Hiler wrote: > On Mon, Jun 05, 2017 at 02:28:38PM +0100, Liviu Dudau wrote: > > From: Brian Starkey > > > > igt_display_commit isn't refreshing all outputs anymore, which means > > that an override mode may never get

Re: [Intel-gfx] [PATCH 3/4] lib/igt_debugfs: Remove igt_debugfs_t

On Mon, Jun 05, 2017 at 02:28:39PM +0100, Liviu Dudau wrote: > From: Brian Starkey > > It's not used anymore, so remove it. > > Signed-off-by: Brian Starkey Reviewed-by: Arkadiusz Hiler

Re: [Intel-gfx] [PATCH 1/4] lib/igt_kms: Fix erroneous assert

On Mon, Jun 05, 2017 at 02:28:37PM +0100, Liviu Dudau wrote: > From: Brian Starkey > > In trying to fix igt_display_init() for devices without cursors, I > actually made matters worse. Fix the assert. > > Fixes: 545aa3398223 lib/igt_kms: Remove redundant cursor code >

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Add i830 "pipes power well"

On Tue, Jun 06, 2017 at 09:04:40AM +0200, Maarten Lankhorst wrote: > Op 01-06-17 om 16:36 schreef ville.syrj...@linux.intel.com: > > From: Ville Syrjälä > > > > 830 more or less requires both pipes and DPLLs to remain on as long > > as either pipe is needed.

Re: [Intel-gfx] [PATCH 2/4] lib/igt_kms: Fix override_mode handling

On Mon, Jun 05, 2017 at 02:28:38PM +0100, Liviu Dudau wrote: > From: Brian Starkey > > igt_display_commit isn't refreshing all outputs anymore, which means > that an override mode may never get picked up. > > Instead of forcing a reprobe to handle copying the

Re: [Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

Quoting Michel Thierry (2017-06-06 01:40:31) > On 6/4/2017 5:06 AM, Chris Wilson wrote: > > And whilst I'm here, we need to extend I915_PARAM_HAS_GPU_RESET to > > indicate having per-engine resets for the complimentary set of igt. > > -Chris > > > > Something like this? > > case

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Start writeback from the shrinker

== Series Details == Series: drm/i915: Start writeback from the shrinker URL : https://patchwork.freedesktop.org/series/25332/ State : success == Summary == Series 25332v1 drm/i915: Start writeback from the shrinker https://patchwork.freedesktop.org/api/1.0/series/25332/revisions/1/mbox/

Re: [Intel-gfx] [PATCH v2 3/5] ACPI / bus: Switch to use new generic UUID API

On Mon, Jun 05, 2017 at 10:37:41PM +0200, Rafael J. Wysocki wrote: > On Mon, Jun 5, 2017 at 6:20 PM, Andy Shevchenko > wrote: > > On Mon, 2017-06-05 at 18:03 +0200, Christoph Hellwig wrote: > >> > + in_params[0].buffer.pointer = (u8 *) > >> > >> Any idea

[Intel-gfx] [RFC] drm/i915: Start writeback from the shrinker

When we are called to relieve mempressue via the shrinker, the only way we can make progress is either by discarding unwanted pages (those objects that userspace has marked MADV_DONTNEED) or by reclaiming the dirty objects via swap. As we know that is the only way to make further progress, we can

Re: [Intel-gfx] [PATCH] drm: Restore GNOME monitors.xml support

On Sun, 04 Jun 2017, "H.J. Lu" wrote: > Please CC me since I am not on this mailing list. Sorry, should've instructed you to send to dri-devel instead of intel-gfx, because the patch touches drm helpers. Cc'd. BR, Jani. > > H.J. > --- > My ~/.config/monitors.xml swaps

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP

On Tue, 06 Jun 2017, Mustamin B Mustaffa wrote: > Currently, BXT_PP is hardcoded with value '0'. > It practically disabled eDP backlight on MRB (BXT) platform. > > This patch will tell which BXT_PP registers (there are two set of PP_CONTROL > in the spec) > to be

Re: [Intel-gfx] [PATCH v2] drm/i915: Remove __GFP_NORETRY from our buffer allocator

On Mon 05-06-17 16:04:55, Chris Wilson wrote: > Quoting Michal Hocko (2017-06-05 14:08:10) > > On Mon 05-06-17 13:49:38, Chris Wilson wrote: > > > Quoting Michal Hocko (2017-06-05 13:26:30) > > > > On Mon 05-06-17 11:35:12, Chris Wilson wrote: > > > > > I tried __GFP_NORETRY in the belief that

Re: [Intel-gfx] [PATCH v2] drm/i915: Remove __GFP_NORETRY from our buffer allocator

On Mon 05-06-17 11:35:12, Chris Wilson wrote: > I tried __GFP_NORETRY in the belief that __GFP_RECLAIM was effective. It > struggles with handling reclaim via kswapd (through inconsistency within > throttle_direct_reclaim() and even then the race between multiple > allocators makes the two step of

Re: [Intel-gfx] [PATCH v2] drm/i915: Remove __GFP_NORETRY from our buffer allocator

On Mon 05-06-17 14:39:17, Chris Wilson wrote: > Quoting Michal Hocko (2017-06-05 14:08:10) > > On Mon 05-06-17 13:49:38, Chris Wilson wrote: > > > Quoting Michal Hocko (2017-06-05 13:26:30) > > > > On Mon 05-06-17 11:35:12, Chris Wilson wrote: > > > > > I tried __GFP_NORETRY in the belief that

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