Re: [Intel-gfx] [RESEND-CI v4 11/15] drm/i915: prepare scaler for YCBCR420 modeset

Regards Shashank On 6/27/2017 5:46 PM, Ander Conselvan De Oliveira wrote: On Wed, 2017-06-21 at 16:04 +0530, Shashank Sharma wrote: To get a YCBCR420 output from intel platforms, we need one scaler to scale down YCBCR444 samples to YCBCR420 samples. This patch: - Does scaler allocation for

Re: [Intel-gfx] [PATCH v5 7/7] drm: create hdmi output property

Regards Shashank On 6/27/2017 5:44 PM, Ville Syrjälä wrote: On Wed, Jun 21, 2017 at 04:04:13PM +0530, Shashank Sharma wrote: HDMI displays can support various output types, based on the color space and subsampling type. The possible outputs from a HDMI 2.0 monitor could be: - RGB - YCBCR

Re: [Intel-gfx] [RESEND-CI v4 06/15] drm/edid: parse sink information before CEA blocks

Regards Shashank On 6/27/2017 5:25 PM, Ville Syrjälä wrote: On Wed, Jun 21, 2017 at 04:04:04PM +0530, Shashank Sharma wrote: CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. This block contains a map of indexes of CEA modes, which can support YCBCR 420 output also. To avoid

Re: [Intel-gfx] [RESEND-CI v4 05/15] drm/edid: parse ycbcr 420 deep color information

Regards Shashank On 6/27/2017 5:23 PM, Ville Syrjälä wrote: On Wed, Jun 21, 2017 at 04:04:03PM +0530, Shashank Sharma wrote: CEA-861-F spec adds ycbcr420 deep color support information in hf-vsdb block. This patch extends the existing hf-vsdb parsing function by adding parsing of ycbcr420

Re: [Intel-gfx] [RESEND-CI v4 04/15] drm/edid: parse YCBCR 420 videomodes from EDID

Regards Shashank On 6/27/2017 5:22 PM, Ville Syrjälä wrote: On Wed, Jun 21, 2017 at 04:04:02PM +0530, Shashank Sharma wrote: HDMI 2.0 spec adds support for YCBCR420 sub-sampled output. CEA-861-F adds two new blocks in EDID's CEA extension blocks, to provide information about sink's YCBCR420

Re: [Intel-gfx] [RESEND-CI v4 03/15] drm/edid: Complete CEA modedb(VIC 1-107)

Regards Shashank On 6/27/2017 5:02 PM, Ville Syrjälä wrote: On Wed, Jun 21, 2017 at 04:04:01PM +0530, Shashank Sharma wrote: CEA-861-F specs defines new video modes to be used with HDMI 2.0 EDIDs. The VIC range has been extended from 1-64 to 1-107. Our existing CEA modedb contains only 64

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming

the patch that introduces this error didn't land yet so, could we squash to the original patch whenever that is reworked to be resent? On Thu, Jun 29, 2017 at 6:14 PM, Manasi Navare wrote: > The Cursor Coeff is lower 6 bits in the PORT_TX_DW4 register > and hence

Re: [Intel-gfx] [PATCH] drm/i915: Setting pch_id for HSW/BDW in virtual environment

> On Thu, 29 Jun 2017, Daniel Vetter wrote: > > On Thu, Jun 15, 2017 at 11:11:45AM +0800, Xiong Zhang wrote: > >> In a IGD passthrough environment, the real ISA bridge may doesn't exist. > >> then pch_id couldn't be correctly gotten from ISA bridge, but pch_id is > >> used to

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming

== Series Details == Series: drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming URL : https://patchwork.freedesktop.org/series/26588/ State : success == Summary == Series 26588v1 drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming

[Intel-gfx] [PATCH] drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming

The Cursor Coeff is lower 6 bits in the PORT_TX_DW4 register and hence the CURSOR_COEFF_MASK should be (0x3F << 0) Signed-off-by: Manasi Navare Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1

Re: [Intel-gfx] [PATCH 10/13] drm/fb-helper: Support deferred setup (fwd)

ree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/fbdev-locking-rework-and-deferred-setup-take-2/20170629-075405 base: git://people.freedesktop.org/~airlied/linux.git drm-next :: branch date: 18 hours ago :: commit dat

Re: [Intel-gfx] [PATCH 1/7] dma-buf/dma-fence: Extract __dma_fence_is_later()

Hi, 2017-06-29 Sean Paul : > On Thu, Jun 29, 2017 at 01:59:24PM +0100, Chris Wilson wrote: > > Often we have the task of comparing two seqno known to be on the same > > context, so provide a common __dma_fence_is_later(). > > > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for

Re: [Intel-gfx] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] dma-buf/dma-fence: Extract __dma_fence_is_later() (rev4)

== Series Details == Series: series starting with [1/7] dma-buf/dma-fence: Extract __dma_fence_is_later() (rev4) URL : https://patchwork.freedesktop.org/series/26551/ State : success == Summary == Series 26551v4 Series without cover letter

Re: [Intel-gfx] [PATCH i-g-t 3/5] lib/cnl: Add Cannonlake PCI IDs for Y-skus.

Matches i915 support PCI device IDs Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for

Re: [Intel-gfx] [PATCH i-g-t 2/5] lib/cnl: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also

[Intel-gfx] [PATCH 3/4] intel/gen10: Add missed gen10 stuff

From: Ben Widawsky This got lost on rebase, I believe Signed-off-by: Ben Widawsky --- intel/intel_bufmgr_gem.c | 2 ++ intel/intel_decode.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c

[Intel-gfx] [PATCH 4/4] intel: add GEN10 to IS_9XX.

From: Paulo Zanoni As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni --- intel/intel_chipset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h

[Intel-gfx] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for

[Intel-gfx] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa Cc: Clinton Taylor

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts (rev2)

== Series Details == Series: drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts (rev2) URL : https://patchwork.freedesktop.org/series/26518/ State : success == Summary == Series 26518v2 drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

[Intel-gfx] [PATCH i-g-t 1/5] lib/cnl: Introduce Cannonlake platform defition.

Cannonlake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen10. Let's start by adding the platform definition based on previous platforms. On following patches we will start adding PCI IDs and the platform specific changes. Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH i-g-t 5/5] lib/intel_batchbuffer: Add Gen10 support for render_copy and gpgpu_fillfunc.

None of the fields we use on render_copy and gpgpu_fill has changed when compared to gen9. So let's reuse them. Signed-off-by: Rodrigo Vivi --- lib/intel_batchbuffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/intel_batchbuffer.c

[Intel-gfx] [PATCH i-g-t 4/5] lib/instdone: Add Gen10 support.

Apparently nothing changed since BDW on these instdone bits. So let's reuse instead of empty duplication. Signed-off-by: Rodrigo Vivi --- lib/instdone.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/lib/instdone.c b/lib/instdone.c index

[Intel-gfx] [PATCH i-g-t 2/5] lib/cnl: Add Cannonlake PCI IDs for U-skus.

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also the new Spec style what makes the review much more easy and straightforward. This is a copy of merged i915's

[Intel-gfx] [PATCH i-g-t 3/5] lib/cnl: Add Cannonlake PCI IDs for Y-skus.

By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Based on Anusha's kernel clean-up. Cc: Anusha Srivatsa Cc: Clinton Taylor

[Intel-gfx] [PATCH v3] dma-buf/sw-sync: Use an rbtree to sort fences in the timeline

Reduce the list iteration when incrementing the timeline by storing the fences in increasing order. v2: Prevent spinlock recursion on free during create v3: Fixup rebase conflict inside comments that escaped the compiler. Signed-off-by: Chris Wilson Cc: Sumit Semwal

[Intel-gfx] [PATCH v2] dma-buf/sw-sync: Use an rbtree to sort fences in the timeline

Reduce the list iteration when incrementing the timeline by storing the fences in increasing order. v2: Prevent spinlock recursion on free during create Signed-off-by: Chris Wilson Cc: Sumit Semwal Cc: Sean Paul Cc:

[Intel-gfx] [PATCH v2] dma-buf/sw-sync: Fix locking around sync_timeline lists

The sync_pt were not adding themselves atomically to the timeline lists, corruption imminent. Only a single list is required to track the unsignaled sync_pt, so reduce it and rename the lock more appropriately along with using idiomatic names to distinguish a list from links along it. v2:

[Intel-gfx] [PATCH v3] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

This patch fixes the DP AUX CH timeouts observed during CI IGT tests thus fixing the CI failures. This is done by adding a quirk for a particular PCI device that requires the panel power cycle delay (T12) to be set to 800ms which is 300msecs more than the minimum value specified in the eDP spec.

Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

Thanks for the review comments. Please find my responses below: On Thu, Jun 29, 2017 at 11:24:48PM +0300, Ville Syrjälä wrote: > On Wed, Jun 28, 2017 at 05:14:31PM -0700, Manasi Navare wrote: > > This patch fixes the DP AUX CH timeouts observed during CI IGT > > tests thus fixing the CI failures.

[Intel-gfx] [PATCH] dri2: Sync i965_pci_ids.h from Mesa.

Copied from Mesa with no modifications. Gives us Coffee Lake and Cannon Lake PCI IDs. Cc: Kenneth Graunke Cc: Eric Anholt Signed-off-by: Rodrigo Vivi --- hw/xfree86/dri2/pci_ids/i965_pci_ids.h | 23 +++ 1

Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

On Wed, Jun 28, 2017 at 05:14:31PM -0700, Manasi Navare wrote: > This patch fixes the DP AUX CH timeouts observed during CI IGT > tests thus fixing the CI failures. This is done by adding a > quirk for a particular PCI device that requires the panel power > cycle delay (T12) to be 300msecs more

Re: [Intel-gfx] [PATCH 1/7] dma-buf/dma-fence: Extract __dma_fence_is_later()

On Thu, Jun 29, 2017 at 01:59:24PM +0100, Chris Wilson wrote: > Often we have the task of comparing two seqno known to be on the same > context, so provide a common __dma_fence_is_later(). > > Signed-off-by: Chris Wilson > Cc: Sumit Semwal >

Re: [Intel-gfx] [PATCH] drm/i915/cfl: Fix Workarounds.

patch merged to dinq. thanks a lot for the review and sorry for causing trouble with the version of that previous patch. On Thu, Jun 29, 2017 at 1:02 PM, Pandiyan, Dhinakaran wrote: > I went and read Mika's review in [1] and also the patches posted and > committed

Re: [Intel-gfx] [PATCH 4/5] drm/i915/gen9+: Don't remove secondary power well requests

This patch makes sense and seems the right thing to do... However removing the sanitize with I915_WRITE(*, val & ~mask); doesn't give me very comfortable... I've seem many power well timeouts on cnl due the lack of that sanitize... I will try to save some time here and do some experiments with

Re: [Intel-gfx] [PATCH] drm/i915/cfl: Fix Workarounds.

I went and read Mika's review in [1] and also the patches posted and committed after that. The version currently in drm-tip deviates from his review and the fix here addresses Mika's comments correctly. Verified that BSpec does indeed say WaDisableKillLogic is applicable to only SKL and BXT.

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Add support for CCS modifiers

On Fri, Jun 23, 2017 at 09:45:44AM -0700, Ben Widawsky wrote: > v2: > Support sprite plane. > Support pipe C/D limitation on GEN9. > > This requires rebase on the correct Ville patches > > Cc: Daniel Stone > Cc: Kristian Høgsberg > Signed-off-by: Ben

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add format modifiers for Intel

On Fri, Jun 23, 2017 at 09:45:43AM -0700, Ben Widawsky wrote: > This was based on a patch originally by Kristian. It has been modified > pretty heavily to use the new callbacks from the previous patch. > > v2: > - Add LINEAR and Yf modifiers to list (Ville) > - Combine i8xx and i965 into one

Re: [Intel-gfx] [PATCH 2/4] drm: Create a format/modifier blob

On Fri, Jun 23, 2017 at 09:45:42AM -0700, Ben Widawsky wrote: > Updated blob layout (Rob, Daniel, Kristian, xerpi) > > v2: > * Removed __packed, and alignment (.+) > * Fix indent in drm_format_modifier fields (Liviu) > * Remove duplicated modifier > 64 check (Liviu) > * Change comment about

Re: [Intel-gfx] [PATCH v4 5/5] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

On Thu, Jun 29, 2017 at 06:57:30PM +0100, Chris Wilson wrote: > Quoting ville.syrj...@linux.intel.com (2017-06-29 15:36:42) > > From: Ville Syrjälä > > > > Introduce an rw_semaphore to protect the display commits. All normal > > commits use down_read() and hence

Re: [Intel-gfx] [PATCH 2/5] drm/i915/skl: Don't disable misc IO power well during display uninit

Indeed very clear there... I don't know how did this never caused any big trouble... Reviewed-by: Rodrigo Vivi On Thu, Jun 29, 2017 at 8:36 AM, Imre Deak wrote: > Bspec requires leaving the misc IO power well enabled during display > uninit, so

Re: [Intel-gfx] [PATCH 7/7] dma-buf/sw-sync: Use an rbtree to sort fences in the timeline

Quoting Sean Paul (2017-06-29 19:10:11) > On Thu, Jun 29, 2017 at 01:59:30PM +0100, Chris Wilson wrote: > > Reduce the list iteration when incrementing the timeline by storing the > > fences in increasing order. > > > > Signed-off-by: Chris Wilson > > Cc: Sumit Semwal

Re: [Intel-gfx] [PATCH 1/5] drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disabling

Oh! indeed! Reviewed-by: Rodrigo Vivi On Thu, Jun 29, 2017 at 8:36 AM, Imre Deak wrote: > Bspec requires a 10 us delay after disabling power well 1 and - if not > toggled on-demand - the AUX IO power wells during display uninit. > > Signed-off-by:

Re: [Intel-gfx] [PATCH 7/7] dma-buf/sw-sync: Use an rbtree to sort fences in the timeline

On Thu, Jun 29, 2017 at 01:59:30PM +0100, Chris Wilson wrote: > Reduce the list iteration when incrementing the timeline by storing the > fences in increasing order. > > Signed-off-by: Chris Wilson > Cc: Sumit Semwal > Cc: Sean Paul

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bxt, glk: Fix assert on conditions for DC9 enabling

"Disable all display engine functions using the full mode set disable sequence on all pipes, transcoders, ports, planes, and power well 2 (PG2)." I hope at this point we really already did all the rest besides the PG2. Anyways I believe this patch itself makes total sense so: Reviewed-by:

Re: [Intel-gfx] [PATCH 5/5] drm/i915/cnl: Fix comment about AUX IO power well enable/disable

Reviewed-by: Rodrigo Vivi On Thu, Jun 29, 2017 at 8:37 AM, Imre Deak wrote: > The comments match an earlier version of the patch, fix them to match > the current state. > > Signed-off-by: Imre Deak > --- >

Re: [Intel-gfx] [PATCH v4 5/5] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

Quoting ville.syrj...@linux.intel.com (2017-06-29 15:36:42) > From: Ville Syrjälä > > Introduce an rw_semaphore to protect the display commits. All normal > commits use down_read() and hence can proceed in parallel, but GPU reset > will use down_write() making sure

Re: [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

series merged to libdrm. thanks for patches and review. On Wed, Jun 28, 2017 at 2:09 PM, Clint Taylor wrote: > > > On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: >> >> Add the PCI IDs for U SKU IN CFL by following the spec. >> >> v2: Update IDs >> >> Cc: Rodrigo Vivi

Re: [Intel-gfx] [RESEND i-g-t 3/3] lib/cfl: Add PCI Ids for U SKU in CFl

series merged. thanks for the patches and reviews. On Wed, 2017-06-28 at 23:16 -0700, Anusha Srivatsa wrote: > Follow the spec and add ID for U SKU > > v2: Update IDs in accordance to the kernel commit: > d29fe702c9cb682df99146d24d06e5455f043101 (Chris) > > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH i-g-t] lib/cfl: Introduce Coffeelake platform definition.

patch merged. thanks for the review. On Thu, 2017-06-29 at 10:35 -0700, Clint Taylor wrote: > Identical to other platforms. > > Reviewed-by: Clinton Taylor > > On 06/29/2017 10:18 AM, Rodrigo Vivi wrote: > > Coffeelake is a Intel® Processor containing Intel® HD

Re: [Intel-gfx] [PATCH i-g-t] Add support for subtest-specific documentation

On 2017-06-22 07:30 AM, Petri Latvala wrote: The current documentation for tests is limited to a single string per test binary. This patch adds support for documenting individual subtests. The syntax for subtest documentation is: igt_subtest_documentation("Frob knobs to see if one of the

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/skl+: Scaling not supported in IF-ID Interlace mode

On Thu, Jun 29, 2017 at 10:10:30PM +0530, Mahesh Kumar wrote: > GEN9+ Interlace fetch mode doesn't support pipe/plane scaling, > This patch adds check to fail the flip if pipe/plane scaling is > requested in Interlace fetch mode. > > Changes since V1: > - move check to skl_update_scaler (ville)

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

On Thu, Jun 29, 2017 at 10:10:29PM +0530, Mahesh Kumar wrote: > In Gen9 platform Interlaced fetch mode doesn't support following plane > configuration: > - Y/Yf tiling > - 90/270 rotation > - YUV420 hybrid planar source pixel formats. > > This patch adds check to fail the flip if any of the

Re: [Intel-gfx] [PATCH i-g-t] lib/cfl: Introduce Coffeelake platform definition.

Identical to other platforms. Reviewed-by: Clinton Taylor On 06/29/2017 10:18 AM, Rodrigo Vivi wrote: Coffeelake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. On following patches we

Re: [Intel-gfx] [PATCH 6/7] dma-buf/sw-sync: Fix locking around sync_timeline lists

Quoting Sean Paul (2017-06-29 18:22:10) > On Thu, Jun 29, 2017 at 01:59:29PM +0100, Chris Wilson wrote: > > The sync_pt were not adding themselves atomically to the timeline lists, > > corruption imminent. Only a single list is required to track the > > unsignaled sync_pt, so reduce it and rename

Re: [Intel-gfx] [PATCH 6/7] dma-buf/sw-sync: Fix locking around sync_timeline lists

On Thu, Jun 29, 2017 at 01:59:29PM +0100, Chris Wilson wrote: > The sync_pt were not adding themselves atomically to the timeline lists, > corruption imminent. Only a single list is required to track the > unsignaled sync_pt, so reduce it and rename the lock more appropriately > along with using

[Intel-gfx] [PATCH i-g-t] lib/cfl: Introduce Coffeelake platform definition.

Coffeelake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. On following patches we will start adding PCI IDs and the platform specific changes. Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] ✗ Fi.CI.BAT: warning for Handle unsupported configuration with IF-ID (rev2)

== Series Details == Series: Handle unsupported configuration with IF-ID (rev2) URL : https://patchwork.freedesktop.org/series/26546/ State : warning == Summary == Series 26546v2 Handle unsupported configuration with IF-ID

Re: [Intel-gfx] [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle

On 6/29/2017 6:07 AM, Chris Wilson wrote: Quoting Ville Syrjälä (2017-06-29 14:05:25) On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote: There's no need to keep reading random registers in i915_swizzle_info if the platform is not doing GPU side swizzling. After HSW, swizzling is

[Intel-gfx] [PATCH v2 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

In Gen9 platform Interlaced fetch mode doesn't support following plane configuration: - Y/Yf tiling - 90/270 rotation - YUV420 hybrid planar source pixel formats. This patch adds check to fail the flip if any of the above configuration is requested. Changes since V1: - handle checks in

[Intel-gfx] [PATCH v2 2/2] drm/i915/skl+: Scaling not supported in IF-ID Interlace mode

GEN9+ Interlace fetch mode doesn't support pipe/plane scaling, This patch adds check to fail the flip if pipe/plane scaling is requested in Interlace fetch mode. Changes since V1: - move check to skl_update_scaler (ville) - mode to adjusted_mode (ville) - combine pipe/plane scaling check

[Intel-gfx] [PATCH v2 0/2] Handle unsupported configuration with IF-ID

Gen9+ Interlace fetch mode doesn't support few plane configurations & pipe scaling. - Y-tile - 90/270 rotation - pipe/plane scaling - 420 planar formats Changes since V1: - Address review comments from ville Mahesh Kumar (2): drm/i915/skl+: Check for supported plane configuration in

[Intel-gfx] ✓ Fi.CI.BAT: success for gen9+: Sanitize power well disabling during display uninit

== Series Details == Series: gen9+: Sanitize power well disabling during display uninit URL : https://patchwork.freedesktop.org/series/26566/ State : success == Summary == Series 26566v1 gen9+: Sanitize power well disabling during display uninit

Re: [Intel-gfx] [PATCH] drm/i915: Setting pch_id for HSW/BDW in virtual environment

On Thu, Jun 29, 2017 at 06:22:45PM +0300, Jani Nikula wrote: > On Thu, 29 Jun 2017, Daniel Vetter wrote: > > On Thu, Jun 15, 2017 at 11:11:45AM +0800, Xiong Zhang wrote: > >> In a IGD passthrough environment, the real ISA bridge may doesn't exist. > >> then pch_id couldn't be

Re: [Intel-gfx] [PATCH 05/20] drm/i915: introduce page_size members

On 2017.06.29 12:59:08 +0100, Chris Wilson wrote: > Quoting Matthew Auld (2017-06-29 12:54:51) > > On 29 June 2017 at 07:36, Zhenyu Wang wrote: > > > We need to fallback to default supported page size when vGPU is active > > > (intel_vgpu_active() is true). > > >

[Intel-gfx] [PATCH 0/5] gen9+: Sanitize power well disabling during display uninit

This patchset aligns the display uninit sequence with Bspec, wrt. to disabling power well 1 and the misc IO power well. It also tunes down a timeout WARN to be a debug message when waiting for power wells to get disabled while KVMR is active. Imre Deak (5): drm/i915/gen9+: Add 10 us delay after

[Intel-gfx] [PATCH 3/5] drm/i915/bxt, glk: Fix assert on conditions for DC9 enabling

What we want to assert based on the conditions required by Bspec is that power well 2 is disabled, so no need to check for other power wells. In addition we can only check if the driver's request is removed, the actual state depends on whether the other request bits are set or not (BIOS, KVMR,

[Intel-gfx] [PATCH 1/5] drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disabling

Bspec requires a 10 us delay after disabling power well 1 and - if not toggled on-demand - the AUX IO power wells during display uninit. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_runtime_pm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid undefined behaviour of "u32 >> 32" (rev2)

Quoting Patchwork (2017-06-29 16:27:13) > == Series Details == > > Series: drm/i915: Avoid undefined behaviour of "u32 >> 32" (rev2) > URL : https://patchwork.freedesktop.org/series/26556/ > State : success > > == Summary == > > Series 26556v2 drm/i915: Avoid undefined behaviour of "u32 >>

[Intel-gfx] [PATCH 5/5] drm/i915/cnl: Fix comment about AUX IO power well enable/disable

The comments match an earlier version of the patch, fix them to match the current state. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 2/5] drm/i915/skl: Don't disable misc IO power well during display uninit

Bspec requires leaving the misc IO power well enabled during display uninit, so align the code accordingly. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_runtime_pm.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 4/5] drm/i915/gen9+: Don't remove secondary power well requests

So far in an attempt to make sure all power wells get disabled during display uninitialization the driver removed any secondary request bits (BIOS, KVMR, DEBUG) that were set for a given power well. The known source for these requests was DMC's request on power well 1 and the misc IO power well.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid undefined behaviour of "u32 >> 32" (rev2)

== Series Details == Series: drm/i915: Avoid undefined behaviour of "u32 >> 32" (rev2) URL : https://patchwork.freedesktop.org/series/26556/ State : success == Summary == Series 26556v2 drm/i915: Avoid undefined behaviour of "u32 >> 32"

Re: [Intel-gfx] [PATCH] drm/i915: Setting pch_id for HSW/BDW in virtual environment

On Thu, 29 Jun 2017, Daniel Vetter wrote: > On Thu, Jun 15, 2017 at 11:11:45AM +0800, Xiong Zhang wrote: >> In a IGD passthrough environment, the real ISA bridge may doesn't exist. >> then pch_id couldn't be correctly gotten from ISA bridge, but pch_id is >> used to identify

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix pre-g4x GPU reset, again

On Thu, Jun 29, 2017 at 02:24:21PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix pre-g4x GPU reset, again > URL : https://patchwork.freedesktop.org/series/26554/ > State : success > > == Summary == > > Series 26554v1 drm/i915: Fix pre-g4x GPU reset, again >

[Intel-gfx] [PATCH v2] drm/i915: Avoid undefined behaviour of "u32 >> 32"

When computing a hash for looking up relcoation target handles in an execbuf, we start with a large size for the hashtable and proceed to reduce it until the allocation suceeds. The final attempt is with an order of 0 (i.e. a single element). This means that we then pass bits=0 to hash_32() which

Re: [Intel-gfx] [PATCH] drm/i915: Avoid undefined behaviour of "u32 >> 32"

Quoting Tvrtko Ursulin (2017-06-29 15:50:17) > > On 29/06/2017 14:49, Chris Wilson wrote: > > When computing a hash for looking up relcoation target handles in an > > execbuf, we start with a large size for the hashtable and proceed to > > reduce it until the allocation suceeds. The final attempt

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix pre-g4x GPU reset, again (rev2)

== Series Details == Series: drm/i915: Fix pre-g4x GPU reset, again (rev2) URL : https://patchwork.freedesktop.org/series/26554/ State : success == Summary == Series 26554v2 drm/i915: Fix pre-g4x GPU reset, again https://patchwork.freedesktop.org/api/1.0/series/26554/revisions/2/mbox/ Test

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

Hi, On Thursday 29 June 2017 07:46 PM, Ville Syrjälä wrote: On Thu, Jun 29, 2017 at 02:27:40PM +0530, Mahesh Kumar wrote: GEN9+ Interlace fetch mode doesn't support pipe scaling, This patch adds check to fail the flip if pipe scaling is requested in Interlace fetch mode. Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915: Avoid undefined behaviour of "u32 >> 32"

On 29/06/2017 14:49, Chris Wilson wrote: When computing a hash for looking up relcoation target handles in an execbuf, we start with a large size for the hashtable and proceed to reduce it until the allocation suceeds. The final attempt is with an order of 0 (i.e. a single element). This means

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid undefined behaviour of "u32 >> 32"

== Series Details == Series: drm/i915: Avoid undefined behaviour of "u32 >> 32" URL : https://patchwork.freedesktop.org/series/26556/ State : success == Summary == Series 26556v1 drm/i915: Avoid undefined behaviour of "u32 >> 32"

[Intel-gfx] [PATCH v4 5/5] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

From: Ville Syrjälä Introduce an rw_semaphore to protect the display commits. All normal commits use down_read() and hence can proceed in parallel, but GPU reset will use down_write() making sure no other commits are in progress when we have to pull the plug on the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix pre-g4x GPU reset, again

== Series Details == Series: drm/i915: Fix pre-g4x GPU reset, again URL : https://patchwork.freedesktop.org/series/26554/ State : success == Summary == Series 26554v1 drm/i915: Fix pre-g4x GPU reset, again https://patchwork.freedesktop.org/api/1.0/series/26554/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH] drm/atomic: Add missing drm_atomic_state_clear to atomic_remove_fb

On Thu, Jun 29, 2017 at 04:57:25PM +0300, Ville Syrjälä wrote: > On Thu, Jun 29, 2017 at 01:59:54PM +0200, Maarten Lankhorst wrote: > > Signed-off-by: Maarten Lankhorst > > --- > > drivers/gpu/drm/drm_framebuffer.c | 1 + > > 1 file changed, 1 insertion(+) > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

Hi, On Thursday 29 June 2017 07:36 PM, Ville Syrjälä wrote: On Thu, Jun 29, 2017 at 02:27:39PM +0530, Mahesh Kumar wrote: In Gen9 platform Interlaced fetch mode doesn't support following plane configuration: - Y/Yf tiling - 90/270 rotation - Scaling - YUV420 hybrid planar source pixel

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

On Thu, Jun 29, 2017 at 02:27:40PM +0530, Mahesh Kumar wrote: > GEN9+ Interlace fetch mode doesn't support pipe scaling, > This patch adds check to fail the flip if pipe scaling is requested in > Interlace fetch mode. > > Signed-off-by: Mahesh Kumar > --- >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] dma-buf/dma-fence: Extract __dma_fence_is_later()

== Series Details == Series: series starting with [1/7] dma-buf/dma-fence: Extract __dma_fence_is_later() URL : https://patchwork.freedesktop.org/series/26551/ State : success == Summary == Series 26551v1 Series without cover letter

Re: [Intel-gfx] [PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

On Thu, Jun 29, 2017 at 02:27:39PM +0530, Mahesh Kumar wrote: > In Gen9 platform Interlaced fetch mode doesn't support following plane > configuration: > - Y/Yf tiling > - 90/270 rotation > - Scaling > - YUV420 hybrid planar source pixel formats. > > This patch adds check to fail the flip if

Re: [Intel-gfx] [PATCH] drm/atomic: Add missing drm_atomic_state_clear to atomic_remove_fb

On Thu, Jun 29, 2017 at 01:59:54PM +0200, Maarten Lankhorst wrote: > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/drm_framebuffer.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_framebuffer.c >

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

Quoting ville.syrj...@linux.intel.com (2017-06-29 14:49:48) > @@ -2640,15 +2600,13 @@ static void i915_reset_device(struct drm_i915_private > *dev_priv) > char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; > char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; >

[Intel-gfx] [PATCH] drm/i915: Avoid undefined behaviour of "u32 >> 32"

When computing a hash for looking up relcoation target handles in an execbuf, we start with a large size for the hashtable and proceed to reduce it until the allocation suceeds. The final attempt is with an order of 0 (i.e. a single element). This means that we then pass bits=0 to hash_32() which

[Intel-gfx] [PATCH 5/5] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

From: Ville Syrjälä Introduce an rw_semaphore to protect the display commits. All normal commits use down_read() and hence can proceed in parallel, but GPU reset will use down_write() making sure no other commits are in progress when we have to pull the plug on the

[Intel-gfx] [PATCH 2/5] drm/atomic: Introduce drm_atomic_helper_duplicate_committed_state()

From: Ville Syrjälä For i915 GPU reset handling we'll want to be able to duplicate the state that was last committed to the hardware. For that purpose let's provide a helper function that is supposed to duplicate the state last committed to the hardware. For now

[Intel-gfx] [PATCH 4/5] drm/i915: Refactor __intel_atomic_commit_tail()

From: Ville Syrjälä Split intel_atomic_commit_tail() into a lower level function that does the actual commit, and a higher level one that waits for the dependencies and signals the commit as done. We'll reuse the lower level function to perform commits during GPU

[Intel-gfx] [PATCH 1/5] drm/atomic: Refactor drm_atomic_state_realloc_connectors()

From: Ville Syrjälä Pull the code to reallocate the state->connectors[] array into a helper function. We'll have another use for this later. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_atomic.c | 43

[Intel-gfx] [PATCH 3/5] drm/i915% Store vma gtt offset in plane state

From: Ville Syrjälä To avoid having to deference plane_state->vma during the commit phase of plane updates, let's store the vma gtt offset (or the bus address when we need it) in the plane state. This is crucial for doing the modeset operations during GPU reset as

[Intel-gfx] [PATCH 0/5] drm/i915: Fix pre-g4x GPU reset, again

From: Ville Syrjälä I set out to fix the pre-g4x GPU reset by protecting display commits with an rw_semaphore. I originally went all out and added infrastructure to track the committed state (as opposed the latest swapped state), but Daniel suggested that we want

Re: [Intel-gfx] [PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

On Wed, Jun 28, 2017 at 06:06:05PM -0300, Gabriel Krisman Bertazi wrote: > There are still cases on these platforms where an attempt is made to > configure the CDCLK while the power domain is off, like when coming back > from a suspend. So the workaround below is still needed. > > This

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