From: Tina Zhang
Enable the guest i915 48bit full ppgtt functionality when host can provide
the capability. vgt_caps is introduced to guest i915 driver to get the vgpu
capabilities from the device model. VGT_CAPS_FULL_PPGTT_48BIT is one of the
capabilities type which let guest i915 dirver know th
From: Tina Zhang
Guest i915 48bit full ppgtt functionality was blocking by an issue, which
would lead to gpu hardware hang. Guest i915 driver may update the ppgtt
table just before this workload is going to be submitted to the hardware
by device model. This case wasn't handled well by device mode
On 2017.07.07 15:29:38 +0800, Zhenyu Wang wrote:
> From: Tina Zhang
>
> Enable the guest i915 48bit full ppgtt functionality when host can provide
> the capability. vgt_caps is introduced to guest i915 driver to get the vgpu
> capabilities from the device model. VGT_CAPS_FULL_PPGTT_48BIT is one o
== Series Details ==
Series: YCBCR 4:2:0 handling in DRM layer
URL : https://patchwork.freedesktop.org/series/26972/
State : success
== Summary ==
Series 26972v1 YCBCR 4:2:0 handling in DRM layer
https://patchwork.freedesktop.org/api/1.0/series/26972/revisions/1/mbox/
Test gem_exec_flush:
== Series Details ==
Series: drm/i915: Fix the kernel panic when using aliasing ppgtt
URL : https://patchwork.freedesktop.org/series/26977/
State : warning
== Summary ==
Series 26977v1 drm/i915: Fix the kernel panic when using aliasing ppgtt
https://patchwork.freedesktop.org/api/1.0/series/269
On 7 July 2017 at 07:00, Chuanxiao Dong wrote:
> The ppgtt should be get directly from i915_address_space *vm instead of
> vma->vm as in alias ppgtt case the vma->vm is not same with vm.
>
> Fixes: 4a234c5fae16 ("drm/i915: pass the vma to insert_entries")
> Bugzilla:https://bugs.freedesktop.org/sh
== Series Details ==
Series: series starting with [v7,1/2] drm/i915: Enable guest i915 48bit full
ppgtt functionality
URL : https://patchwork.freedesktop.org/series/26980/
State : success
== Summary ==
Series 26980v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series
== Series Details ==
Series: drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.
URL : https://patchwork.freedesktop.org/series/26956/
State : success
== Summary ==
Series 26956v1 drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.
https://patchwork.freedesktop.org/
Quoting Chuanxiao Dong (2017-07-07 07:00:09)
> The ppgtt should be get directly from i915_address_space *vm instead of
> vma->vm as in alias ppgtt case the vma->vm is not same with vm.
And for consistency, also
@@ -2242,7 +2242,7 @@ static void bxt_vtd_ggtt_insert_entries__BKL(struct
i915_addres
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Friday, July 7, 2017 5:38 PM
> To: Dong, Chuanxiao ; intel-
> g...@lists.freedesktop.org
> Cc: intel-gvt-...@lists.freedesktop.org; Dong, Chuanxiao
> ; Auld, Matthew ;
> Zhenyu Wang
> Subject: Re: [PATCH] d
The ppgtt should be get directly from i915_address_space *vm instead of
vma->vm.
v2:
- add one more fix for bxt. (Chris)
Fixes: 4a234c5fae16 ("drm/i915: pass the vma to insert_entries")
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=101713
Signed-off-by: Chuanxiao Dong
Reviewed-by: Matthe
Quoting Chuanxiao Dong (2017-07-07 10:50:59)
> The ppgtt should be get directly from i915_address_space *vm instead of
> vma->vm.
>
> v2:
> - add one more fix for bxt. (Chris)
>
> Fixes: 4a234c5fae16 ("drm/i915: pass the vma to insert_entries")
> Bugzilla:https://bugs.freedesktop.org/show_bug.cgi
== Series Details ==
Series: drm/i915: Fix the kernel panic when using aliasing ppgtt (rev2)
URL : https://patchwork.freedesktop.org/series/26977/
State : success
== Summary ==
Series 26977v2 drm/i915: Fix the kernel panic when using aliasing ppgtt
https://patchwork.freedesktop.org/api/1.0/ser
On Fri, Mar 17, 2017 at 12:15 PM, Joonas Lahtinen
wrote:
> On to, 2017-03-16 at 13:20 +, Chris Wilson wrote:
>> Currently, the last object in the execlist is the always the batch.
>> However, when building the batch buffer we often know the batch object
>> first and if we can use the first slo
From: Ville Syrjälä
Currently the .modeset_calc_cdclk() hooks check the final cdclk value
against the max allowed. That's not really sufficient since the low
level calc_cdclk() functions effectively clamp the minimum required
cdclk to the max supported by the platform. Hence if the minimum
requir
From: Ville Syrjälä
Make the min_pixclk thing less confusing by changing it to track
the minimum acceptable cdclk frequency instead. This means moving
the application of the guardbands to a slightly higher level from
the low level platform specific calc_cdclk() functions.
The immediate benefit i
From: Ville Syrjälä
Follow the GLK path when computing cdclk and related limits. CNL
pipes also produce two pixels per clock, so that's what we should
use.
For the HBR2 vs. audio issue the limit should more correctly be 336
MHz, but the GLK limit of 316.8 MHz works just as well and results
in pi
Quoting Ben Widawsky (2017-07-07 00:27:01)
> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 13 +
> include/uapi/drm/i915_drm.h | 8
> 4 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --g
Quoting Marc MERLIN (2017-07-07 06:40:51)
> Is this the right place to send this?
> Can anyone help?
>
> On Wed, Jul 05, 2017 at 11:33:01PM -0700, Marc MERLIN wrote:
> > Howdy,
> >
> > I have a thinkpad P70 with debian testing and 4.11.6 kernel.
> > A recent-ish upgrade broke something and now I'
On Thu, Jul 06, 2017 at 03:03:15PM +0200, Maarten Lankhorst wrote:
> Op 06-07-17 om 13:09 schreef Tomeu Vizoso:
> > Looks good to me:
> >
> > Reviewed-by: Tomeu Vizoso
> >
> > I guess you have tested this with IGT? In any case, I think it would
> > be good to mention how a patch has been tested in
On 7 July 2017 at 11:34, Chris Wilson wrote:
> Quoting Ben Widawsky (2017-07-07 00:27:01)
>> drivers/gpu/drm/i915/i915_drv.c | 3 +++
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/i915_pci.c | 13 +
>> include/uapi/drm/i915_drm.h | 8
>> 4 files ch
== Series Details ==
Series: series starting with [1/3] drm/i915: Fix up CNL cdclk related limits
URL : https://patchwork.freedesktop.org/series/26988/
State : success
== Summary ==
Series 26988v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/26988/revisions/1/mb
Quoting Daniel Vetter (2017-07-07 11:17:22)
> On Fri, Mar 17, 2017 at 12:15 PM, Joonas Lahtinen
> wrote:
> > On to, 2017-03-16 at 13:20 +, Chris Wilson wrote:
> >> Currently, the last object in the execlist is the always the batch.
> >> However, when building the batch buffer we often know the
On Thu, Jul 06, 2017 at 11:24:41PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> For i915 GPU reset handling we'll want to be able to duplicate the state
> that was last commited to the hardware. For that purpose let's start to
> track the commited state for each object an
On Thu, Jul 06, 2017 at 01:41:13PM -0700, Rodrigo Vivi wrote:
> Apparently no change on RPS stuff from previous platforms.
>
> v2: Merging to rps related patches in one and also adding
> missed cases.
>
> Cc: David Weinehall
> Signed-off-by: Rodrigo Vivi
Double-checking BSpec didn't yield
On Fri, Jul 07, 2017 at 02:03:38PM +0200, Daniel Vetter wrote:
> On Thu, Jul 06, 2017 at 11:24:41PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > For i915 GPU reset handling we'll want to be able to duplicate the state
> > that was last commited to the hardware. For
On Thu, Jul 6, 2017 at 9:00 AM, Daniel Vetter wrote:
> From: Thierry Reding
>
> The FB helper core now supports deferred setup, so the driver's custom
> implementation can be removed.
>
> v2: Dont' resurrect drm_vblank_cleanup.
>
> Cc: Xinliang Liu
> Cc: Rongrong Zou
> Cc: Xinwei Kong
> Cc: Ch
On Fri, Jun 30, 2017 at 01:11:52PM -0700, Rodrigo Vivi wrote:
> On Fri, Jun 30, 2017 at 12:12 PM, Jim Bride wrote:
> > Factor out some code that was replicated in three test utilities into
> > some new IGT library functions so that we are checking PSR status in
> > a consistent fashion across all
On Fri, Jun 30, 2017 at 05:54:32PM -0300, Paulo Zanoni wrote:
> Em Sex, 2017-06-30 às 12:12 -0700, Jim Bride escreveu:
> > Factor out some code that was replicated in three test utilities into
> > some new IGT library functions so that we are checking PSR status in
> > a consistent fashion across a
On Fri, Jul 7, 2017 at 3:21 PM, Ville Syrjälä
wrote:
> On Fri, Jul 07, 2017 at 02:03:38PM +0200, Daniel Vetter wrote:
>> On Thu, Jul 06, 2017 at 11:24:41PM +0300, ville.syrj...@linux.intel.com
>> wrote:
>> > From: Ville Syrjälä
>> >
>> > For i915 GPU reset handling we'll want to be able to dupli
Check that all the power well IDs are unique on the given platform.
v2:
- Fix using BIT_ULL() instead of BIT() for 64 bit mask.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtim
== Series Details ==
Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2)
URL : https://patchwork.freedesktop.org/series/26922/
State : success
== Summary ==
Series 26922v2 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26
On Fri, Jul 07, 2017 at 04:05:28PM +0200, Daniel Vetter wrote:
> On Fri, Jul 7, 2017 at 3:21 PM, Ville Syrjälä
> wrote:
> > On Fri, Jul 07, 2017 at 02:03:38PM +0200, Daniel Vetter wrote:
> >> On Thu, Jul 06, 2017 at 11:24:41PM +0300, ville.syrj...@linux.intel.com
> >> wrote:
> >> > From: Ville Sy
On Fri, Jul 7, 2017 at 3:34 AM, Chris Wilson
wrote:
> Quoting Ben Widawsky (2017-07-07 00:27:01)
> > drivers/gpu/drm/i915/i915_drv.c | 3 +++
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 13 +
> > include/uapi/drm/i915_drm.h | 8
> >
On Thu, Jul 6, 2017 at 4:27 PM, Ben Widawsky wrote:
> We don't yet have optimal MOCS settings, but we have enough to know how
> to at least determine when we might have non-optimal settings within our
> driver.
>
> Signed-off-by: Ben Widawsky
> ---
> src/intel/vulkan/anv_device.c |
patch merged to dinq. thanks for reviewing.
On Thu, Jul 6, 2017 at 2:52 PM, Clint Taylor wrote:
>
>
> On 07/06/2017 02:08 PM, Rodrigo Vivi wrote:
>>
>> Cannon Lake's VBT that is currently available for B0 stepping
>> states that port D uses alternate pin 3 messing up with the
>> default pin-port
patch merged to dinq. thanks for reviewing.
On Fri, Jul 7, 2017 at 5:03 AM, David Weinehall
wrote:
> On Thu, Jul 06, 2017 at 01:41:13PM -0700, Rodrigo Vivi wrote:
>> Apparently no change on RPS stuff from previous platforms.
>>
>> v2: Merging to rps related patches in one and also adding
>> m
patch merged to dinq. thanks for reviewing.
On Thu, Jul 6, 2017 at 7:51 PM, Ben Widawsky
wrote:
> On 17-07-06 14:06:24, Vivi, Rodrigo wrote:
>>
>> No change on render context size is required for Gen10.
>>
>> So this patch doesn't change the default behaviour,
>> but only avoid the missing_case m
Signed-off-by: Lionel Landwerlin
---
tests/perf.c | 135 +++
1 file changed, 135 insertions(+)
diff --git a/tests/perf.c b/tests/perf.c
index db28ba1f..14bbb361 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -146,6 +146,33 @@ enum drm_i915
patch merged to dinq.
On Thu, Jul 6, 2017 at 1:52 PM, Rodrigo Vivi wrote:
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> v2: Mika pointed out that 24 was hardcoded while it
> should consider ref clock that can b
From: Matthew Auld
The motivation behind this new interface is expose at runtime the
creation of new OA configs which can be used as part of the i915 perf
open interface. This will enable the kernel to learn new configs which
may be experimental, or otherwise not part of the core set currently
av
Hi,
This series adds support for loadable OA configurations. It is based
off Matthew's initial work. This idea is to let userspace mostly hold
these configurations, so they can be tweaked from userspace without
patching the kernel, which is quite useful for debug purposes.
I've made sent IGT test
The goal here was to minimise doing any thing or any check inside the
kernel that was not strictly required. For a userspace that assumes
complete control over the cache domains, the kernel is usually using
outdated information and may trigger clflushes where none were
required.
However, swapping
On Fri, Jul 07, 2017 at 11:47:25AM +0100, Chris Wilson wrote:
> Quoting Marc MERLIN (2017-07-07 06:40:51)
> > Is this the right place to send this?
> > Can anyone help?
> >
> > On Wed, Jul 05, 2017 at 11:33:01PM -0700, Marc MERLIN wrote:
> > > Howdy,
> > >
> > > I have a thinkpad P70 with debian
Quoting Lionel Landwerlin (2017-07-07 18:08:37)
> +static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32
> addr)
> +{
> + static const i915_reg_t flex_eu_regs[] = {
> + EU_PERF_CNTL0,
> + EU_PERF_CNTL1,
> + EU_PERF_CNTL2,
> +
I will review the series more carefully later,
but my concern is that with this series applied I got a blank screen on eDP...
On Fri, Jul 7, 2017 at 3:24 AM, wrote:
> From: Ville Syrjälä
>
> Follow the GLK path when computing cdclk and related limits. CNL
> pipes also produce two pixels per cl
On Thu, Jul 06, 2017 at 01:45:08PM -0700, Rodrigo Vivi wrote:
> This is a follow-up after enabling DC states with
> commit: "drm/i915/DMC/CNL: Load DMC on CNL".
>
> Cc: Anusha Srivatsa
> Cc: Imre Deak
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Imre Deak
We could add max_dc_state to intel_dev
== Series Details ==
Series: drm/i915/perf: Add support for loadable OA configs
URL : https://patchwork.freedesktop.org/series/27011/
State : success
== Summary ==
Series 27011v1 drm/i915/perf: Add support for loadable OA configs
https://patchwork.freedesktop.org/api/1.0/series/27011/revisions
== Series Details ==
Series: drm/i915: Force CPU synchronisation even if userspace requests ASYNC
URL : https://patchwork.freedesktop.org/series/27012/
State : success
== Summary ==
Series 27012v1 drm/i915: Force CPU synchronisation even if userspace requests
ASYNC
https://patchwork.freedeskt
On Fri, Jul 07, 2017 at 10:54:47AM -0700, Rodrigo Vivi wrote:
> I will review the series more carefully later,
> but my concern is that with this series applied I got a blank screen on eDP...
Hmm. Oh, I guess we could now be going for a lower cdclk that before
since we now account for 2 pixels per
On Fri, Jul 07, 2017 at 01:24:49PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Make the min_pixclk thing less confusing by changing it to track
> the minimum acceptable cdclk frequency instead. This means moving
> the application of the guardbands to a slightly higher le
iirc I assumed 1 pixel per clk for CNL when I originally submitted the
workaround patch because cnl_xxx_calc_cdclk() functions assume that. Are we
missing something in the cdclk setup code to enable 2 pixels per clk?
-DK
From: Ville Syrjälä [ville.syrj...
On 17-07-07 11:34:48, Chris Wilson wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
include/uapi/drm/i915_drm.h | 8
4 files changed, 22 insertio
On 17-07-07 09:23:26, Jason Ekstrand wrote:
On Fri, Jul 7, 2017 at 3:34 AM, Chris Wilson
wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
> include/uapi
Em Sex, 2017-06-30 às 12:12 -0700, Jim Bride escreveu:
> The multidraw subtest was not taking whether or not the GEM buffer
> had
> ever been in write-combining mode when checking for PSR state, so fix
> that.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Jim Bride
> ---
> tests/kms_frontbuffe
Quoting Ben Widawsky (2017-07-07 19:42:25)
> On 17-07-07 11:34:48, Chris Wilson wrote:
> >Quoting Ben Widawsky (2017-07-07 00:27:01)
> >> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> >> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> >> drivers/gpu/drm/i915/i915_pci.c | 13 +
> >> include/ua
On 06/07/17 11:51, Michel Thierry wrote:
On 7/6/2017 10:59 AM, Chris Wilson wrote:
> If there are no conflicts, then just skip the patch, and really there
> shouldn't be since the writes we care about are ordered and the writes
> we don't, we don't. We will need to move to per-context hwsp i
On Fri, Jun 30, 2017 at 01:19:57PM -0700, Rodrigo Vivi wrote:
> I believe it would be better to create the psr lib with only one
> function at time and on every patch that adds the new function already
> removes that from here and from frontbuffer tracking test as well...
>
> easier to review and
This function now takes the link rate and lane ocunt to be validated
as an argument so that this can be used for validating even the
compliance test link parameters.
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
Cc: Jani Nikula
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 1
Validate the compliance test link parameters when the compliance
test dpcd registers are read. Also validate them in compute_config
before using them since the max values might have been reduced
due to link training fallback.
If either the link rate or lane count is invalid, we still bail
from usi
Hi Daniel,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.12 next-20170707]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Daniel-Vetter/fbcon-Make-fbcon-a-built-time
== Series Details ==
Series: series starting with [RESEND,v2,1/2] drm/i915/dp: Generalize
intel_dp_link_params function to accept arguments to be validated
URL : https://patchwork.freedesktop.org/series/27028/
State : success
== Summary ==
Series 27028v1 Series without cover letter
https://pa
On 07/07/17 14:15, Daniele Ceraolo Spurio wrote:
After a bit of investigation I've found that the issue is not actually
with the positioning of the HWSP but with the fact that we use
status_page.ggtt_offset to point to the lrca offset of the default
context in guc_ads_create instead of using
k
On 7 July 2017 at 18:08, Lionel Landwerlin
wrote:
> From: Matthew Auld
>
> The motivation behind this new interface is expose at runtime the
> creation of new OA configs which can be used as part of the i915 perf
> open interface. This will enable the kernel to learn new configs which
> may be ex
On Friday, July 7, 2017 3:17:22 AM PDT Daniel Vetter wrote:
> On Fri, Mar 17, 2017 at 12:15 PM, Joonas Lahtinen
> wrote:
> > On to, 2017-03-16 at 13:20 +, Chris Wilson wrote:
> >> Currently, the last object in the execlist is the always the batch.
> >> However, when building the batch buffer w
65 matches
Mail list logo
