== Series Details ==
Series: enable virtual HWSP in GVT-g
URL : https://patchwork.freedesktop.org/series/31217/
State : failure
== Summary ==
Series 31217 revision 1 was fully merged or fully failed: no git log
___
Intel-gfx mailing list
Intel-gfx@l
Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.
Signed-off-by: Weinan Li
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_vgpu.c | 5 +
drivers/gpu/drm/i915/i915_vgpu.h | 1 +
d
V2: clean merge confict.
Weinan Li (2):
drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP
drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g
VM
drivers/gpu/drm/i915/gvt/execlist.c| 16 +
drivers/gpu/drm/i915/gvt/gvt.h | 1 +
driver
The engine provides a mirror of the CSB and CSB write pointer in the HWSP.
Read these status from virtual HWSP in VM can reduce CPU utilization while
applications have much more short GPU workloads. Here we update the
corresponding data in virtual HWSP as it in virtual MMIO.
Before read these stat
On 09/28/2017 10:25 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 10:09 +0800, Xiaolin Zhang wrote:
if vgpu active, the page table entry should be initialized after
allocation and then the hypersivor can ping pages succesuffly,
otherwise hypervisor will ping pages failed and the host will pri
== Series Details ==
Series: CNL DVFS
URL : https://patchwork.freedesktop.org/series/31211/
State : failure
== Summary ==
Series 31211v1 CNL DVFS
https://patchwork.freedesktop.org/api/1.0/series/31211/revisions/1/mbox/
Test chamelium:
Subgroup dp-hpd-fast:
skip -
At cdclk initialization at spec they tell us to always use dvfs
or avoid change cdclk if it fails.
Here on pll sequence, spec tells us to only use dvfs "if the
frequency will result in a change to the voltage requirement."
So in order to respect that and avoid necessary interactions with
PCODE we
No functional change expected. Just let's use this enum
when possible and also same standard pll_id name
so we can rework gen9+ port clock later.
Cc: Mika Kahola
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 34 ++
1 file ch
From: Paulo Zanoni
These functions even have their own page in our spec,
so extract them from cnl_set_cdclk().
v2: (By Rodrigo) Fixed inverted logic on error return of
cnl_dvfs_pre_change.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915
From: "Kahola, Mika"
Display Voltage and Frequency Switching (DVFS) is used to adjust the
display voltage to match the display clock frequencies. If voltage is
set too low, it will break functionality. If voltage is set too high,
it will waste power. Voltage level is selected based on CD clock an
From: "Kahola, Mika"
DVFS computation needs cnl_dvfs_{pre,post}_change() functions to be exposed.
These functions will be used when computing DVFS levels in intel_dpll_mgr.c
Cc: Ville Syrjälä
Signed-off-by: Kahola, Mika
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c | 4 +
From: "Kahola, Mika"
Display Voltage and Frequency Switching (DVFS) is used to adjust the
display voltage to match the display clock frequencies. To save power the
voltage is set to minimum when disabling PLL.
The sequence before frequency change is the following and it requests
the power contro
No functional change. Just spliting the function for
better port clock handling later.
Cc: Mika Kahola
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/
When port clock is zero or undefined we base our
calculation on cdclk. So, same function can be used
for port clock == 0 now that we have the same default "2".
Cc: Mika Kahola
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c| 28 +-
No functional change. Just spliting the function for
better port clock handling later.
Cc: Mika Kahola
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/
This is a new attempt of fixing the DVFS on CNL.
After I got the CI nack on the initial attempt I went down
finding and fixing some issues.
But also I decided to rework the existent port clock
functions to make sure we don't duplicate existent code
but also make sure we address HDMI case.
Another
Spec tells us to change the level "if the frequency will result
in a change to the voltage requirement."
When we don't have pll enabled yet we only base our level
calculation on cdclk. So let's do the same when disabling the
pll instead of forcing randomly to zero.
Cc: Mika Kahola
Signed-off-by:
According to spec "If voltage is set too low,
it will break functionality. If voltage is set too high,
it will waste power."
So, let's prefer the waste of power instead of breaking
functionality.
But also the logic of deciding the level on spec
tells "Else, use level 2."
So, default is actually
On Cannonlake the DVFS level selection depends on the
port clock.
So let's re-org in a way that we can easily export without
duplicating any code.
Cc: Mika Kahola
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 21 ++---
drivers/gpu/drm/i915
> -Original Message-
> From: Gerd Hoffmann [mailto:kra...@redhat.com]
> Sent: Friday, September 29, 2017 6:21 PM
> To: Zhang, Tina ; zhen...@linux.intel.com; Wang, Zhi
> A ; Tian, Kevin ; Alex
> Williamson
> Cc: Daniel Vetter ; intel-gfx@lists.freedesktop.org;
> intel-gvt-...@lists.freed
== Series Details ==
Series: drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
URL : https://patchwork.freedesktop.org/series/31204/
State : warning
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
pass -> SKIP
On Fri, 29 Sep 2017 20:07:48 +0200, Patchwork
wrote:
== Series Details ==
Series: drm/i915: Guc code reorg
URL : https://patchwork.freedesktop.org/series/31199/
State : warning
== Summary ==
Series 31199v1 drm/i915: Guc code reorg
https://patchwork.freedesktop.org/api/1.0/series/31199/re
On 09/29/2017 12:10 AM, Michal Wajdeczko wrote:
On Fri, 29 Sep 2017 00:36:56 +0200, Srivatsa, Anusha
wrote:
-Original Message-
From: Sundaresan, Sujaritha
Sent: Thursday, September 21, 2017 11:38 AM
To: intel-gfx@lists.freedesktop.org
Cc: Sundaresan, Sujaritha ;
Wajdeczko, Micha
Quoting Matthew Auld (2017-09-29 17:10:17)
> diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/i915_gem_userptr.c
> index 70ad7489827d..ad5abca1f794 100644
> --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> @@ -405,6 +405,9
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Friday, September 29, 2017 12:10 AM
>To: Sundaresan, Sujaritha ; intel-
>g...@lists.freedesktop.org; Srivatsa, Anusha
>Cc: Wajdeczko, Michal ; Mateo Lozano, Oscar
>; Ceraolo Spurio, Daniele
>
>Subject: Re: [PATCH v4 1/2] drm/i915/guc :
== Series Details ==
Series: drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
URL : https://patchwork.freedesktop.org/series/31204/
State : success
== Summary ==
Series 31204v1 drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
https://patchwork.freedesktop.org/api/1.0/series/31204/r
Per BSpec, 400us is "BDW+ Do not use this setting." Also rename 1600us to
MAX, as the value varies per platform - pre-CNL it means 1600us, and CNL is
3200us.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.
== Series Details ==
Series: huge gtt pages (rev10)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
== Series Details ==
Series: drm/i915: Guc code reorg
URL : https://patchwork.freedesktop.org/series/31199/
State : warning
== Summary ==
Series 31199v1 drm/i915: Guc code reorg
https://patchwork.freedesktop.org/api/1.0/series/31199/revisions/1/mbox/
Test chamelium:
Subgroup dp-edid-r
== Series Details ==
Series: Dist cleanups
URL : https://patchwork.freedesktop.org/series/31177/
State : success
== Summary ==
Test gem_eio:
Subgroup throttle:
dmesg-warn -> PASS (shard-hsw) fdo#102886 +3
Test perf:
Subgroup blocking:
fail
We want to keep GuC specific code in separated files.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc.h | 173 +++
drivers/gpu/drm/i915/intel_uc.h | 146 +
We want to keep GuC functions together. While here move
send registers initialization to early init as this is
one time operation.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/inte
We want to keep each uC specific code in separate files.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_huc.h | 38 ++
drivers/gpu/drm/i915/intel_uc.h | 13 +
2 files ch
We want to keep GuC functions together.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc.c | 21 +
drivers/gpu/drm/i915/intel_guc.h | 4 +---
drivers/gpu/drm/i915/intel_uc.c | 21 ---
We want to keep GuC functions together.
Signatures of the function will be changed in upcoming patch.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 52
drivers/gpu/drm/i9
We want to keep GuC functions together.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 42 --
drivers/gpu/drm/i915/intel_guc.c | 42 ++
We want to keep GuC functions together.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc.c | 16
drivers/gpu/drm/i915/intel_guc.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 16
3 fi
This is a prerequisite to unblock next steps.
No functional changes, only s/dev_priv/i915
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_uc.c| 163 ++-
Other pending series will try to fix current GuC code.
Lets move some functions to dedicated files now to
make place for these changes and preserve history.
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Michal Wajdeczko (9):
drm/i915: Drop unnecessary forward declaration
drm/i
We don't need it here.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 6966349..38ec880 100644
--- a/drivers/gpu/drm/i915/intel_
== Series Details ==
Series: IGT PMU support (rev5)
URL : https://patchwork.freedesktop.org/series/28253/
State : warning
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
== Series Details ==
Series: huge gtt pages (rev10)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Series 25118v10 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/10/mbox/
Test chamelium:
Subgroup hdmi-crc-fast:
Quoting Matthew Auld (2017-09-29 17:10:28)
> v2: mock test page support configurations and add MI_STORE_DWORD test
>
> v3: run all mockable huge page tests on all platforms via the mock_device
>
> v4: add pin_update regression test
> various improvements suggested by Chris
>
> v5: fix issues
Quoting Matthew Auld (2017-09-29 17:10:14)
> Enable transparent-huge-pages through gemfs by mounting with
> huge=within_size.
>
> v2: sprinkle within_size comment
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
It's the interface that exists, not necessarily the one t
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++
drivers/gpu/drm/i91
For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/dr
Before we can fully enable 64K pages, we need to first support a 64K
scratch page if we intend to support the case where we have object sizes
< 2M, since any scratch PTE must also point to a 64K region. Without
this our 64K usage is limited to objects which completely fill the
page-table, and ther
v2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v5: fix issues reported by kbuild
test single sg spanning multiple pa
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Revie
Support inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c |
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
1 file cha
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
v3: move to more suitable home
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuopp
Good to know, mostly for debugging purposes.
v2: some improvements from Chris
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 61 ++---
1 file changed, 57 insertions(+), 4 del
For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
v2: sprinkle within_size comment
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gemfs.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/dri
In preparation for supporting huge gtt pages for the ppgtt, we introduce
page size members for gem objects. We fill in the page sizes by
scanning the sg table.
v2: pass the sg_mask to set_pages
v3: calculate the sg_mask inline with populating the sg_table where
possible, and pass to set_pages al
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.
v2: remove useless 48b PPGTT check
Suggested-by: Zhenyu Wang
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Zhenyu Wang
Reviewed-by: Zhenyu Wang
Reviewed-by: Chris Wilson
---
drivers/gp
For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++
Support inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust maybe_64K at every sg interval
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +
Each backend is now responsible for calling __i915_gem_object_set_pages
upon successfully gathering its backing storage. This eliminates the
inconsistency between the async and sync paths, which stands out even
more when we start throwing around an sg_mask in a later patch.
Suggested-by: Chris Wil
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected op
In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
v2: s/page_size_mask/page_sizes/
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Chris Wilson
Reviewed-by: Joo
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed o
Move the setting/clearing of the vma->pages to a vm operation. Doing so
neatens things up a little, but more importantly gives us a sane place
to also set/clear the vma->pages_sizes, which we introduce later in
preparation for supporting huge-pages.
v2: remove redundant vma->pages check
v3: GEM_B
We are planning to use our own tmpfs mnt in i915 in place of the
shm_mnt, such that we can control the mount options, in particular
huge=, which we require to support huge-gtt-pages. So rather than roll
our own version of __shmem_file_setup, it would be preferred if we could
just give shmem our mnt
The less contentious version of gemfs.
Matthew Auld (21):
mm/shmem: introduce shmem_file_setup_with_mnt
drm/i915: introduce simple gemfs
drm/i915/gemfs: enable THP
drm/i915: introduce page_sizes field to dev_info
drm/i915: push set_pages down to the callers
drm/i915: introduce page_siz
== Series Details ==
Series: series starting with [1/3] drm/i915: Introduce execlist_port_* accessors
URL : https://patchwork.freedesktop.org/series/31175/
State : success
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#10
== Series Details ==
Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock
URL : https://patchwork.freedesktop.org/series/31189/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
09f8cb1a3758fa9868a07b83a3d3db2973d795cc igt/gem_sync:
Signed-off-by: Chris Wilson
---
tests/gem_workarounds.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 074ffc0c..62c10877 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@
Since the introduction of debugfs/i915_drop_caches, we have offered the
ability to wait upon all outstanding batches. This is more efficient and
less error prone (one example is the use of context priorities, we have
to idle at the lowest in order not to jump over any low priority tasks
we want to
Signed-off-by: Chris Wilson
---
tests/gem_workarounds.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 55cab561..86d70369 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -34,6 +34,7
Signed-off-by: Chris Wilson
---
tests/gem_workarounds.c | 50 -
1 file changed, 24 insertions(+), 26 deletions(-)
diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 2a328959..55cab561 100644
--- a/tests/gem_workarounds.c
+++ b/tes
To complete the picture also test a new fd with its implicit default
context. Now we have a test for a longstanding fd, new client, new
context.
Signed-off-by: Chris Wilson
---
tests/gem_workarounds.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/tests/gem_workar
The workarounds are only valid whilst the GPU is active. To be sure we
are reading the registers in the right state, issue the reads from the GPU.
Signed-off-by: Chris Wilson
---
tests/gem_workarounds.c | 137 +++-
1 file changed, 77 insertions(+), 60
Hide the initial setup cost of a new batch by performing it before we
start the clock for measuring the execute-wait latency.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
tests/gem_sync.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/gem_sync.c b/tests/gem_sync.c
On 9/29/2017 3:25 AM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 16:47 -0700, Michel Thierry wrote:
On 28/09/17 15:40, Oscar Mateo wrote:
RING_FORCE_TO_NONPRIV registers do not live in the logical context. They are
simply
global privileged MMIO registers that happen to be powercontext saved
== Series Details ==
Series: lib: Fix igt_sysfs_set_u32 return value
URL : https://patchwork.freedesktop.org/series/31166/
State : warning
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup blocking
== Series Details ==
Series: Remove viral glib dependency
URL : https://patchwork.freedesktop.org/series/31163/
State : failure
== Summary ==
Test gem_eio:
Subgroup in-flight:
pass -> DMESG-WARN (shard-hsw) fdo#102886 +4
Test kms_flip:
Subgroup flip-vs-abs
On Fri, 29 Sep 2017 16:13:54 +0200, Sagar Arun Kamble
wrote:
On 9/29/2017 5:42 PM, Joonas Lahtinen wrote:
+ Michal,
On the principle of code motion first, changes second, I'd like to see
the clean split-up from Michal before touching the files much. That way
git history will be easier t
== Series Details ==
Series: Dist cleanups
URL : https://patchwork.freedesktop.org/series/31177/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
182b1941d8e221f1f5625c53f74b09bef7d8837a benchmarks: Actually build
LIBDRM_INTEL_BENCHMARKS
with latest DRM-Tip
On 9/29/2017 5:30 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
Currently GPU is reset at the end of suspend via i915_gem_sanitize.
On resume, GuC will not be loaded until intel_uc_init_hw happens
during GEM resume flow but action to exit sleep can be s
On 9/29/2017 5:42 PM, Joonas Lahtinen wrote:
+ Michal,
On the principle of code motion first, changes second, I'd like to see
the clean split-up from Michal before touching the files much. That way
git history will be easier to examine.
I think we wanted to get these fixes in prior to restru
== Series Details ==
Series: IGT PMU support (rev5)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
182b1941d8e221f1f5625c53f74b09bef7d8837a benchmarks: Actually build
LIBDRM_INTEL_BENCHMARKS
with lates
On 9/29/2017 7:29 PM, Sagar Arun Kamble wrote:
On 9/29/2017 5:18 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i915_restore_state.
+ Chris
Didn't I just review
On 9/29/2017 5:18 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i915_restore_state.
+ Chris
Didn't I just review this patch elsewhere? Other thread explains that
On 9/29/2017 5:15 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
This patch moves GuC suspend/resume handlers to corresponding GEM handlers
and orders them properly in the runtime and system suspend/resume flows.
v2: Removed documentation of suspend/res
On 9/29/2017 6:46 PM, Joonas Lahtinen wrote:
On Fri, 2017-09-29 at 12:49 +0100, Chris Wilson wrote:
Quoting Joonas Lahtinen (2017-09-29 12:43:48)
On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
These changes are preparation to handle GuC suspend/resume. Prepared
helper i915_gem_r
== Series Details ==
Series: series starting with [1/3] drm/i915: Introduce execlist_port_* accessors
URL : https://patchwork.freedesktop.org/series/31175/
State : success
== Summary ==
Series 31175v1 series starting with [1/3] drm/i915: Introduce execlist_port_*
accessors
https://patchwork.f
On Fri, Sep 29, 2017 at 01:39:33PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Idea is to avoid duplication across multiple users in
> upcoming patches.
>
> v2: Commit message and use a separate library instead of piggy-
> backing to libintel_tools. (Chris Wilson)
>
> Signed-off
== Series Details ==
Series: i915 PMU and engine busy stats (rev14)
URL : https://patchwork.freedesktop.org/series/27488/
State : failure
== Summary ==
Series 27488v14 i915 PMU and engine busy stats
https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/14/mbox/
Test chamelium:
On Fri, 2017-09-29 at 09:19 +0100, Chris Wilson wrote:
> Hide the initial setup cost of a new batch by performing it before we
> start the clock for measuring the execute-wait latency.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source
Chris Wilson writes:
> Quoting Chris Wilson (2017-09-29 11:45:57)
>> We coalesce onto an active port[0], but not onto an active port[1]
>> despite it being the same mechanism. So explain the complications that
>> make skipping the first active port and coalescing onto the second
>> active port in
On Fri, 2017-09-29 at 12:49 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-09-29 12:43:48)
> > On Thu, 2017-09-28 at 12:18 +0530, Sagar Arun Kamble wrote:
> > > These changes are preparation to handle GuC suspend/resume. Prepared
> > > helper i915_gem_runtime_resume to reinitialize susp
On Fri, 2017-09-29 at 11:12 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-09-29 08:29:57)
> > On Thu, 2017-09-28 at 20:39 +0100, Chris Wilson wrote:
> > > When we write to ELSP, it triggers a context preemption at the earliest
> > > arbitration point (3DPRIMITIVE, some PIPECONTROLs, a
On Fri, 2017-09-29 at 10:40 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-09-29 10:23:10)
> > On Tue, 2017-09-26 at 21:13 +0100, Chris Wilson wrote:
> > > Quoting Paulo Zanoni (2017-09-26 20:29:08)
> > > > Stolen memory pointers are dma_addr_t, which means they can be 64 bit
> > > > th
On Fri, 2017-09-29 at 11:59 +0200, Maarten Lankhorst wrote:
> Most of these tests have no reason to look at those members,
> so try other ways of getting the information.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Mika Kahola
> ---
> lib/igt_kms.h | 21
> tests
Quoting Tvrtko Ursulin (2017-09-29 13:39:36)
> From: Tvrtko Ursulin
>
> v2: Update for i915 changes.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> @@ -176,8 +176,8 @@ int gpu_freq_update(struct gpu_freq *gf)
> return EAGAIN;
> }
>
> - gf->curr
Signed-off-by: Petri Latvala
---
docs/Makefile.am | 5 +
1 file changed, 5 insertions(+)
diff --git a/docs/Makefile.am b/docs/Makefile.am
index b68c7745..68cb80a5 100644
--- a/docs/Makefile.am
+++ b/docs/Makefile.am
@@ -1 +1,6 @@
SUBDIRS=reference
+
+EXTRA_DIST = \
+ audio.txt \
+
Signed-off-by: Petri Latvala
---
benchmarks/Makefile.am | 2 ++
benchmarks/wsim/Makefile.am | 31 +++
configure.ac| 1 +
3 files changed, 34 insertions(+)
create mode 100644 benchmarks/wsim/Makefile.am
diff --git a/benchmarks/Makefile.am b/benc
Distribute files that should be, remove files that shouldn't be even
in git.
Notable inclusion: Meson build system files added to dist. With this
series, both a git checkout and tarball distribution build the same
results with either autotools or meson. Meson support looks to be
mature enough to g
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