There seems to be another clock gating issue which the workaround is
described as:
"WA: Set 0xE4F0[1] = 1 to disable Early EOT of thread."
Signed-off-by: Rafael Antognolli
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 4 ins
On Thu, 2017-11-30 at 13:19 +0200, Imre Deak wrote:
> On Thu, Nov 30, 2017 at 09:45:25AM +, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-11-30 09:18:20)
> > > From: Tvrtko Ursulin
> > >
> > > It seems that the DMC likes to transition between the DC states a lot when
> > > there are no
== Series Details ==
Series: series starting with [1/2] drm/i915: Implement WaDisableVFclkgate.
URL : https://patchwork.freedesktop.org/series/34785/
State : success
== Summary ==
Series 34785v1 series starting with [1/2] drm/i915: Implement
WaDisableVFclkgate.
https://patchwork.freedesktop.o
On Thu, 2017-11-30 at 13:19 +0200, Imre Deak wrote:
> > > +#define NEEDS_CSR_GT_PERF_WA(dev_priv) \
> > > + (HAS_CSR(dev_priv) && IS_GEN9(dev_priv) && !
> IS_SKYLAKE(dev_priv))
>
> Nitpick: could be just !IS_SKYLAKE(), but works in the above way too.
> For all other platforms the GT_IRQ doma
== Series Details ==
Series: igt/gem_busy: Replace arbitrary busy batch with indefinite spinbatch
(rev2)
URL : https://patchwork.freedesktop.org/series/34780/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
476c4b462e0453c70ee81664c0227fdddc26cbd0 igt/gem_e
Record the before/after semaphore-wait values around the sleep to try to
reduce the inaccuracy from scheduler delays. Previously, the samples
were taken before submitting the batch and then after synchronising its
completion. The measurement will then be the total that the semaphore
was being sampl
== Series Details ==
Series: igt/perf_pmu: Tighten semaphore-wait measurement
URL : https://patchwork.freedesktop.org/series/34786/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
476c4b462e0453c70ee81664c0227fdddc26cbd0 igt/gem_eio: Increase wakeup delay fo
Hi all,
The following changes tagged drm-intel-testing-2017-12-01:
drm-intel-next-2017-12-01:
- Init clock gate fix (Ville)
- Execlists event handling corrections (Chris, Michel)
- Improvements on GPU Cache invalidation and context switch (Chris)
- More perf OA changes (Lionel)
- More selftests
== Series Details ==
Series: series starting with [1/2] drm/i915: Implement WaDisableVFclkgate.
URL : https://patchwork.freedesktop.org/series/34785/
State : failure
== Summary ==
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS (shard-hsw) fdo#10
== Series Details ==
Series: igt/gem_busy: Replace arbitrary busy batch with indefinite spinbatch
(rev2)
URL : https://patchwork.freedesktop.org/series/34780/
State : failure
== Summary ==
Test pm_rpm:
Subgroup drm-resources-equal:
pass -> SKIP (shard-hsw)
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