[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

== Series Details == Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2) URL : https://patchwork.freedesktop.org/series/35338/ State : success == Summary == Series 35338v2 drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines.

== Series Details == Series: igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines. URL : https://patchwork.freedesktop.org/series/36246/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] debugger: Convert to current intel_register_access_init()

== Series Details == Series: series starting with [1/3] debugger: Convert to current intel_register_access_init() URL : https://patchwork.freedesktop.org/series/36242/ State : failure == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render:

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines.

== Series Details == Series: igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines. URL : https://patchwork.freedesktop.org/series/36246/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9 tools: Cannonlake

[Intel-gfx] ✓ Fi.CI.IGT: success for overlay: Update .gitignore

== Series Details == Series: overlay: Update .gitignore URL : https://patchwork.freedesktop.org/series/36241/ State : success == Summary == Test kms_flip: Subgroup flip-vs-absolute-wf_vblank-interruptible: fail -> PASS (shard-hsw) fdo#100368 fdo#100368

[Intel-gfx] [PATCH i-g-t] igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines.

Fix flip subtest that used plaform names in igt_require() instead of testing if rotation property is supported on given combination of rotation/flips. Suggested-by: Daniel Vetter Cc: Daniel Vetter Signed-off-by: Anusha Srivatsa ---

[Intel-gfx] ✓ Fi.CI.IGT: success for pull in headers for major/minor/makedev funcs (rev2)

== Series Details == Series: pull in headers for major/minor/makedev funcs (rev2) URL : https://patchwork.freedesktop.org/series/9042/ State : success == Summary == Test gem_eio: Subgroup in-flight-contexts: notrun -> INCOMPLETE (shard-snb) fdo#104058 Test

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_kms.c: Unconditionally include poll.h

On 9 January 2018 at 05:11, Petri Latvala wrote: > Commit 98c64b33a793 ("lib/igt_kms: Drop all stale events on first > commit.") added a use of poll() to igt_kms.c, but that file only > includes poll.h when HAVE_UDEV is defined. Move the include outside > the UDEV

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] debugger: Convert to current intel_register_access_init()

== Series Details == Series: series starting with [1/3] debugger: Convert to current intel_register_access_init() URL : https://patchwork.freedesktop.org/series/36242/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9

[Intel-gfx] ✗ Fi.CI.IGT: failure for include inttypes.h for PRI defines (rev2)

== Series Details == Series: include inttypes.h for PRI defines (rev2) URL : https://patchwork.freedesktop.org/series/9041/ State : failure == Summary == Test gem_shrink: Subgroup reclaim: pass -> DMESG-FAIL (shard-hsw) Test kms_frontbuffer_tracking:

[Intel-gfx] ✓ Fi.CI.BAT: success for overlay: Update .gitignore

== Series Details == Series: overlay: Update .gitignore URL : https://patchwork.freedesktop.org/series/36241/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9 tools: Cannonlake port clock programming with latest

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

Regards Shashank On 1/9/2018 11:31 PM, Ville Syrjälä wrote: On Thu, Dec 28, 2017 at 08:32:05PM +0530, Sharma, Shashank wrote: On 12/22/2017 11:58 PM, Ville Syrjala wrote: From: Ville Syrjälä The LG 4k TV I have doesn't deassert HPD when I turn the TV off,

[Intel-gfx] ✓ Fi.CI.BAT: success for pull in headers for major/minor/makedev funcs (rev2)

== Series Details == Series: pull in headers for major/minor/makedev funcs (rev2) URL : https://patchwork.freedesktop.org/series/9042/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9 tools: Cannonlake port clock

[Intel-gfx] [PATCH i-g-t 2/3] debugger: Clean up register access helper in debug_rdata

Clean up the register access helper initialized with intel_register_access_init() by debug_rdata Signed-off-by: Rhys Kidd --- debugger/debug_rdata.c | 1 + 1 file changed, 1 insertion(+) diff --git a/debugger/debug_rdata.c b/debugger/debug_rdata.c index 45084b8e..4db7cbcd

[Intel-gfx] [PATCH i-g-t 1/3] debugger: Convert to current intel_register_access_init()

Fixes: 301ad44c ("lib: Open debugfs files for the given DRM device") Signed-off-by: Rhys Kidd --- debugger/debug_rdata.c | 2 +- debugger/eudb.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/debugger/debug_rdata.c b/debugger/debug_rdata.c index

[Intel-gfx] [PATCH i-g-t 3/3] debugger: No longer rely on compatability define in intel_bufmgr.h

Symbol rename from dri_* to drm_intel_* introduced a number of compatability defines within intel_bufmgr.h. Replace the old function with the new function, consistent with the balance of this file. Signed-off-by: Rhys Kidd --- debugger/eudb.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH i-g-t] overlay: Update .gitignore

Fixes: 865a47ca ("overlay: parse tracepoints from sysfs to figure out fields' location") Signed-off-by: Rhys Kidd --- overlay/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/overlay/.gitignore b/overlay/.gitignore index bf91f08e..9ee5a356 100644 ---

[Intel-gfx] ✓ Fi.CI.BAT: success for include inttypes.h for PRI defines (rev2)

== Series Details == Series: include inttypes.h for PRI defines (rev2) URL : https://patchwork.freedesktop.org/series/9041/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9 tools: Cannonlake port clock programming

[Intel-gfx] [PATCH i-g-t] include inttypes.h for PRI defines

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96620 Signed-off-by: Mike Frysinger --- lib/igt_fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index dcae07dff021..ded639e833f1 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -27,6

[Intel-gfx] [PATCH i-g-t] pull in headers for major/minor/makedev funcs

Use the portable autoconf helper to figure out which header to include for these funcs. Linux C libs are moving to not implicitly include them via sys/types.h anymore, and other OS's have long required you to pull in the right header directly. Bugzilla:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use the engine name directly in the error_state file (rev2)

== Series Details == Series: drm/i915: Use the engine name directly in the error_state file (rev2) URL : https://patchwork.freedesktop.org/series/36215/ State : success == Summary == Test kms_flip: Subgroup flip-vs-absolute-wf_vblank-interruptible: fail -> PASS

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bxt: Enable VBT based BL control for DP (rev4)

== Series Details == Series: drm/i915/bxt: Enable VBT based BL control for DP (rev4) URL : https://patchwork.freedesktop.org/series/25323/ State : failure == Summary == Applying: drm/i915/bxt: Enable VBT based BL control for DP (v2) error: Failed to merge in the changes. Using index info to

[Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP (v2)

Currently, BXT_PP is hardcoded with value '0'. It practically disabled eDP backlight on MRB (BXT) platform. This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP backlight

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the engine name directly in the error_state file (rev2)

== Series Details == Series: drm/i915: Use the engine name directly in the error_state file (rev2) URL : https://patchwork.freedesktop.org/series/36215/ State : success == Summary == Series 36215v2 drm/i915: Use the engine name directly in the error_state file

[Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

Instead of using local string names that we will have to keep maintaining, use the engine->name directly. v2: Better invalid engine_id handling, capture_bo will not be able know the engine_id and end up with -1 (Michal). Suggested-by: Michal Wajdeczko Signed-off-by:

Re: [Intel-gfx] [PATCH 02/27] drm/i915/icl: Add the ICL PCI IDs

On 01/09/2018 05:02 PM, De Marchi, Lucas wrote: On Tue, 2018-01-09 at 16:09 -0800, Oscar Mateo wrote: On 01/09/2018 03:23 PM, Paulo Zanoni wrote: This is the current PCI ID list in our documentation. Let's leave the _gt#_ part out for now since our current documentation is not 100% clear

Re: [Intel-gfx] [PATCH 02/27] drm/i915/icl: Add the ICL PCI IDs

On Tue, 2018-01-09 at 16:09 -0800, Oscar Mateo wrote: > > On 01/09/2018 03:23 PM, Paulo Zanoni wrote: > > This is the current PCI ID list in our documentation. > > > > Let's leave the _gt#_ part out for now since our current documentation > > is not 100% clear and we don't need this info now

Re: [Intel-gfx] [PATCH] drm/i915: add support for specifying DMC firmware override by module param

Hi, This patch could be really helpful Is there any issue with it? It's not merged yet. Regards, Anusha >-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Jani Nikula >Sent: Wednesday, November 22, 2017 8:20 AM >To: Joonas

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

On 09/01/18 13:37, Michel Thierry wrote: On 09/01/18 12:46, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-01-09 20:39:09) On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use

Re: [Intel-gfx] [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

On Tue, Jan 9, 2018 at 10:48 AM, Paulo Zanoni wrote: > Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu: >> By the Spec all CNL skus are GT2. > > This is definitely not my understanding, some of the PCI IDs in our > driver are clearly marked as GT1 on the spec. >

Re: [Intel-gfx] [PATCH 02/27] drm/i915/icl: Add the ICL PCI IDs

On 01/09/2018 03:23 PM, Paulo Zanoni wrote: This is the current PCI ID list in our documentation. Let's leave the _gt#_ part out for now since our current documentation is not 100% clear and we don't need this info now anyway. v2: Use the new ICL_11 naming (Kelvin Gardiner). v3: Latest IDs

Re: [Intel-gfx] [PATCH 01/27] drm/i915/icl: Add initial Icelake definitions.

On 01/09/2018 03:23 PM, Paulo Zanoni wrote: From: Rodrigo Vivi Icelake is a Intel® Processor containing Intel® HD Graphics. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and

[Intel-gfx] [PATCH 27/27] drm/i915/gen11: add support for reading the timestamp frequency

The only thing that differs here is that the crystal clock freq now has four possible values. This patch gets rid of the "Unknown gen, unable to compute..." message at boot for gen11. Reviewed-by: Lionel Landwerlin Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 25/27] drm/i915/icl: Enable RC6 and RPS in Gen11

From: Oscar Mateo AFAICT, once the new interrupt is in place, the rest should behave the same as Gen10. v2: Update ring frequencies (Sagar) Cc: Daniele Ceraolo Spurio Cc: Sagar Arun Kamble Cc: Paulo Zanoni

[Intel-gfx] [PATCH 23/27] drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers

From: Oscar Mateo Both for clarity and so that we can reuse it later on. v2: - local_clock returns a u64 (Tvrtko) - Use the funky BIT(bit) version (Tvrtko) - wait_start not required (Tvrtko) - Use time_after64 (Oscar) Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 20/27] drm/i915/icl: Make use of the SW counter field in the new context descriptor

From: Oscar Mateo The new context descriptor format in Gen11 contains two assignable fields: the SW Context ID (technically 11 bits, but practically limited to 2032 entries due to some being reserved for future use by the GuC) and the SW Counter (6 bits). We don't want to

[Intel-gfx] [PATCH 17/27] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11

From: Oscar Mateo Icelake 11 has one vebox and two vdboxes (0 and 2). Bspec: 21140 v2: Split out in two (Daniele) Cc: Daniele Ceraolo Spurio Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_pci.c | 1 +

[Intel-gfx] [PATCH 21/27] drm/i915/icl: Add reset control register changes

From: Michel Thierry The bits used to reset the different engines/domains have changed in GEN11, this patch maps the reset engine mask bits with the new bits in the reset control register. v2: Use shift-left instead of BIT macro to match the file style (Paulo). v3:

[Intel-gfx] [PATCH 19/27] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection

From: Kelvin Gardiner This patch adds support to detect ICL, slice, subslice and EU fuse settings. Add addresses for ICL 11 slice, subslice and EU fuses registers. These register addresses are the same as previous platforms but the format and / or the meaning of the

[Intel-gfx] [PATCH 24/27] drm/i915/icl: Handle RPS interrupts correctly for Gen11

From: Oscar Mateo Using the new hierarchical interrupt infrastructure. Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Cc: Sagar Arun Kamble Cc: Paulo Zanoni

[Intel-gfx] [PATCH 22/27] drm/i915/icl: Add configuring MOCS in new Icelake engines

From: Tomasz Lis In Icelake, there are more engines on which Memory Object Control States need to be configured. Besides adding Icelake under Skylake config, the patch makes sure MOCS register addresses for the new engines are properly defined. Additional patch might be

[Intel-gfx] [PATCH 26/27] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register

This enables the Mesa driver to advertise support for ARB_timer_query, and thus an OpenGL version higher than 3.2. Based on the CNL patch by Nanley Chery. v2: Rebase. Cc: Anuj Phogat Cc: Nanley Chery Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 18/27] drm/i915/icl: Update subslice define for ICL 11

From: Kelvin Gardiner ICL 11 has a greater number of maximum subslices. This patch updates the subslice max define to reflect this. Bspec: 21139 Reviewed-by: Oscar Mateo Reviewed-by: Daniele Ceraolo Spurio

[Intel-gfx] [PATCH 13/27] drm/i915/icl: Gen11 forcewake support

From: Daniele Ceraolo Spurio The main difference with previous GENs is that starting from Gen11 each VCS and VECS engine has its own power well, which only exist if the related engine exists in the HW. The fallback forcewake request workaround is only needed on

[Intel-gfx] [PATCH 10/27] drm/i915/icl: Enhanced execution list support

From: Thomas Daniel Supports two-element submission using the new enhanced execlist mechanism v2: Rebase. v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio). v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio) Signed-off-by: Thomas Daniel

[Intel-gfx] [PATCH 14/27] drm/i915/icl: Set graphics mode register for gen11

From: kgardine This patch clears a single bit. The bit is 0 by default but expected not to be set. Explicitly clearing the bit in this patch is intended to indicate some thinking has occurred, and that we want this bit cleared and we are not just excepting the default

[Intel-gfx] [PATCH 16/27] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

From: Oscar Mateo In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also, each VDBOX and VEBOX has its own power well, which only exist if the related engine exists in the HW.

[Intel-gfx] [PATCH 15/27] drm/i915/icl: new context descriptor support

From: "Ceraolo Spurio, Daniele" Starting from Gen11 the context descriptor format has been updated in the HW. The hw_id field has been considerably reduced in size and engine class and instance fields have been added. There is a slight name clashing issue

[Intel-gfx] [PATCH 11/27] drm/i915/icl: Gen11 render context size

From: Tvrtko Ursulin The current size may be bigger than the correct one, this needs to be revisited later. v2: Rebase. Acked-by: Ben Widawsky Signed-off-by: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 12/27] drm/i915/icl: Add Indirect Context Offset for Gen11

From: Michel Thierry v2: rebased to intel_lr_indirect_ctx_offset Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko ---

[Intel-gfx] [PATCH 06/27] drm/i915/icl: Prepare for more rings

From: Tvrtko Ursulin Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be

[Intel-gfx] [PATCH 02/27] drm/i915/icl: Add the ICL PCI IDs

This is the current PCI ID list in our documentation. Let's leave the _gt#_ part out for now since our current documentation is not 100% clear and we don't need this info now anyway. v2: Use the new ICL_11 naming (Kelvin Gardiner). v3: Latest IDs as per BSpec (Oscar). v4: Make it compile

[Intel-gfx] [PATCH 03/27] drm/i915/icl: add icelake_init_clock_gating()

For now it does nothing, except for avoiding a MISSING_CASE. v2: Rebase. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 01/27] drm/i915/icl: Add initial Icelake definitions.

From: Rodrigo Vivi Icelake is a Intel® Processor containing Intel® HD Graphics. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the ICL_FEATURES

[Intel-gfx] [PATCH 09/27] drm/i915/icl: Correctly initialize the Gen11 engines

From: Oscar Mateo Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio base definitions for all of them. Bspec: 20944 Bspec: 7021 v2: Set the correct mmio_base in intel_engines_init_mmio; updating the base mmio values any later would cause incorrect reads

[Intel-gfx] [PATCH 04/27] drm/i915/icl: Icelake interrupt register addresses and bits

From: Tvrtko Ursulin MMIO addresses and register definition for the new interrupt registers in Gen11. v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio) v4: Bikeshedding (Paulo). Cc: Ceraolo Spurio,

[Intel-gfx] [PATCH 05/27] drm/i915/icl: Show interrupt registers in debugfs

From: Tvrtko Ursulin v2: Update for POR changes. (Daniele Ceraolo Spurio) Signed-off-by: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Cc: Ceraolo Spurio, Daniele ---

[Intel-gfx] [PATCH 07/27] drm/i915/icl: Interrupt handling

From: Tvrtko Ursulin v2: Rebase. v3: * Remove DPF, it has been removed from SKL+. * Fix -internal rebase wrt. execlists interrupt handling. v4: Rebase. v5: * Updated for POR changes. (Daniele Ceraolo Spurio) * Merged with irq handling fixes by Daniele Ceraolo

[Intel-gfx] [PATCH 08/27] drm/i915/icl: Ringbuffer interrupt handling

From: Tvrtko Ursulin Since it is not possible to mask individual engine instances and they are all permanently unmasked we do not need to do anything for engine interrupt management. v2: Rebase. v3: Remove gen 11 extra check in logical_render_ring_init. v4: Rebase

[Intel-gfx] [PATCH 00/27] ICL basic enabling + GEM

Hello This is the first series of patches for the Icelake platform. Unlike the other series that introduced new platforms, this one is very small and only contains patches for very basic enabling, interrupts and some GEM code. No patches for display or other subsystems yet and GEM is not complete

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use the engine name directly in the error_state file

== Series Details == Series: drm/i915: Use the engine name directly in the error_state file URL : https://patchwork.freedesktop.org/series/36215/ State : failure == Summary == Test gem_tiled_swapping: Subgroup non-threaded: pass -> DMESG-WARN (shard-hsw)

Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/perf_pmu: Exercise busy stats and lite-restore

Quoting Tvrtko Ursulin (2018-01-09 16:16:21) > From: Tvrtko Ursulin > > While developing a fix for an accounting hole in busy stats we realized > lite-restore is a potential edge case which would be interesting to check > is properly handled. > > It is unfortnately

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

On 09/01/18 12:46, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-01-09 20:39:09) On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly. Suggested-by:

Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy

Quoting Tvrtko Ursulin (2018-01-09 16:16:20) > From: Tvrtko Ursulin > > Make sure busyness is correctly reported when PMU is enabled after the > engine is already busy with a single long batch. > > Signed-off-by: Tvrtko Ursulin > --- >

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

Quoting Michal Wajdeczko (2018-01-09 20:39:09) > On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry > wrote: > > > Instead of using local string names that we will have to keep > > maintaining, use the engine->name directly. > > > > Suggested-by: Michal Wajdeczko

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

== Series Details == Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2) URL : https://patchwork.freedesktop.org/series/35338/ State : success == Summary == Series 35338v2 drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set

Re: [Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry wrote: Instead of using local string names that we will have to keep maintaining, use the engine->name directly. Suggested-by: Michal Wajdeczko Signed-off-by: Michel Thierry

Re: [Intel-gfx] [PATCH] drm: i915: Fix audio issue on BXT

Sorry, I've been out. I'm checking on this. -Original Message- From: Pandiyan, Dhinakaran Sent: Thursday, 4 January, 2018 2:00 PM To: Singh, Gaurav K Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo ; subransu.s.pru...@intel.com;

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the engine name directly in the error_state file

== Series Details == Series: drm/i915: Use the engine name directly in the error_state file URL : https://patchwork.freedesktop.org/series/36215/ State : success == Summary == Series 36215v1 drm/i915: Use the engine name directly in the error_state file

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Don't allow HDCP on PORT E/F

== Series Details == Series: drm/i915: Don't allow HDCP on PORT E/F URL : https://patchwork.freedesktop.org/series/36214/ State : failure == Summary == Applying: drm/i915: Don't allow HDCP on PORT E/F Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_hdmi.c

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Only disable HDCP when it's active

== Series Details == Series: drm/i915: Only disable HDCP when it's active URL : https://patchwork.freedesktop.org/series/36212/ State : failure == Summary == Applying: drm/i915: Only disable HDCP when it's active Using index info to reconstruct a base tree... M

[Intel-gfx] [PATCH] drm/i915: Use the engine name directly in the error_state file

Instead of using local string names that we will have to keep maintaining, use the engine->name directly. Suggested-by: Michal Wajdeczko Signed-off-by: Michel Thierry Cc: Michal Wajdeczko ---

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy

== Series Details == Series: series starting with [1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy URL : https://patchwork.freedesktop.org/series/36201/ State : warning == Summary == Test gem_eio: Subgroup in-flight: pass ->

[Intel-gfx] [PATCH] drm/i915: Don't allow HDCP on PORT E/F

Port E doesn't have HDCP support, and Port F is disabled. Don't setup the hdcp shim on those. Reviewed-by: Daniel Vetter Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/intel_hdmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH] drm/i915: Only disable HDCP when it's active

Instead of always trying to disable HDCP. Only run hdcp_disable when the state is not UNDESIRED. This will catch cases where it's enabled and also cases where enable failed and the state is left in DESIRED mode. Note that things won't blow up if disable is attempted while already disabled, it's

Re: [Intel-gfx] [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu: > By the Spec all CNL skus are GT2. This is definitely not my understanding, some of the PCI IDs in our driver are clearly marked as GT1 on the spec. But since we don't use this GTX number anywhere for CNL for the Kernel driver, can't we

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

On Thu, Dec 28, 2017 at 08:32:05PM +0530, Sharma, Shashank wrote: > > > On 12/22/2017 11:58 PM, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The LG 4k TV I have doesn't deassert HPD when I turn the TV off, but > > when I turn it back on it will pulse the

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy

== Series Details == Series: series starting with [1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy URL : https://patchwork.freedesktop.org/series/36201/ State : success == Summary == IGT patchset tested on top of latest successful build

[Intel-gfx] [PATCH i-g-t 1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy

From: Tvrtko Ursulin Make sure busyness is correctly reported when PMU is enabled after the engine is already busy with a single long batch. Signed-off-by: Tvrtko Ursulin --- tests/perf_pmu.c | 42 ++

[Intel-gfx] [PATCH i-g-t 2/2] tests/perf_pmu: Exercise busy stats and lite-restore

From: Tvrtko Ursulin While developing a fix for an accounting hole in busy stats we realized lite-restore is a potential edge case which would be interesting to check is properly handled. It is unfortnately quite timing sensitive to hit lite-restore in the fashion test

[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/igt_kms: Fix build warning in igt_display_drop_events

== Series Details == Series: lib/igt_kms: Fix build warning in igt_display_drop_events URL : https://patchwork.freedesktop.org/series/36190/ State : failure == Summary == Test kms_cursor_crc: Subgroup cursor-64x64-suspend: pass -> SKIP (shard-hsw)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

== Series Details == Series: drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks URL : https://patchwork.freedesktop.org/series/36188/ State : failure == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: fail ->

Re: [Intel-gfx] [-next PATCH 3/4] treewide: Use DEVICE_ATTR_RO

On Thu, Dec 21, 2017 at 11:34:10AM +0200, Sakari Ailus wrote: > Hi Joe, > > On Tue, Dec 19, 2017 at 10:15:08AM -0800, Joe Perches wrote: > > diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm.c > > b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm.c > > index

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

On Tue, Jan 09, 2018 at 01:33:48PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks > URL : https://patchwork.freedesktop.org/series/36188/ > State : success Thanks for the reviews, pushed to -dinq. > > == Summary == >

Re: [Intel-gfx] [RFC v2 2/8] drm/ioctl: Remove trailing whitespace

Hi Noralf, Thank you for the patch. On Thursday, 4 January 2018 00:21:04 EET Noralf Trønnes wrote: > Remove a couple of trailing spaces. > > Signed-off-by: Noralf Trønnes Reviewed-by: Laurent Pinchart > --- >

Re: [Intel-gfx] [RFC v2 3/8] drm: Export some ioctl functions

Hi Noralf, Thank you for the patch. On Thursday, 4 January 2018 00:21:05 EET Noralf Trønnes wrote: > Export the following functions so in-kernel users can allocate > dumb buffers: > - drm_file_alloc > - drm_file_free > - drm_prime_handle_to_fd_ioctl > - drm_mode_addfb2 > -

Re: [Intel-gfx] [PATCH v2] drm/i915/pmu: Only enumerate available counters in sysfs

Quoting Tvrtko Ursulin (2018-01-09 12:20:05) > From: Tvrtko Ursulin > > Switch over to dynamically creating device attributes, which are in turn > used by the perf core to expose available counters in sysfs. > > This way we do not expose counters which are not avaiable

Re: [Intel-gfx] [PATCH] drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

On Tue, 2018-01-09 at 14:20 +0200, Imre Deak wrote: > The power domain masks are 64 bit wide, so we need BIT_ULL() when > setting bits in them, these ones were missed during converting from 32 > to 64 bit masks. All 3 enums are <32 atm, so this didn't cause a real > problem. > > Fixes:

Re: [Intel-gfx] [PATCH i-g-t 6/6] i-g-t: kms_plane_scaling: test for multi pipe with scaling

Op 13-12-17 om 10:50 schreef Vidya Srinivas: > From: Jyoti Yadav > > Patch adds subtest to display primary and overlay planes on two > connected pipes and runs scaling test on both pipes > > Signed-off-by: Jyoti Yadav > Signed-off-by: Mahesh

[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_kms: Fix build warning in igt_display_drop_events

== Series Details == Series: lib/igt_kms: Fix build warning in igt_display_drop_events URL : https://patchwork.freedesktop.org/series/36190/ State : success == Summary == IGT patchset tested on top of latest successful build 834321a5d76a16783000441a02d7e79e72be9cc9 tools: Cannonlake port

Re: [Intel-gfx] [PATCH] drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

Quoting Imre Deak (2018-01-09 12:20:40) > The power domain masks are 64 bit wide, so we need BIT_ULL() when > setting bits in them, these ones were missed during converting from 32 > to 64 bit masks. All 3 enums are <32 atm, so this didn't cause a real > problem. > > Fixes: d8fc70b7367b

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

== Series Details == Series: drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks URL : https://patchwork.freedesktop.org/series/36188/ State : success == Summary == Series 36188v1 drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Only enumerate available counters in sysfs (rev2)

== Series Details == Series: drm/i915/pmu: Only enumerate available counters in sysfs (rev2) URL : https://patchwork.freedesktop.org/series/35689/ State : success == Summary == Series 35689v2 drm/i915/pmu: Only enumerate available counters in sysfs

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

== Series Details == Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2) URL : https://patchwork.freedesktop.org/series/35338/ State : failure == Summary == Warning: bzip CI_DRM_3609/shard-glkb6/results32.json.bz2 wasn't in correct JSON format Test

[Intel-gfx] [PATCH i-g-t] lib/igt_kms: Fix build warning in igt_display_drop_events

From: Tvrtko Ursulin Check read(2) return for robustness and to silence gcc. Signed-off-by: Tvrtko Ursulin Cc: Maarten Lankhorst -- Compile tested only. --- lib/igt_kms.c | 5 +++-- 1 file changed, 3

Re: [Intel-gfx] [PATCH i-g-t 4/6] i-g-t kms_plane_scaling: test scaling with tiling rotation and pixel formats

Op 14-12-17 om 11:55 schreef Daniel Vetter: > Just a quick comment at the bottom. > > On Wed, Dec 13, 2017 at 03:20:50PM +0530, Vidya Srinivas wrote: >> @@ -312,23 +480,40 @@ static void test_plane_scaling(data_t *d, enum pipe >> pipe) >> igt_require_f(valid_tests, "no valid crtc/connector

Re: [Intel-gfx] [PATCH i-g-t 2/6] i-g-t: lib: Add plane pixel format support

Op 09-01-18 om 13:10 schreef Maarten Lankhorst: > Op 13-12-17 om 10:50 schreef Vidya Srinivas: >> From: Mahesh Kumar >> >> This patch adds the following: >> - Query supported pixel formats from kernel for a given >> plane. >> - Get number of supported pixel formats for a

Re: [Intel-gfx] [PATCH i-g-t 3/6] i-g-t: lib/igt_kms: Run kms_plane for all supported pixel formats

Op 13-12-17 om 10:50 schreef Vidya Srinivas: > From: Mahesh Kumar > > This patch adds a subtest related to pixel format testing. The test > create framebuffer with all supported pixel formats for primary and > sprite planes which can be drawn using cairo and commits the

[Intel-gfx] [PATCH] drm/i915: Fix using BIT_ULL() vs. BIT() for power domain masks

The power domain masks are 64 bit wide, so we need BIT_ULL() when setting bits in them, these ones were missed during converting from 32 to 64 bit masks. All 3 enums are <32 atm, so this didn't cause a real problem. Fixes: d8fc70b7367b ("drm/i915: Make power domain masks 64 bit long") Cc: Joonas

[Intel-gfx] [PATCH v2] drm/i915/pmu: Only enumerate available counters in sysfs

From: Tvrtko Ursulin Switch over to dynamically creating device attributes, which are in turn used by the perf core to expose available counters in sysfs. This way we do not expose counters which are not avaiable on the current platform, and are so more consistent

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