== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets
around wedging
URL : https://patchwork.freedesktop.org/series/39312/
State : warning
== Summary ==
Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-pri-in
On Fri, Mar 02, 2018 at 11:20:42PM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
> > > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 28, 2018 at 12:
Ville Syrjälä writes:
> On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
>> On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
>> > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
>> > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
>> > > > On Tue, Feb 27,
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets
around wedging
URL : https://patchwork.freedesktop.org/series/39312/
State : success
== Summary ==
Series 39312v1 series starting with [CI,1/3] drm/i915: Suspend submission
tasklets around wedgin
On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
> > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
> > > > On Tue, 2018-02-27 at 23:34 +0200, Ville S
Although this state (execlists->active and engine->irq_posted) itself is
not protected by the engine->timeline spinlock, it does conveniently
ensure that irqs are disabled. We can use this to protect our
manipulation of the state and so ensure that the next IRQ to arrive sees
consistent state and (
After staring hard at sequences like
[ 28.199013] systemd-1 2..s. 26062228us :
execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
[ 28.199095] systemd-1 2..s. 26062229us :
execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x,
active=0x1
[ 2
During reset/wedging, we have to clean up the requests on the timeline
and flush the pending interrupt state. Currently, we are abusing the irq
disabling of the timeline spinlock to protect the irq state in
conjunction to the engine's timeline requests, but this is accidental
and conflates the spin
== Series Details ==
Series: series starting with [1/3] drm/i915/error: remove unused
gen8_engine_sync_index
URL : https://patchwork.freedesktop.org/series/39305/
State : warning
== Summary ==
Possible new issues:
Test gem_pwrite:
Subgroup big-gtt-forwards:
pass
On Wed, Feb 28, 2018 at 3:34 PM, Sean Paul wrote:
>
> Hi Dave,
> Here's this weeks pull, relatively small when you pull out the trivial fixes.
>
> drm-misc-next-2018-02-28:
> drm-misc-next for 4.17:
>
> UAPI Changes:
> Fix drm_color_ctm matrix docs to match usage and change the type to
> __u64 m
On Fri, 02 Mar 2018 20:19:29 +0100, Daniele Ceraolo Spurio
wrote:
some of the static functions used from capture() have the "i915_"
prefix while other don't; most of them take i915 as a parameter, but one
of them derives it internally from error->i915. Let's be consistent by
avoiding prefix f
== Series Details ==
Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before
drm_atomic_helper_check_modeset
URL : https://patchwork.freedesktop.org/series/38678/
State : failure
== Summary ==
Applying: drm/i915: Check for I915_MODE_FLAG_INHERITED before
drm_atomic_helper_check_modeset
e
== Series Details ==
Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling
URL : https://patchwork.freedesktop.org/series/39293/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
incomplete -> PASS
== Series Details ==
Series: series starting with [1/3] drm/i915/error: remove unused
gen8_engine_sync_index
URL : https://patchwork.freedesktop.org/series/39305/
State : success
== Summary ==
Series 39305v1 series starting with [1/3] drm/i915/error: remove unused
gen8_engine_sync_index
http
Leftover from Gen8 ringbuffer support removal
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_gpu_error.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
some of the static functions used from capture() have the "i915_"
prefix while other don't; most of them take i915 as a parameter, but one
of them derives it internally from error->i915. Let's be consistent by
avoiding prefix for static functions and always providing i915 as a
parameter.
Signed-of
error->device_info.has_guc, which we check in capture_uc_state, is set
in capture_gen_state, so the latter needs to be performed first.
Reported-by: Vinay Belgaumkar
Cc: Vinay Belgaumkar
Cc: Michal Wajdeczko
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915
Quoting Ville Syrjälä (2018-03-02 17:09:29)
> On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote:
> > A couple of bugs inside the hang injector, the worst being that the
> > presumed_offset of the reloc didn't match the batch; so if the reloc was
> > skipped (as the presumed_offset matche
== Series Details ==
Series: drm/i915/dp: clean up leftover references to CHV HBR2 support
URL : https://patchwork.freedesktop.org/series/39285/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-
On 03/02/2018 10:10 AM, Rodrigo Vivi wrote:
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actual use of these registers and bits?
S
== Series Details ==
Series: drm/i915: Clean up the port pipe select bits (rev2)
URL : https://patchwork.freedesktop.org/series/39259/
State : failure
== Summary ==
Series 39259v2 drm/i915: Clean up the port pipe select bits
https://patchwork.freedesktop.org/api/1.0/series/39259/revisions/2/mb
On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:
(GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
+
+/**
+ * intel_wopcm_init_early() - Early initialization of the WOPCM.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * Setup the size of WOPCM which will be used by later on WOPCM
partitioning.
+ */
+
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actual use of these registers and bits?
thanks,
Rodrigo.
>
> Signed-off-by: Clint T
== Series Details ==
Series: series starting with [1/5] drm/i915: Stop engines around GPU reset
preparations
URL : https://patchwork.freedesktop.org/series/39284/
State : failure
== Summary ==
Possible new issues:
Test drv_selftest:
Subgroup live_hangcheck:
pass
From: Ville Syrjälä
Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.
v2: Return PIPE_A for cpt/ppt when the port isn't selected by
any transcoder
From: "Xiong, James"
Previously a bucket size was used for buffer allocation whether
bo_reuse is false or true. This patch returns NULL in function
drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the
original requested size is used instead.
Signed-off-by: Xiong, James
---
intel/inte
From: "Xiong, James"
With gem_reuse enabled, when a buffer size is different than
the sizes of buckets, it is aligned to the next bucket's size,
which means about 25% more memory than the requested is allocated
in the worst senario. For example:
Orignal sizeActual
32KB+1Byte 40KB
.
.
.
== Series Details ==
Series: Documentation patch for batchbuffer submission (rev2)
URL : https://patchwork.freedesktop.org/series/38433/
State : warning
== Summary ==
Possible new issues:
Test gem_pwrite:
Subgroup big-gtt-forwards:
pass -> SKIP (shard-
On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote:
> A couple of bugs inside the hang injector, the worst being that the
> presumed_offset of the reloc didn't match the batch; so if the reloc was
> skipped (as the presumed_offset matched the reloc offset), the batch
> wasn't updated and
== Series Details ==
Series: series starting with [1/3] drm: Don't create properties without names
(rev2)
URL : https://patchwork.freedesktop.org/series/39277/
State : success
== Summary ==
Known issues:
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-bottom-edge:
== Series Details ==
Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling
URL : https://patchwork.freedesktop.org/series/39293/
State : success
== Summary ==
Series 39293v1 series starting with [1/6] drm/i915/icl: Ringbuffer interrupt
handling
https://patchwork.freed
On Fri, Feb 23, 2018 at 08:14:53PM +0530, Ramalingam C wrote:
>
>
> On Friday 23 February 2018 07:16 PM, Ville Syrjälä wrote:
> > On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
> >> This is really making it cleaner.
> >>
> >> Reviewed-by: Ramalingam C
> >>
> >>
> >>
> >> On Friday
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on
auth failure
URL : https://patchwork.freedesktop.org/series/39280/
State : failure
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-03-02 15:50:53)
>> Chris Wilson writes:
>>
>> > During reset/wedging, we have to clean up the requests on the timeline
>> > and flush the pending interrupt state. Currently, we are abusing the irq
>> > disabling of the timeline spinlock to prot
From: Thomas Daniel
Enhanced Execlists is an upgraded version of execlists which supports
up to 8 ports. The lrcs to be submitted are written to a submit queue
(the ExecLists Submission Queue - ELSQ), which is then loaded on the
HW. When writing to the ELSP register, the lrcs are written cyclical
From: Daniele Ceraolo Spurio
Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.
There is a slight name clashing issue because the field that we call
hw_id is act
From: Daniele Ceraolo Spurio
The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entr
From: Michel Thierry
v2: rebased to intel_lr_indirect_ctx_offset
v3: rebase, move define to intel_lrc_reg.h
BSpec: 11740
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 4
driv
From: Tvrtko Ursulin
On Gen11 interrupt masks need to be clear to allow C6 entry.
We keep them all enabled knowing that we generate extra
interrupts.
v2: Rebase.
v3: Remove gen 11 extra check in logical_render_ring_init.
v4: Rebase fixes.
v5: Rebase/refactor.
v6: Rebase.
v7: Rebase.
v8: Update c
From: Oscar Mateo
Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio
base definitions for all of them.
Bspec: 20944
Bspec: 7021
v2: Set the correct mmio_base in intel_engines_init_mmio; updating the
base mmio values any later would cause incorrect reads in
i915_gem_sanitize (M
A couple of bugs inside the hang injector, the worst being that the
presumed_offset of the reloc didn't match the batch; so if the reloc was
skipped (as the presumed_offset matched the reloc offset), the batch
wasn't updated and so we may not have generated a hanging batch at all!
Secondly, the MI_
On Thu, 01 Mar 2018, Jani Nikula wrote:
> Does checkpatch support disabling checks or do you have to filter them
> out from the output?
Turns out it does. There's an --ignore option. For starters, I sent a
patch [1] to show the warning types in the output, so we can more
accurately discuss the ig
Quoting Mika Kuoppala (2018-03-02 15:50:53)
> Chris Wilson writes:
>
> > During reset/wedging, we have to clean up the requests on the timeline
> > and flush the pending interrupt state. Currently, we are abusing the irq
> > disabling of the timeline spinlock to protect the irq state in
> > conju
== Series Details ==
Series: drm/i915/dp: clean up leftover references to CHV HBR2 support
URL : https://patchwork.freedesktop.org/series/39285/
State : success
== Summary ==
Series 39285v1 drm/i915/dp: clean up leftover references to CHV HBR2 support
https://patchwork.freedesktop.org/api/1.0/
Chris Wilson writes:
> During GEM sanitization, we reset the GPU so that it's always in a
> default state whenever we take over or return the GPU back to the BIOS.
> We call the GPU reset directly, so that we don't get caught up in trying
> to handle GEM or KMS state that is isn't ready at that t
Chris Wilson writes:
> During reset/wedging, we have to clean up the requests on the timeline
> and flush the pending interrupt state. Currently, we are abusing the irq
> disabling of the timeline spinlock to protect the irq state in
> conjunction to the engine's timeline requests, but this is ac
On Thu, Mar 01, 2018 at 10:48:25PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset (rev2)
> URL : https://patchwork.freedesktop.org/series/39129/
> State : success
>
> == Summary ==
Thanks for the review, pushed it to -
== Series Details ==
Series: drm/i915/execlists: Move irq state manipulation inside irq disabled
region
URL : https://patchwork.freedesktop.org/series/39276/
State : success
== Summary ==
Known issues:
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-left-edge:
== Series Details ==
Series: series starting with [1/5] drm/i915: Stop engines around GPU reset
preparations
URL : https://patchwork.freedesktop.org/series/39284/
State : success
== Summary ==
Series 39284v1 series starting with [1/5] drm/i915: Stop engines around GPU
reset preparations
http
Quoting Chris Wilson (2018-03-02 12:14:07)
> Quoting Ville Syrjälä (2018-03-02 12:12:26)
> > On Fri, Mar 02, 2018 at 12:01:42PM +, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-03-02 11:59:18)
> > > > From: Ville Syrjälä
> > > >
> > > > Use the new "COLOR_ENCODING" plane property to i
Quoting dom.const...@free.fr (2018-02-06 18:57:05)
>
>
> > Quoting dom.const...@free.fr (2018-02-02 18:37:12)
> > > Hello,
> > >
> > > For my HTPC setup, I'm using the option "CustomEDID".
> > > With this option, output attaching and destroying events leads to
> > > crashes.
> > >
> > > The fol
== Series Details ==
Series: Documentation patch for batchbuffer submission (rev2)
URL : https://patchwork.freedesktop.org/series/38433/
State : success
== Summary ==
Series 38433v2 Documentation patch for batchbuffer submission
https://patchwork.freedesktop.org/api/1.0/series/38433/revisions/
No such thing as CHV HBR2. Clean up after commit ed63baaf849e
("drm/i915: Avoid TP3 on CHV").
Reported-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drive
== Series Details ==
Series: series starting with [1/3] drm: Don't create properties without names
(rev2)
URL : https://patchwork.freedesktop.org/series/39277/
State : success
== Summary ==
Series 39277v2 series starting with [1/3] drm: Don't create properties without
names
https://patchwork
Chris Wilson writes:
> After starting hard at sequences like
Perhaps you meant staring, but starting is fine too.
-Mika
>
> [ 28.199013] systemd-1 2..s. 26062228us :
> execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
> [ 28.199095] systemd-1 2..s. 26062229us
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on
auth failure
URL : https://patchwork.freedesktop.org/series/39280/
State : success
== Summary ==
Series 39280v1 series starting with [v2,1/2] drm/i915/huc: Mark firmware as
failed on auth fail
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/39272/
State : failure
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Te
During reset/wedging, we have to clean up the requests on the timeline
and flush the pending interrupt state. Currently, we are abusing the irq
disabling of the timeline spinlock to protect the irq state in
conjunction to the engine's timeline requests, but this is accidental
and conflates the spin
After starting hard at sequences like
[ 28.199013] systemd-1 2..s. 26062228us :
execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
[ 28.199095] systemd-1 2..s. 26062229us :
execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x,
active=0x1
[
During GEM sanitization, we reset the GPU so that it's always in a
default state whenever we take over or return the GPU back to the BIOS.
We call the GPU reset directly, so that we don't get caught up in trying
to handle GEM or KMS state that is isn't ready at that time, but now we
have a couple o
Although this state (execlists->active and engine->irq_posted) itself is
not protected by the engine->timeline spinlock, it does conveniently
ensure that irqs are disabled. We can use this to protect our
manipulation of the state and so ensure that the next IRQ to arrive sees
consistent state and (
As we make preparations to reset the GPU state, we assume that the GPU
is hung and will not advance. Make this assumption more explicit by
setting the STOP_RING bit on the engines as part of our early reset
preparations.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michel Thierry
Reviewed-
On Thu, 01 Mar 2018, Marc Herbert wrote:
> Hi Jani,
>
>> *cringe* at adding a parameter to workaround issues.
>
> I understand that *each* parameter has the potential to *multiply* the total
> number of configurations and that the resulting combinatorial explosion is
> absolutely not scalable and
== Series Details ==
Series: series starting with [1/3] drm: Don't create properties without names
URL : https://patchwork.freedesktop.org/series/39277/
State : success
== Summary ==
Series 39277v1 series starting with [1/3] drm: Don't create properties without
names
https://patchwork.freedes
From: Kevin Rogovin
This patch provides additional overview documentation to the
i915 kernel driver GEM. In addition, it presents already written
documentation to i915.rst as well.
Signed-off-by: Kevin Rogovin
---
Documentation/gpu/i915.rst | 194 +++--
From: Kevin Rogovin
v2:
More documentation: intel_ringbuffer, sequence number.
Expose to i915.rst existing documentation
Call out GEM_EXECBUFFER as deprecated.
Place code detailed documentation in source files.
Call out INTEL_EXEC_RENDER.
Reorder text to make it more readable.
From: Ville Syrjälä
Reject requests to add properties/enums with an overly long name.
Previously we would have just silently truncated the string and exposed
it userspace.
v2: drm_property_create() returns a pointer
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_property.c | 6 ++
1
== Series Details ==
Series: series starting with [1/3] drm: Don't create properties without names
URL : https://patchwork.freedesktop.org/series/39277/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Don't create properties without names
Okay!
Commit: drm: Check proper
Quoting Chris Wilson (2018-03-02 13:12:46)
> Although this state (execlists->active and engine->irq_posted) itself is
> not protected by the engine->timeline spinlock, it does conveniently
> ensure that irqs are disabled. We can use this to protect our
> manipulation of the state and so ensure that
== Series Details ==
Series: drm/i915/execlists: Move irq state manipulation inside irq disabled
region
URL : https://patchwork.freedesktop.org/series/39276/
State : success
== Summary ==
Series 39276v1 drm/i915/execlists: Move irq state manipulation inside irq
disabled region
https://patchw
Chris Wilson writes:
> Although this state (execlists->active and engine->irq_posted) itself is
> not protected by the engine->timeline spinlock, it does conveniently
> ensure that irqs are disabled. We can use this to protect our
> manipulation of the state and so ensure that the next IRQ to arr
Chris Wilson writes:
> After starting hard at sequences like
>
> [ 28.199013] systemd-1 2..s. 26062228us :
> execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
> [ 28.199095] systemd-1 2..s. 26062229us :
> execlists_submission_tasklet: rcs0 csb[1]: status=0x000
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
inde
If we fail to authenticate HuC firmware, we should change
its load status to FAIL. While around, print HUC_STATUS
on firmware verification failure.
v2: keep the variables sorted by length (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Reviewed-by: Chris Wilson
--
== Series Details ==
Series: series starting with [1/2] drm/i915: Stop engines around GPU reset
preparations
URL : https://patchwork.freedesktop.org/series/39270/
State : failure
== Summary ==
Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb
== Series Details ==
Series: drm/i915: Stop engines around GPU reset preparations
URL : https://patchwork.freedesktop.org/series/39261/
State : failure
== Summary ==
Possible new issues:
Test drv_selftest:
Subgroup live_hangcheck:
pass -> INCOMPLETE (shard-a
From: Ville Syrjälä
BT.2020 specifies two YCbCr<->RGB conversion formulas. The more
traditional non-constant luminance and a more complicate constant
luminance one. Add an enum value for the constant luminance variant
as well in case someone has hardware supporting it.
v2: Reduce the enum name t
From: Ville Syrjälä
Reject requests to add properties/enums with an overly long name.
Previously we would have just silently truncated the string and exposed
it userspace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_property.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/
From: Ville Syrjälä
Creating a property that doesn't have a name makes no sense to me. Don't
allow it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_property.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_
== Series Details ==
Series: drm/i915: Kill the remaining CHV HBR2 leftovers
URL : https://patchwork.freedesktop.org/series/39260/
State : success
== Summary ==
Possible new issues:
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
skip -> PASS (sh
Although this state (execlists->active and engine->irq_posted) itself is
not protected by the engine->timeline spinlock, it does conveniently
ensure that irqs are disabled. We can use this to protect our
manipulation of the state and so ensure that the next IRQ to arrive sees
consistent state and (
== Series Details ==
Series: drm/i915: Clean up the port pipe select bits
URL : https://patchwork.freedesktop.org/series/39259/
State : failure
== Summary ==
Series 39259v1 drm/i915: Clean up the port pipe select bits
https://patchwork.freedesktop.org/api/1.0/series/39259/revisions/1/mbox/
--
On Wed, Feb 14, 2018 at 09:23:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Here's a refresh of Jyri's COLOR_ENCODING and COLOR_RANGE properties,
> and the i915 implementation I did on top. I tossed in a few core
> updates as well: plane state dump, and the BT.2020 constant luminance
Quoting Chris Wilson (2018-03-02 11:33:24)
> After starting hard at sequences like
>
> [ 28.199013] systemd-1 2..s. 26062228us :
> execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
> [ 28.199095] systemd-1 2..s. 26062229us :
> execlists_submission_tasklet: rcs0
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/39272/
State : success
== Summary ==
Series 39272v1 series starting with [v2,1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
https://pa
On Wed, Feb 14, 2018 at 09:23:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> BT.2020 specifies two YCbCr<->RGB conversion formulas. The more
> traditional non-constant luminance and a more complicate one constant
> luminance one. Add an enum value for the constant luminance variant
>
Quoting Mika Kuoppala (2018-03-02 12:17:19)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2018-03-02 11:50:32)
> >> Chris Wilson writes:
> >> > +static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
> >> > + unsigned engine_mask,
> >> > +
On Fri, Mar 02, 2018 at 09:56:26AM +, Tvrtko Ursulin wrote:
>
> On 02/03/2018 09:29, Imre Deak wrote:
> > On Wed, Feb 28, 2018 at 03:35:06PM +, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Some tests (the ones which call igt_setup_runtime_pm and
> > > igt_pm_enable_audio_
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-03-02 11:50:32)
>> Chris Wilson writes:
>> > +static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
>> > + unsigned engine_mask,
>> > + u32 mode)
>> > +{
>> > + struc
Quoting Ville Syrjälä (2018-03-02 12:12:26)
> On Fri, Mar 02, 2018 at 12:01:42PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-03-02 11:59:18)
> > > From: Ville Syrjälä
> > >
> > > Use the new "COLOR_ENCODING" plane property to implement the
> > > XV_COLORSPACE port attribute for spr
On Fri, Mar 02, 2018 at 12:01:42PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-03-02 11:59:18)
> > From: Ville Syrjälä
> >
> > Use the new "COLOR_ENCODING" plane property to implement the
> > XV_COLORSPACE port attribute for sprite Xv adaptors.
> >
> > v2: assert(colorspace < ARRAY_
== Series Details ==
Series: series starting with [1/2] drm/i915: Stop engines around GPU reset
preparations
URL : https://patchwork.freedesktop.org/series/39270/
State : success
== Summary ==
Series 39270v1 series starting with [1/2] drm/i915: Stop engines around GPU
reset preparations
http
On 28/02/2018 17:54, Patchwork wrote:
== Series Details ==
Series: drm/i915: Wedged engine mask makes more sense in hex
URL : https://patchwork.freedesktop.org/series/39147/
State : success
== Summary ==
Series 39147v1 drm/i915: Wedged engine mask makes more sense in hex
https://patchwork.f
Quoting Ville Syrjala (2018-03-02 11:59:18)
> From: Ville Syrjälä
>
> Use the new "COLOR_ENCODING" plane property to implement the
> XV_COLORSPACE port attribute for sprite Xv adaptors.
>
> v2: assert(colorspace < ARRAY_SIZE) (Chris)
>
> Cc: Jyri Sarha
> Cc: Chris Wilson
> Signed-off-by: Vill
Quoting Mika Kuoppala (2018-03-02 11:50:32)
> Chris Wilson writes:
> > +static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
> > + unsigned engine_mask,
> > + u32 mode)
> > +{
> > + struct intel_engine_cs *engine;
> >
From: Ville Syrjälä
Use the new "COLOR_ENCODING" plane property to implement the
XV_COLORSPACE port attribute for sprite Xv adaptors.
v2: assert(colorspace < ARRAY_SIZE) (Chris)
Cc: Jyri Sarha
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
src/sna/sna.h | 1 +
src/sna/sna_
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases better.
Handle failures to off-line a CPU by immediately skipping the test, and
failures to on-line a CPU by
Chris Wilson writes:
> As we make preparations to reset the GPU state, we assume that the GPU
> is hung and will not advance. Make this assumption more explicit by
> setting the STOP_RING bit on the engines as part of our early reset
> preparations.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuo
On Fri, Mar 02, 2018 at 04:39:38PM +0530, Sagar Arun Kamble wrote:
>
>
> On 2/27/2018 6:22 PM, Michał Winiarski wrote:
> > We plan to decouple log runtime (mapping + relay) from verbosity control.
> > Let's tidy the code now to reduce the churn in the following patches.
> >
> > Signed-off-by: Mi
We want to use higher level 'uc' functions as the main entry points to
the GuC/HuC code to hide some details and keep code layered.
While here, move call to disable_guc_interrupts after sending suspend
action to the GuC to allow it work also with CTB as comm mechanism.
v2: update commit msg (Saga
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