[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw

== Series Details == Series: series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw URL : https://patchwork.freedesktop.org/series/40704/ State : success == Summary == Known issues: Test kms_flip: Subgroup blocking-wf_vblank: pass

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit

== Series Details == Series: series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit URL : https://patchwork.freedesktop.org/series/40702/ State : success == Summary == Known issues: Test kms_flip: Subgroup flip-vs-expired-vblank: pass -> FAIL

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add NV12 support (rev4)

> -Original Message- > From: Jani Nikula [mailto:jani.nik...@linux.intel.com] > Sent: Monday, March 26, 2018 7:19 PM > To: Patchwork ; Srinivas, Vidya > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] ✗

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw

== Series Details == Series: series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw URL : https://patchwork.freedesktop.org/series/40704/ State : success == Summary == Series 40704v1 series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw

== Series Details == Series: series starting with [v2,1/4] drm/i915: Enable edp psr error interrupts on hsw URL : https://patchwork.freedesktop.org/series/40704/ State : warning == Summary == $ dim checkpatch origin/drm-tip e0e155ae5044 drm/i915: Enable edp psr error interrupts on hsw -:109:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit

== Series Details == Series: series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit URL : https://patchwork.freedesktop.org/series/40702/ State : success == Summary == Series 40702v1 series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit

== Series Details == Series: series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit URL : https://patchwork.freedesktop.org/series/40702/ State : warning == Summary == $ dim checkpatch origin/drm-tip 38150dd0cc54 drm: Add DP PSR2 sink enable bit b58a3e8a7618 drm: Add DP last

[Intel-gfx] [PATCH v2 3/4] drm/i915/psr: Control PSR interrupts via debugfs

Interrupts other than the one for AUX errors are required only for debug, so unmask them via debugfs when the user requests debug. User can make such a request with echo 1 > /dri/0/i915_edp_psr_debug v2: Unroll loops (Ville) Avoid resetting error mask bits. Cc: Rodrigo Vivi

[Intel-gfx] [PATCH v2 4/4] drm/i915/psr: Timestamps for PSR entry and exit interrupts.

Timestamps are useful for IGT tests that trigger PSR exit and/or wait for PSR entry. v2: Removed seqlock (Ville) Removed erroneous warning in irq loop (Chris) Cc: Ville Syrjälä Cc: Rodrigo Vivi Cc: Chris Wilson

[Intel-gfx] [PATCH v2 2/4] drm/i915: Enable edp psr error interrupts on bdw+

From: Ville Syrjälä Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr on any transcoder in theory, though the we don't currenty enable PSR except on the EDP transcoder. v2: From DK * Rebased on drm-tip v3: Switched author to Ville based on IRC

[Intel-gfx] [PATCH v2 1/4] drm/i915: Enable edp psr error interrupts on hsw

From: Daniel Vetter The definitions for the error register should be valid on bdw/skl too, but there we haven't even enabled DE_MISC handling yet. Somewhat confusing the the moved register offset on bdw is only for the _CTL/_AUX register, and that _IIR/IMR stayed where

[Intel-gfx] [PATCH v2 03/10] drm/i915/psr: Nuke aux frame sync

eDP spec states that aux frame is required to do PSR2 selective update but i915 don't fully implement it. It sends the aux frame sync messages but the value is always zero as the GTC is not enabled in driver. Through tests was findout that pannels can do selective update when the y-coordinate is

[Intel-gfx] [PATCH v2 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed

In the 2 eDP1.4a pannels tested set or not set bit have no effect but is better set it and comply with specification. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH v2 04/10] drm/i915/psr: Tie PSR2 support to Y coordinate requirement

Although i915 don't implement aux sync frame through tests was findout that pannels can do selective update when the y-coordinate is also included in SDP, that is why it is required to run PSR2 in i915. So moving to only one place the sink requirements that the actual driver needs to enable PSR2.

[Intel-gfx] [PATCH v2 07/10] drm/i915/psr: Use PSR2 macro for PSR2

Cosmetic change. Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 3 ++- drivers/gpu/drm/i915/intel_psr.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH v2 08/10] drm/i915/psr: Cache sink synchronization latency

This value do not change overtime so better cache it than fetch it every PSR enable. Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 1 +

[Intel-gfx] [PATCH v2 06/10] drm/i915/psr: Do not override PSR2 sink support

Sink can support our PSR2 requirements but userspace can request a resolution that PSR2 hardware do not support, in this case it was overwritten the PSR2 sink support. Adding another flag here, this way if requested resolution changed to a value that PSR2 hardware can handle, PSR2 can be enabled.

[Intel-gfx] [PATCH v2 01/10] drm: Add DP PSR2 sink enable bit

To comply with eDP1.4a this bit should be set when enabling PSR2. Signed-off-by: José Roberto de Souza Reviewed-by: Rodrigo Vivi --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h

[Intel-gfx] [PATCH v2 02/10] drm: Add DP last received PSR SDP VSC register and bits

This is a register to help debug what is in the last SDP VSC packet revived by sink. Signed-off-by: José Roberto de Souza Reviewed-by: Rodrigo Vivi --- include/drm/drm_dp_helper.h | 9 + 1 file changed, 9 insertions(+) diff --git

[Intel-gfx] [PATCH v2 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source

From: "Souza, Jose" For Geminilake and Cannonlake+ the Y-coordinate support must be enabled in PSR2_CTL too. Spec: 7713 and 7720 Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v2 10/10] drm/i915/debugfs: Print sink PSR status

IGT tests could be improved with sink status, knowing for sure that hardware have activate or exit PSR. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza ---

Re: [Intel-gfx] [PATCH 03/12] drm/i915/psr: Nuke aux frame sync

On Fri, 2018-03-23 at 19:16 -0700, Pandiyan, Dhinakaran wrote: > On Fri, 2018-03-23 at 23:49 +, Souza, Jose wrote: > > On Fri, 2018-03-23 at 15:14 -0700, Pandiyan, Dhinakaran wrote: > > > On Thu, 2018-03-22 at 15:57 -0700, Rodrigo Vivi wrote: > > > > On Thu, Mar 22, 2018 at 02:48:39PM -0700,

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

Quoting Chris Wilson (2018-03-26 21:08:33) > Quoting Patchwork (2018-03-26 17:53:44) > > Test gem_userptr_blits: > > Subgroup coherency-unsync: > > pass -> INCOMPLETE (shard-hsw) > > Forgot that obj->userptr.mn may not exist. > > > Subgroup dmabuf-sync: > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Support for Guc responses and requests (rev3)

== Series Details == Series: drm/i915/guc: Support for Guc responses and requests (rev3) URL : https://patchwork.freedesktop.org/series/28393/ State : failure == Summary == Possible new issues: Test gem_eio: Subgroup execbuf: pass -> INCOMPLETE (shard-apl)

Re: [Intel-gfx] [PATCH i-g-t] lib/gpgpu_fill: Adding missing configuration parameters for gpgpu_fill function

+ igt-dev On 21/03/18 07:23, Katarzyna Dec wrote: During debugging gpgpu_fill test on various platforms, I found out few things that can affect newer gens: this is slightly confusing, as you start with saying that you've found something but then below you start with what you've changed. I'd

Re: [Intel-gfx] [PATCH 15/23] drm: Stop updating plane->crtc/fb/old_fb on atomic drivers

On Mon, Mar 26, 2018 at 10:52:58PM +0200, Daniel Vetter wrote: > On Thu, Mar 22, 2018 at 05:23:05PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Stop playing around with plane->crtc/fb/old_fb with atomic > > drivers. Make life a lot simpler when we

Re: [Intel-gfx] [PATCH 15/23] drm: Stop updating plane->crtc/fb/old_fb on atomic drivers

On Thu, Mar 22, 2018 at 05:23:05PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Stop playing around with plane->crtc/fb/old_fb with atomic > drivers. Make life a lot simpler when we don't have to do the > magic old_fb vs. fb dance around plane updates.

Re: [Intel-gfx] [PATCH 06/23] drm: Adjust whitespace for legibility

On Thu, Mar 22, 2018 at 05:22:56PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Add a bit of whitespace here and there to make the code look a bit > more structured. > > Signed-off-by: Ville Syrjälä Too lazy to grow a real

Re: [Intel-gfx] [PATCH 05/23] drm: Add local 'plane' variable for primary/cursor planes

On Thu, Mar 22, 2018 at 05:22:55PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the code a bit more readable by storing the plane pointer in a > local variable rather than having to do crtc->{primary,cursor} all the > time. > > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Allow user control over preempt timeout on the important context

Quoting Chris Wilson (2018-03-26 20:52:06) > Quoting Tvrtko Ursulin (2018-03-26 18:09:29) > > > > On 26/03/2018 12:50, Chris Wilson wrote: > > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.h > > > b/drivers/gpu/drm/i915/i915_gem_context.h > > > index 7854262ddfd9..74d4cadd729e 100644 > >

Re: [Intel-gfx] [PATCH 02/23] drm/atomic-helper: Make drm_atomic_helper_disable_all() update the plane->fb pointers

On Thu, Mar 22, 2018 at 05:22:52PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > drm_atomic_helper_shutdown() needs to release the reference held by > plane->fb, so we want to use drm_atomic_clean_old_fb() in > drm_atomic_helper_disable_all(). However

Re: [Intel-gfx] [PATCH 04/23] drm/atomic-helper: WARN if legacy plane fb pointers are bogus when committing duplicated state

On Thu, Mar 22, 2018 at 05:22:54PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > drm_atomic_helper_commit_duplicated_state() should only be called > resume/reset/load_detect paths where plane->old_fb should always be > NULL and plane->fb should be equal to

Re: [Intel-gfx] [PATCH 03/23] drm: Clear crtc->primary->crtc when disabling the crtc via setcrtc()

On Thu, Mar 22, 2018 at 05:22:53PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Keep the primary->crtc in sync with the state->crtc (also with > primary->fb and state->fb) when disabling the crtc (and thus also > the primary) via setcrtc(). > >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Support for Guc responses and requests (rev3)

== Series Details == Series: drm/i915/guc: Support for Guc responses and requests (rev3) URL : https://patchwork.freedesktop.org/series/28393/ State : success == Summary == Series 28393v3 drm/i915/guc: Support for Guc responses and requests

Re: [Intel-gfx] [PATCH 02/23] drm/atomic-helper: Make drm_atomic_helper_disable_all() update the plane->fb pointers

On Thu, Mar 22, 2018 at 05:22:52PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > drm_atomic_helper_shutdown() needs to release the reference held by > plane->fb, so we want to use drm_atomic_clean_old_fb() in > drm_atomic_helper_disable_all(). However

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Support for Guc responses and requests (rev3)

== Series Details == Series: drm/i915/guc: Support for Guc responses and requests (rev3) URL : https://patchwork.freedesktop.org/series/28393/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/guc: Add documentation for MMIO based communication Okay! Commit:

Re: [Intel-gfx] [PATCH 09/11] drm/i915/perf: allowing opening the perf stream without sampling

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > We want to allow a user to configure the OA hardware so that > MI_RECORD_PERF_COUNT is functional but without having to deal with the > OA buffer. > > This is an interesting optimization we can apply on Gen7.5

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

Quoting Patchwork (2018-03-26 17:53:44) > Test gem_userptr_blits: > Subgroup coherency-unsync: > pass -> INCOMPLETE (shard-hsw) Forgot that obj->userptr.mn may not exist. > Subgroup dmabuf-sync: > pass -> DMESG-WARN (shard-hsw) But

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reword warning for missing cases (rev2)

== Series Details == Series: drm/i915: Reword warning for missing cases (rev2) URL : https://patchwork.freedesktop.org/series/39821/ State : success == Summary == Possible new issues: Test kms_rotation_crc: Subgroup cursor-rotation-180: fail -> PASS

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Allow user control over preempt timeout on the important context

Quoting Tvrtko Ursulin (2018-03-26 18:09:29) > > On 26/03/2018 12:50, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.h > > b/drivers/gpu/drm/i915/i915_gem_context.h > > index 7854262ddfd9..74d4cadd729e 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_context.h > > +++

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

== Series Details == Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3) URL : https://patchwork.freedesktop.org/series/40503/ State : success == Summary == Possible new issues: Test kms_rotation_crc: Subgroup

[Intel-gfx] [PATCH v5 07/12] drm/i915/guc: Use better name for helper wait function

In next patch we will introduce another way of waiting for the response that will use RECV buffer. To avoid misleading names, rename old wait function to reflect the fact that it is based on descriptor update. v2: fix comment style (Michal) v3: use more specific name (Michel) Signed-off-by:

[Intel-gfx] [PATCH v5 11/12] drm/i915/guc: Trace messages from CT while in debug

During debug we may want to investigate all communication from the Guc. Add proper tracing macros in debug config. v2: convert remaining DRM_DEBUG into new CT_DEBUG (Michal) v3: use dedicated Kconfig (Daniele) v4: checkpatch Signed-off-by: Michal Wajdeczko Cc:

[Intel-gfx] [PATCH v5 09/12] drm/i915/guc: Prepare to process incoming requests from CT

Requests are read from CT in the irq handler, but actual processing will be done in the work thread. Processing of specific actions will be added in the upcoming patches. v2: don't use GEM_BUG_ON (Chris) don't kmalloc too large buffer (Michal) v3: rebased v4: don't name it 'dispatch' (Michel)

[Intel-gfx] [PATCH v5 06/12] drm/i915/guc: Prepare to handle messages from CT RECV buffer

GuC can respond to our commands not only by updating SEND buffer descriptor, but can also send a response message over RECV buffer. Guc can also send unsolicited request messages over RECV buffer. Let's start reading those messages and make placeholders for actual response/request handlers. v2:

[Intel-gfx] [PATCH v5 03/12] drm/i915/guc: Prepare send() function to accept bigger response

This is a preparation step for the upcoming patches. We already can return some small data decoded from the command status, but we will need more in the future. v2: add explicit response buf size v3: squash with helper patch Signed-off-by: Michal Wajdeczko Cc: Oscar

[Intel-gfx] [PATCH v5 04/12] drm/i915/guc: Implement response handling in send_mmio()

We're using data encoded in the status MMIO as return value from send function, but GuC may also write more data in remaining MMIO regs. Let's copy content of these registers to the buffer provided by caller. v2: new line (Michel) v3: updated commit message Signed-off-by: Michal Wajdeczko

[Intel-gfx] [PATCH v5 12/12] HAX: Enable GuC for CI

Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 ---

[Intel-gfx] [PATCH v5 10/12] drm/i915/guc: Handle default action received over CT

When running on platform with CTB based GuC communication enabled, GuC to Host event data will be delivered as CT request message. However, content of the data[1] of this CT message follows format of the scratch register used in MMIO based communication, so some code reuse is still possible.

[Intel-gfx] [PATCH v5 08/12] drm/i915/guc: Implement response handling in send_ct()

Instead of returning small data in response status dword, GuC may append longer data as response message payload. If caller provides response buffer, we will copy received data and use number of received data dwords as new success return value. We will WARN if response from GuC does not match

[Intel-gfx] [PATCH v5 05/12] drm/i915/guc: Make event handler a virtual function

On platforms with CTB based GuC communications, we will handle GuC events in a different way. Let's make event handler a virtual function to allow easy switch between those variants. Credits-to: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc:

[Intel-gfx] [PATCH v5 00/12] drm/i915/guc: Support for Guc responses and requests

With this series we will be able to receive more data from the Guc. New Guc firmwares will be required to actually use that feature. v4: respin series after 1/2 year break v5: updated after review comments Michal Wajdeczko (12): drm/i915/guc: Add documentation for MMIO based communication

[Intel-gfx] [PATCH v5 01/12] drm/i915/guc: Add documentation for MMIO based communication

As we are going to extend our use of MMIO based communication, try to explain its mechanics and update corresponding definitions. v2: fix checkpatch MACRO_ARG_REUSE Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Sagar

[Intel-gfx] [PATCH v5 02/12] drm/i915/guc: Add support for data reporting in GuC responses

GuC may return additional data in the response message. Format and meaning of this data is action specific. We will use this non-negative data as a new success return value. Currently used actions don't return data that way yet. v2: fix prohibited space after '~' (Michel) update commit

Re: [Intel-gfx] [PATCH 08/11] drm/i915/perf: add more debug message on open perf open & configs

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > This will make it easier to spot issues related to config > creation/usage. > > Signed-off-by: Lionel Landwerlin s/open perf open/perf open/ ? Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH] drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

On Mon, Mar 26, 2018 at 05:28:58PM +0100, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2018-03-26 16:59:20) > > > > On 26/03/2018 15:59, Chris Wilson wrote: > > > We've always been blatantly ignoring mmu_notifier.h: > > > > > > * Invalidation of multiple concurrent ranges may be > > > *

Re: [Intel-gfx] [PATCH 07/11] drm/i915/perf: pass stream as argument to oa enable vfunc

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > This will allow use to program the hardware based on the stream's > properties in a later commit. I couldn't see where we need this? Regardless, operating on the stream itself makes more sense to me. > >

Re: [Intel-gfx] [PATCH 01/11] drm/i915/perf: pass stream to enable metric set vfuncs

On 26 March 2018 at 20:21, Matthew Auld wrote: > On 26 March 2018 at 10:08, Lionel Landwerlin > wrote: >> We want to use some of the properties of the perf stream to program >> the hardware in a later commit. >> >> Signed-off-by:

Re: [Intel-gfx] [PATCH 02/11] drm/i915/perf: check the value of PROP_SAMPLE_OA uapi parameter

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > We've been a bit loose about this opening parameter. We should only > add the flag for writing OA reports when the value of this parameter > is != 0. > > Signed-off-by: Lionel Landwerlin

Re: [Intel-gfx] [PATCH 01/11] drm/i915/perf: pass stream to enable metric set vfuncs

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > We want to use some of the properties of the perf stream to program > the hardware in a later commit. > > Signed-off-by: Lionel Landwerlin > --- > drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reword warning for missing cases (rev2)

== Series Details == Series: drm/i915: Reword warning for missing cases (rev2) URL : https://patchwork.freedesktop.org/series/39821/ State : success == Summary == Series 39821v2 drm/i915: Reword warning for missing cases https://patchwork.freedesktop.org/api/1.0/series/39821/revisions/2/mbox/

Re: [Intel-gfx] [PATCH] drm/scdc-helper: Convert errors into debug messages

On Sat, Mar 24, 2018 at 08:35:43AM +0530, Sharma, Shashank wrote: > Reviewed-by: Shashank Sharma Thanks. Pushed to drm-misc-next. > > Regards > Shashank > On 3/23/2018 11:55 PM, Ville Syrjala wrote: > > From: Ville Syrjälä > > > >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reword warning for missing cases (rev2)

== Series Details == Series: drm/i915: Reword warning for missing cases (rev2) URL : https://patchwork.freedesktop.org/series/39821/ State : warning == Summary == $ dim checkpatch origin/drm-tip 82628817d5f1 drm/i915: Reword warning for missing cases -:41: CHECK:MACRO_ARG_REUSE: Macro

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/scdc-helper: Convert errors into debug messages

On Fri, Mar 23, 2018 at 11:53:47PM -, Patchwork wrote: > == Series Details == > > Series: drm/scdc-helper: Convert errors into debug messages > URL : https://patchwork.freedesktop.org/series/40591/ > State : failure > > == Summary == > > Possible new issues: > > Test

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

== Series Details == Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3) URL : https://patchwork.freedesktop.org/series/40503/ State : success == Summary == Series 40503v3 series starting with [v4,1/2] drm/i915/cnl: Implement

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

== Series Details == Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3) URL : https://patchwork.freedesktop.org/series/40503/ State : warning == Summary == $ dim checkpatch origin/drm-tip 530daf66ff2f drm/i915/cnl: Implement

Re: [Intel-gfx] [PATCH 11/11] drm/i915: Allow user control over preempt timeout on the important context

On 26/03/2018 12:50, Chris Wilson wrote: EGL_NV_realtime_priority? Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 22 ++ drivers/gpu/drm/i915/i915_gem_context.h | 13 + drivers/gpu/drm/i915/i915_request.c

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 26/03/2018 17:12, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 26/03/2018 17:12, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

== Series Details == Series: drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore URL : https://patchwork.freedesktop.org/series/40676/ State : failure == Summary == Possible new issues: Test drv_module_reload: Subgroup basic-no-display: pass ->

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Mon, 26 Mar 2018 17:35:00 +0200, Jani Nikula wrote: On Mon, 26 Mar 2018, Michał Winiarski wrote: On Fri, Mar 23, 2018 at 02:47:23PM +, Michal Wajdeczko wrote: Instead of returning small data in response status dword, GuC may

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Mon, 26 Mar 2018 17:29:32 +0200, Michał Winiarski wrote: On Fri, Mar 23, 2018 at 02:47:23PM +, Michal Wajdeczko wrote: Instead of returning small data in response status dword, GuC may append longer data as response message payload. If caller provides

Re: [Intel-gfx] [PATCH] drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

Quoting Tvrtko Ursulin (2018-03-26 16:59:20) > > On 26/03/2018 15:59, Chris Wilson wrote: > > We've always been blatantly ignoring mmu_notifier.h: > > > > * Invalidation of multiple concurrent ranges may be > > * optionally permitted by the driver. Either way the > > * establishment of

[Intel-gfx] [PATCH v4 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a MMIO read into L3Bank range will return 0

[Intel-gfx] [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will be returned. However, that means each

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/perf: enable perf support on ICL (rev2)

== Series Details == Series: drm/i915/perf: enable perf support on ICL (rev2) URL : https://patchwork.freedesktop.org/series/39689/ State : warning == Summary == Possible new issues: Test kms_cursor_legacy: Subgroup short-flip-before-cursor-toggle: pass ->

Re: [Intel-gfx] [PATCH] drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

On 26/03/2018 15:59, Chris Wilson wrote: We've always been blatantly ignoring mmu_notifier.h: * Invalidation of multiple concurrent ranges may be * optionally permitted by the driver. Either way the * establishment of sptes is forbidden in the range passed to *

[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5)

== Series Details == Series: drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5) URL : https://patchwork.freedesktop.org/series/40478/ State : success == Summary == Known issues: Test kms_flip: Subgroup 2x-dpms-vs-vblank-race: fail -> PASS

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Mon, 26 Mar 2018, Michał Winiarski wrote: > On Fri, Mar 23, 2018 at 02:47:23PM +, Michal Wajdeczko wrote: >> Instead of returning small data in response status dword, >> GuC may append longer data as response message payload. >> If caller provides response

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

== Series Details == Series: drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore URL : https://patchwork.freedesktop.org/series/40676/ State : success == Summary == Series 40676v1 drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Fri, Mar 23, 2018 at 02:47:23PM +, Michal Wajdeczko wrote: > Instead of returning small data in response status dword, > GuC may append longer data as response message payload. > If caller provides response buffer, we will copy received > data and use number of received data dwords as new

[Intel-gfx] [PATCH] drm/i915/userptr: Wrap mmu_notifier inside its own rw_semaphore

We've always been blatantly ignoring mmu_notifier.h: * Invalidation of multiple concurrent ranges may be * optionally permitted by the driver. Either way the * establishment of sptes is forbidden in the range passed to * invalidate_range_begin/end for the whole duration of the *

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling

== Series Details == Series: series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling URL : https://patchwork.freedesktop.org/series/40665/ State : failure == Summary == Possible new issues: Test gem_ctx_param: Subgroup

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Interface to get GFX shmem usage stats per process

On Thu, 22 Mar 2018, Patchwork wrote: > == Series Details == > > Series: drm/i915: Interface to get GFX shmem usage stats per process > URL : https://patchwork.freedesktop.org/series/40464/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: enable perf support on ICL (rev2)

== Series Details == Series: drm/i915/perf: enable perf support on ICL (rev2) URL : https://patchwork.freedesktop.org/series/39689/ State : success == Summary == Series 39689v2 drm/i915/perf: enable perf support on ICL https://patchwork.freedesktop.org/api/1.0/series/39689/revisions/2/mbox/

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: enable perf support on ICL (rev2)

== Series Details == Series: drm/i915/perf: enable perf support on ICL (rev2) URL : https://patchwork.freedesktop.org/series/39689/ State : warning == Summary == $ dim checkpatch origin/drm-tip 778ddd601367 drm/i915/icl: read timestamp frequency information -:19: WARNING:LONG_LINE: line over

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add NV12 support (rev4)

On Mon, 26 Mar 2018, Patchwork wrote: > == Series Details == > > Series: Add NV12 support (rev4) > URL : https://patchwork.freedesktop.org/series/39670/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 0503b1db737a drm/i915/skl+: rename

[Intel-gfx] [PATCH v2 3/3] drm/i915/perf: use IS_GEN() instead an or condition

Make the code a bit more concise. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index

[Intel-gfx] [PATCH v2 0/3] drm/i915/perf: enable perf support on ICL

Hi, Adding a patch to the previous series to read the timestamp frequency on ICL which is required for the perf support. I'm sure I saw this patch written by somebody before but I can't find it back :( Please manifest yourself if you did write that patch, it should be attributed to its rightful

[Intel-gfx] [PATCH v2 1/3] drm/i915/icl: read timestamp frequency information

We're missing this value which is needed for i915/perf support. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_reg.h | 6 drivers/gpu/drm/i915/intel_device_info.c | 48 2 files changed, 43

[Intel-gfx] [PATCH v2 2/3] drm/i915/perf: enable perf support on ICL

No significant changes from either context offsets, nor report formats, nor register whitelist. v2: Also drop slice/unslice clock ratio changes (Matt) Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld ---

Re: [Intel-gfx] [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER

On Fri, 23 Mar 2018, Paulo Zanoni wrote: > Protect the macro parameters with parens in order to avoid priority > issues on macro evaluation when the macro argument is not a single > operand. > > This is not a problem today, but it could be in the future. I found > this

Re: [Intel-gfx] [PATCH 10/11] drm/i915/perf: limit OA buffer size to minimum when unread

On 26/03/18 10:08, Lionel Landwerlin wrote: The way our hardware is designed doesn't seem to let us use the MI_RECORD_PERF_COUNT command without setting up a circular buffer. In the case where the user didn't request OA reports to be available through the i915 perf stream, we can set the OA

Re: [Intel-gfx] [PATCH 04/11] drm/i915/perf: do not warn when OA buffer is already allocated

On 26/03/18 13:00, Matthew Auld wrote: On 26 March 2018 at 10:08, Lionel Landwerlin wrote: If 2 processes race to open the perf stream, it's possible that one of them will see that OA buffer has already been allocated, while a previous process is still finishing

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5)

== Series Details == Series: drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5) URL : https://patchwork.freedesktop.org/series/40478/ State : success == Summary == Series 40478v5 drm: Eliminate plane->fb/crtc usage for atomic drivers

Re: [Intel-gfx] [igt-dev] [CI i-g-t] tests/perf_pmu: Avoid RT thread for accuracy test

On 26/03/2018 12:17, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-03-26 11:57:58) * No self-adjust - instead just report the achieved cycle and let the parent check against it. Sniff, I was rather proud of our achievement. I had it in mind as a template for future autocalibration

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5)

== Series Details == Series: drm: Eliminate plane->fb/crtc usage for atomic drivers (rev5) URL : https://patchwork.freedesktop.org/series/40478/ State : warning == Summary == $ dim checkpatch origin/drm-tip eec2e4920fa9 Revert "drm/atomic-helper: Fix leak in disable_all" 885b9185b11c

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling

== Series Details == Series: series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling URL : https://patchwork.freedesktop.org/series/40665/ State : success == Summary == Series 40665v1 series starting with [01/11] drm/i915/execlists: Avoid

[Intel-gfx] [PATCH v3 13/23] drm/zte: Stop consulting plane->crtc

From: Ville Syrjälä We want to get rid of plane->crtc on atomic drivers. Stop looking at it. v2: Use old_state->crtc (Maarten) v3: s/fb/crtc/ in commit message to actually match the patch (Shawn) Cc: Shawn Guo Cc: Maarten Lankhorst

Re: [Intel-gfx] [PATCH 06/11] drm/i915: rename PPGTT/GGTT fields OA registers

On 26 March 2018 at 10:08, Lionel Landwerlin wrote: > We had a generic field name used across 2 registers but it feels like > it's clearer we make it obvious what register this field belongs to. > > Signed-off-by: Lionel Landwerlin

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