Re: [Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Avoid RT thread for accuracy test

2018-04-03 Thread Chris Wilson
Quoting Tvrtko Ursulin (2018-04-03 13:38:25) > From: Tvrtko Ursulin > > Realtime scheduling interferes with execlists submission (tasklet) so try > to simplify the PWM loop in a few ways: > > * Drop RT. > * Longer batches for smaller systematic error. > * More truthful test duration calculati

[Intel-gfx] ✓ Fi.CI.BAT: success for Add NV12 support (rev7)

2018-04-03 Thread Patchwork
== Series Details == Series: Add NV12 support (rev7) URL : https://patchwork.freedesktop.org/series/39670/ State : success == Summary == Series 39670v7 Add NV12 support https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/7/mbox/ fi-bdw-5557u total:285 pass:264 dwarn:0 dfa

[Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Avoid RT thread for accuracy test

2018-04-03 Thread Tvrtko Ursulin
From: Tvrtko Ursulin Realtime scheduling interferes with execlists submission (tasklet) so try to simplify the PWM loop in a few ways: * Drop RT. * Longer batches for smaller systematic error. * More truthful test duration calculation. * Less clock queries. * No self-adjust - instead just r

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add NV12 support (rev7)

2018-04-03 Thread Patchwork
== Series Details == Series: Add NV12 support (rev7) URL : https://patchwork.freedesktop.org/series/39670/ State : warning == Summary == $ dim checkpatch origin/drm-tip 028f935bfc8a drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values c37c92d65c7c drm/i915/skl+: refactor WM calculation

[Intel-gfx] ✗ Fi.CI.BAT: failure for Documentation patch for batchbuffer submission (rev4)

2018-04-03 Thread Patchwork
== Series Details == Series: Documentation patch for batchbuffer submission (rev4) URL : https://patchwork.freedesktop.org/series/38433/ State : failure == Summary == Applying: i915.rst: Narration overview on GEM + minor reorder to improve narration error: Failed to merge in the changes. Usin

Re: [Intel-gfx] [PATCH v4 3/5] i915.rst: add link to documentation in i915_gem_execbuffer.c

2018-04-03 Thread Joonas Lahtinen
Quoting kevin.rogo...@intel.com (2018-04-03 13:52:25) > From: Kevin Rogovin > > Add the documentation of "DOC: User command execution" of > i915_gem_execbuffer.c into a new section in i915.rst. > > Signed-off-by: Kevin Rogovin Reviewed-by: Joonas Lahtinen Regards, Joonas

Re: [Intel-gfx] [PATCH v4 2/5] i915: add a text about what happens at bottom of stack in processing a batchbuffer

2018-04-03 Thread Joonas Lahtinen
Quoting kevin.rogo...@intel.com (2018-04-03 13:52:24) > From: Kevin Rogovin > > Now that "DOC: User command execution" of i915_gem_execbuffer.c is included > in the i915.rst, it is benecifial (for new developers) to read what happens > at the bottom of the driver stack (in terms of bytes written

Re: [Intel-gfx] [PATCH v2 1/2] trace: Default to using trace_global_clock if sched_clock is unstable

2018-04-03 Thread Chris Wilson
Quoting Steven Rostedt (2018-04-02 16:17:36) > On Fri, 30 Mar 2018 16:01:31 +0100 > Chris Wilson wrote: > > > Across suspend, we may see a very large drift in timestamps if the sched > > clock is unstable, prompting the global trace's ringbuffer code to warn > > and suggest switching to the globa

Re: [Intel-gfx] [PATCH v4 1/5] i915.rst: Narration overview on GEM + minor reorder to improve narration

2018-04-03 Thread Joonas Lahtinen
Quoting kevin.rogo...@intel.com (2018-04-03 13:52:23) > From: Kevin Rogovin > > Add a narration to i915.rst about Intel GEN GPU's: engines, > driver context and relocation. > > Signed-off-by: Kevin Rogovin I'm still bummed by the long lines in the bulleted list, but regardless: Reviewed-by: J

Re: [Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing

2018-04-03 Thread Chris Wilson
Quoting Tvrtko Ursulin (2018-04-03 12:36:44) > From: Tvrtko Ursulin > > Reset and unwedge stress testing is supposed to trigger wedging or resets > at incovenient times and then re-use the context so either the context or > driver tracking might get confused and break. > > v2: > * Renamed for m

[Intel-gfx] ✗ Fi.CI.IGT: failure for GuC, HuC Loading Support for Cannonlake. (rev2)

2018-04-03 Thread Patchwork
== Series Details == Series: GuC, HuC Loading Support for Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/41031/ State : failure == Summary == Possible new issues: Test core_auth: Subgroup basic-auth: pass -> SKIP (shard-snb)

[Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing

2018-04-03 Thread Tvrtko Ursulin
From: Tvrtko Ursulin Reset and unwedge stress testing is supposed to trigger wedging or resets at incovenient times and then re-use the context so either the context or driver tracking might get confused and break. v2: * Renamed for more sensible naming. * Added some comments to explain what t

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Track begin/end of execlists submission sequences

2018-04-03 Thread Chris Wilson
Quoting Francisco Jerez (2018-04-02 17:32:20) > Chris Wilson writes: > > > We would like to start doing some bookkeeping at the beginning, between > > contexts and at the end of execlists submission. We already mark the > > beginning and end using EXECLISTS_ACTIVE_USER, to provide an indication >

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Track begin/end of execlists submission sequences

2018-04-03 Thread Mika Kuoppala
Chris Wilson writes: > We would like to start doing some bookkeeping at the beginning, between > contexts and at the end of execlists submission. We already mark the > beginning and end using EXECLISTS_ACTIVE_USER, to provide an indication > when the HW is idle. This give us a pair of sequence po

[Intel-gfx] [PATCH v4 0/5] Documentation patch for batchbuffer submission

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Note: I want to make a one or two follow-up series that provide narration and potentially additional documentation for GUC submission and the breadcrumbs. v4: Drop some details from narration to provide better focus. (suggested/requested by Chris Wilson) Spelling an

[Intel-gfx] [PATCH v4 5/5] i915: add documentation to intel_engine_cs

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Add documentation to a number of the function pointer fields of intel_engine_cs. Signed-off-by: Kevin Rogovin --- drivers/gpu/drm/i915/intel_ringbuffer.h | 29 + 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer

[Intel-gfx] [PATCH v4 2/5] i915: add a text about what happens at bottom of stack in processing a batchbuffer

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Now that "DOC: User command execution" of i915_gem_execbuffer.c is included in the i915.rst, it is benecifial (for new developers) to read what happens at the bottom of the driver stack (in terms of bytes written to be read by the GPU) when processing a user-space batchbuffer.

[Intel-gfx] [PATCH v4 1/5] i915.rst: Narration overview on GEM + minor reorder to improve narration

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Add a narration to i915.rst about Intel GEN GPU's: engines, driver context and relocation. Signed-off-by: Kevin Rogovin --- Documentation/gpu/i915.rst | 116 drivers/gpu/drm/i915/i915_vma.h | 10 ++-- 2 files changed, 100 inser

[Intel-gfx] [PATCH v4 3/5] i915.rst: add link to documentation in i915_gem_execbuffer.c

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Add the documentation of "DOC: User command execution" of i915_gem_execbuffer.c into a new section in i915.rst. Signed-off-by: Kevin Rogovin --- Documentation/gpu/i915.rst | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/g

[Intel-gfx] [PATCH v4 4/5] i915: correct lazy ringbuffer and backing store documentation

2018-04-03 Thread kevin . rogovin
From: Kevin Rogovin Correct documentation of logical ring context implementation to note that ringbuffer and backing store are created lazily for all context types (driver global, local default context and local extra context). Signed-off-by: Kevin Rogovin --- drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev5)

2018-04-03 Thread Patchwork
== Series Details == Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev5) URL : https://patchwork.freedesktop.org/series/36068/ State : warning == Summary == Series 36068v5 YCBCR 4:2:0/4:4:4 output support for LSPCON https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/5/mbox

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev5)

2018-04-03 Thread Patchwork
== Series Details == Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev5) URL : https://patchwork.freedesktop.org/series/36068/ State : warning == Summary == $ dim checkpatch origin/drm-tip 093f7ee765f1 drm/i915: Introduce CRTC output format -:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment s

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v3] intel-gpu-top: Rewrite the tool to be safe to use

2018-04-03 Thread Tvrtko Ursulin
On 30/03/2018 20:15, Rinat Ibragimov wrote: Четверг, 29 марта 2018, 21:46 +03:00 от Tvrtko Ursulin : +#define engine_ptr(engines, n) \ +((struct engine *)((unsigned char *)(&engines->engine) + (n) * sizeof(struct engine))) I think (&engines->engine + (n)) is easier to read. Absolutel

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

2018-04-03 Thread Tvrtko Ursulin
On 29/03/2018 15:30, Eero Tamminen wrote: Hi, I tested this on HSW GT2, BYT, BDW GT3, SKL GT2 and KBL GT3e, with Ubuntu 16.04 and 17.10, using Ubuntu default kernels (4.4 to 4.13) and latest drm-tip build (4.16.0-rc7). General comments This will be used by our customers and

[Intel-gfx] ✗ Fi.CI.BAT: failure for GuC, HuC Loading Support for Cannonlake. (rev2)

2018-04-03 Thread Patchwork
== Series Details == Series: GuC, HuC Loading Support for Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/41031/ State : failure == Summary == Series 41031v2 GuC, HuC Loading Support for Cannonlake. https://patchwork.freedesktop.org/api/1.0/series/41031/revisions/2/mbox/ ---

[Intel-gfx] [PATCH i-g-t v4] intel-gpu-top: Rewrite the tool to be safe to use

2018-04-03 Thread Tvrtko Ursulin
From: Tvrtko Ursulin intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio register access. This patch rewrites it to use only PMU. Only overall command streamer busyness and GPU global data such as power and frequencies are included in this new version. For access to more G

[Intel-gfx] [PATCH v7 1/8] drm/i915: Introduce CRTC output format

2018-04-03 Thread Shashank Sharma
This patch adds an enum "intel_output_format" to represent the output format of a particular CRTC. This enum will be used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format during the atomic modeset calculations. V5: - Created this separate patch to introduce and init output_format. - Initialize

[Intel-gfx] [PATCH v7 6/8] drm/i915: Write AVI infoframes for MCA LSPCON

2018-04-03 Thread Shashank Sharma
From: "Sharma, Shashank" As LSPCON is a DP branch device, LSPCON vendors define specific methods to pass AVI infoframes to the the chip. This patch adds: - a generic wrapper function for writing AVI infoframes for all LSPCON devices. - a vendor specific function to wrire AVI infoframes into M

[Intel-gfx] [PATCH v7 2/8] drm/i915: Add CRTC output format YCBCR 4:2:0

2018-04-03 Thread Shashank Sharma
Currently, we are using a bool in CRTC state (state->ycbcr420), to indicate modeset, that the output format is YCBCR 4:2:0. Now in order to support other YCBCR formats, we will need more such flags. This patch adds a new enum parameter for YCBCR 4:2:0 outputs, in the CRTC output formats and then p

[Intel-gfx] [PATCH v7 3/8] drm/i915: Add CRTC output format YCBCR 4:4:4

2018-04-03 Thread Shashank Sharma
This patch adds support for YCBCR 4:4:4 CRTC output format. To do this, this patch extends the existing YCBCR 4:2:0 framework by: - Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format. - Adding case for YCBCR 4:4:4 in while setting AVI infoframes. - Adding necessary checks in modeset se

[Intel-gfx] [PATCH v7 4/8] drm/i915: Check LSPCON vendor OUI

2018-04-03 Thread Shashank Sharma
From: "Sharma, Shashank" Intel LSPCON chip is provided by 2 vendors: - Megachips America (MCA) - Parade technologies (Parade tech) Its important to know the vendor of this chip, as the address to write AVI infoframes is different for those two. This patch reads the vendor OUI signature, and mar

[Intel-gfx] [PATCH v7 5/8] drm/i915: Add AVI infoframe support for LSPCON

2018-04-03 Thread Shashank Sharma
In order to pass AVI infoframes to LSPCON devices, a source has to write them in a vendor recommended method and location. This patch series: - adds generic LSPCON infoframe setup functions. - registers these functions into existing AVI infoframe framework. - triggers these functions from modeset

[Intel-gfx] [PATCH v7 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON

2018-04-03 Thread Shashank Sharma
This patch series adds YCBCR 4:2:0 output support for LSPCON displays. In order to indicate the color format of output, to the LSPCON device, a source has to set and send proper AVI infoframes to LSPCON. So this patch series: - introduces concept of CRTC output format. - adds AVI infoframes support

[Intel-gfx] [PATCH v7 7/8] drm/i915: Write AVI infoframes for Parade LSPCON

2018-04-03 Thread Shashank Sharma
Different LSPCON vendors specify their custom methods to pass AVI infoframes to the LSPCON chip, so does Parade tech. This patch adds functions to arrange and write AVI infoframes into Parade LSPCON chips. V2: rebase V3: Added r-b from Maarten V4: rebase V5: rebase V6: rebase V7: Fixed checkpatch

[Intel-gfx] [PATCH v7 8/8] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

2018-04-03 Thread Shashank Sharma
LSPCON chips can generate YCBCR outputs, if asked nicely :). In order to generate YCBCR 4:2:0 outputs, a source must: - send YCBCR 4:4:4 signals to LSPCON - program color space as 4:2:0 in AVI infoframes Whereas for YCBCR 4:4:4 outputs, the source must: - send YCBCR 4:4:4 signals to LSPCON - prog

[Intel-gfx] [PULL] gvt-fixes for 4.17-rc1

2018-04-03 Thread Zhenyu Wang
Hi, Here's refreshed fixes for 4.17-rc1 with regression one removed, contains a few fixes for vfio ioctl and dmabuf interface, properly dma unmap for ggtt, etc. thanks -- The following changes since commit d8303075699292008ae5b2c8fc728d455b994c26: drm/i915/gvt: force to set all context contro

Re: [Intel-gfx] [stable:v4.15] drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.

2018-04-03 Thread Jani Nikula
DK, please start stable backport commit messages with: commit b1e314462bba76660eec62760bb2e87f28f58866 upstream. Referencing the upstream commit. BR, Jani. On Thu, 29 Mar 2018, Dhinakaran Pandiyan wrote: > If bios sets up an MST output and hardware state readout code sees this is > an SST co

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