-Original Message-
From: Vivi, Rodrigo
Sent: Friday, April 20, 2018 11:06 PM
To: Nagaraju, Vathsala
Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
Subject: Re: [PATCH] drm/i915/psr : Add psr1 live status
On Fri, Apr 20, 2018 at 03:06:03PM +0530, vathsala nagaraju wrote:
>
Hi all:
We tested GLK DMC 1.04 FW in last week of September 2017, using the latest
drm-tip version for that time (4.14.0-rc2) and according to our results we
could declare this FW as acceptable and healthy to be used with kernel version
4.14 .
However, we cannot guarantee quality and healthy o
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information
about what caused a PSR exit
URL : https://patchwork.freedesktop.org/series/42058/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4073_full -> Patchwork_8769_full =
== Summary -
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information
about what caused a PSR exit
URL : https://patchwork.freedesktop.org/series/42058/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4073 -> Patchwork_8769 =
== Summary - SUCCESS ==
On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
>
> Bspec: 7721 an
On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
This seems a good
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information
about what caused a PSR exit
URL : https://patchwork.freedesktop.org/series/42058/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac17ffd9158a drm/i915/psr/skl+: Print information ab
This was my bad, spec says that the name of this bit is
'Y-coordinate valid' but the values for it is:
0: Include Y-coordinate valid eDP1.4a
1: Do not include Y-coordinate valid eDP 1.4
So not setting it.
BSpec: 7713
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto
This will be helpful to debug what hardware is actually tracking
and causing PSR to exit.
BSpec: 7721
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
New patch in this series.
drivers/gpu/drm/i915/i915_reg.h | 23
drivers/gpu/drm/i915/inte
Any write in any display register was causing HW to exit PSR,
masking it to allow more power savings. Writes to pipe related
registers will still cause HW to exit PSR.
This is already masked for PSR2.
Bspec: 7721 and 8042
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de S
IGT tests could be improved with sink status, knowing for sure that
hardware have activate or exit PSR.
Reviewed-by: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
No changes since v2, Dhinakaran asked to not merge this patch in v2
because reading i915_edp_psr_st
On Tue, Apr 17, 2018 at 01:01:39PM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Tue, 2018-04-17 at 20:41 +0300, Ville Syrjälä wrote:
> > On Mon, Apr 16, 2018 at 05:43:54PM -0700, Paulo Zanoni wrote:
> > > Em Qui, 2018-04-05 às 15:00 -0700, Dhinakaran Pandiyan escreveu:
> > > > From: Daniel Vette
On Wed, Apr 18, 2018 at 08:46:44AM +0300, Jani Nikula wrote:
> On Tue, 17 Apr 2018, Souptick Joarder wrote:
> > On 17-Apr-2018 9:45 PM, "Matthew Wilcox" wrote:
> >>
> >> On Tue, Apr 17, 2018 at 09:14:32PM +0530, Souptick Joarder wrote:
> >> > Not exactly. The plan for these patches is to introduc
== Series Details ==
Series: Workarounds for Icelake
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8768_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8768_full need
On Thu, Apr 12, 2018 at 05:58:02PM +0300, Mika Kuoppala wrote:
> Evidence indicates that Cannonlake HWSP is not coherent
> as it should. Revert to using mmio access for now.
>
> Testcase: igt/gem_ctx_switch
> References: https://bugs.freedesktop.org/show_bug.cgi?id=105888
> Cc: Chris Wilson
> Cc:
On Fri, Apr 20, 2018 at 02:29:27PM -0700, Oscar Mateo wrote:
>
>
> On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
> > >
> > > On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > > > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wr
On Tue, Apr 10, 2018 at 11:29:09AM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Tue, 2018-04-10 at 10:59 -0700, Rodrigo Vivi wrote:
> > On Tue, Apr 10, 2018 at 12:49:25AM -, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: series starting with [v4] drm/i915: Enable edp psr er
On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynam
On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
>
>
> On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> > > Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> > > power by dynamically changing its clock fr
On Wed, Apr 18, 2018 at 03:43:08PM -0700, José Roberto de Souza wrote:
> Sink can be configured to calculate the CRC over the static frame and
> compare with the CRC calculated and transmited in the VSC SDP by
> source, if there is a mismatch sink will do a short pulse in HPD
> and set DP_PSR_LINK_
== Series Details ==
Series: Workarounds for Icelake
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8768 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop
== Series Details ==
Series: Workarounds for Icelake
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expre
On Fri, 2018-04-20 at 20:20 +, Patchwork wrote:
> Possible regressions
>
> igt@drv_module_reload@basic-no-display:
> fi-elk-e7500: PASS -> DMESG-FAIL +2
>
> igt@drv_module_reload@basic-reload:
> fi-gdg-551: PASS -> DMESG-FAIL +2
> fi-blb-
== Series Details ==
Series: Workarounds for Icelake
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
abf7b0421b03 drm/i915/icl: Introduce initial Icelake Workarounds
-:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - poss
On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
>
>
> On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> > > Disable GWL clock gating to prevent two different issues that
> > > might cause hangs.
> > >
> > > Please notice t
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen1
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
>
> v2: Wrong operation to clear the bi
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> Disable GWL clock gating to prevent two different issues that
> might cause hangs.
>
> Please notice that one of the issues is pre-production only.
>
> v2: Rebased on top of the WA refactoring
>
> Cc: Mika Kuoppala
> Signed-off-by:
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 7 insertions(+)
di
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --gi
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring
Cc: Praveen Paner
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA r
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workar
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
1 file c
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add ice
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of t
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 5 ++
List of GT workarounds for Icelake that we have been carrying in internal.
Can we get eyes on these please?
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i
Disable blend embellishment in RCC.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 16 insertions(+), 7 deletions(-)
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files c
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_w
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 14 insertions(+), 5
On Fri, 2018-04-20 at 11:15 -0700, Rodrigo Vivi wrote:
> On Thu, Apr 19, 2018 at 10:03:05AM +0300, Mika Kahola wrote:
> > On Thu, 2018-04-19 at 09:11 +0300, Lofstedt, Marta wrote:
> > > For the PW results:
> > > https://patchwork.freedesktop.org/series/41877/
> > >
> > > it didn't fix the CRC mis
== Series Details ==
Series: series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1
URL : https://patchwork.freedesktop.org/series/42054/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8767 =
== Summary - FAILURE ==
Serious unknown changes c
== Series Details ==
Series: series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1
URL : https://patchwork.freedesktop.org/series/42054/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4c8f8499a696 agp/intel-gtt: Drop the code for gen > 1
-:8: ERROR:GIT_COMMIT_ID: P
The gen2+ code has been unreachable since:
commit ebb7c78d358b2ea45c7d997423e6feb42e5ce4ef
Author: Daniel Vetter
Date: Wed Jan 27 14:38:00 2016 +0100
agp/intel-gtt: Only register fake agp driver for gen1
Signed-off-by: Adam Jackson
---
drivers/char/agp/intel-gtt.c | 631
The i810 was attached to Pentium III motherboards, no 64-bit CPU is ever
going to have one.
Signed-off-by: Adam Jackson
---
drivers/gpu/drm/i915/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index dfd95889f
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, April 20, 2018 11:04 AM
>To: Jani Nikula
>Cc: Srivatsa, Anusha ; Ian W MORRISON
>; airl...@linux.ie; Greg KH
>; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; sta...@vger.kernel.org; dri-
>de...@lists.freedesktop.o
On Thu, Apr 19, 2018 at 10:03:05AM +0300, Mika Kahola wrote:
> On Thu, 2018-04-19 at 09:11 +0300, Lofstedt, Marta wrote:
> > For the PW results:
> > https://patchwork.freedesktop.org/series/41877/
> >
> > it didn't fix the CRC mismatch on:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8
On Tue, Apr 17, 2018 at 12:02:52PM +0300, Jani Nikula wrote:
> On Mon, 16 Apr 2018, "Srivatsa, Anusha" wrote:
> >>-Original Message-
> >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> >>Sent: Wednesday, April 11, 2018 5:27 AM
> >>To: Ian W MORRISON
> >>Cc: Vivi, Rodrigo ; Srivat
== Series Details ==
Series: Aspect ratio support in DRM layer
URL : https://patchwork.freedesktop.org/series/42030/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8766_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_876
On 04/20/2018 08:51 AM, Daniel Vetter wrote:
Control nodes are no more!
Signed-off-by: Daniel Vetter
Cc: VMware Graphics
Cc: Sinclair Yeh
Cc: Thomas Hellstrom
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
Dear Jose,
On 04/19/18 01:41, Souza, Jose wrote:
If the initial fbdev configuration(intel_fbdev_initial_config()) runs and
Nit: Space before (.
there still no sink connected it will cause
drm_fb_helper_initial_config() to return 0 as no error happened(but
internally the return is -EAGAIN).
On Fri, Apr 20, 2018 at 03:06:03PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
>
> Tested on KBL with psr2 and psr1 panel.
Does it really work?
I mean... I heard DK complaining that any
== Series Details ==
Series: series starting with [1/4] drm/i915: Stop tracking
timeline->inflight_seqnos
URL : https://patchwork.freedesktop.org/series/42033/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8765_full =
== Summary - WARNING ==
Minor
On Fri, 2018-04-20 at 15:06 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
>
> Tested on KBL with psr2 and psr1 panel.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
>
> Signed-off-by: V
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Friday, April 20, 2018 9:56 AM
> To: Bloomfield, Jon ; Tvrtko Ursulin
> ; Intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean
> any second VCS instance
>
>
> On 20/04/2018 15:19
== Series Details ==
Series: Aspect ratio support in DRM layer
URL : https://patchwork.freedesktop.org/series/42030/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8766 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.f
On 20/04/2018 15:19, Bloomfield, Jon wrote:
-Original Message-
From: Tvrtko Ursulin
Sent: Wednesday, April 18, 2018 2:34 AM
To: Intel-gfx@lists.freedesktop.org
Cc: tursu...@ursulin.net; Ursulin, Tvrtko ; Chris
Wilson ; Bloomfield, Jon
; Ye, Tony
Subject: [PATCH] drm/i915/icl: Adjust BS
== Series Details ==
Series: series starting with [1/2] drm/i915: Use ktime on wait_for
URL : https://patchwork.freedesktop.org/series/42035/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8764_full =
== Summary - FAILURE ==
Serious unknown changes
Hi,
On 04/20/2018 03:52 PM, Patchwork wrote:
== Series Details ==
Series: drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated
buffers (rev3)
URL : https://patchwork.freedesktop.org/series/40929/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full ->
== Series Details ==
Series: Aspect ratio support in DRM layer
URL : https://patchwork.freedesktop.org/series/42030/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
004a2f4d2e45 drm/modes: Introduce drm_mode_match()
-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open p
== Series Details ==
Series: series starting with [1/4] drm/i915: Stop tracking
timeline->inflight_seqnos
URL : https://patchwork.freedesktop.org/series/42033/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8765 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/4] drm/i915: Stop tracking
timeline->inflight_seqnos
URL : https://patchwork.freedesktop.org/series/42033/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Stop tracking timeline->inflight_seqnos
-O:drivers/gpu/dr
== Series Details ==
Series: series starting with [1/4] drm/i915: Stop tracking
timeline->inflight_seqnos
URL : https://patchwork.freedesktop.org/series/42033/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9beb7851c63 drm/i915: Stop tracking timeline->inflight_seqnos
-:14: ER
== Series Details ==
Series: series starting with [1/2] drm/i915: Use ktime on wait_for
URL : https://patchwork.freedesktop.org/series/42035/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8764 =
== Summary - SUCCESS ==
No regressions found.
External
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subse
On Fri, Apr 20, 2018 at 08:31:56AM +, Lisovskiy, Stanislav wrote:
>
>
> From: Daniel Vetter [daniel.vet...@ffwll.ch] on behalf of Daniel Vetter
> [dan...@ffwll.ch]
>
> > The property documentation to tie all the bits together (property, helper,
> > in
On Fri, Apr 20, 2018 at 07:01:49PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal
>
> We parse the EDID and add all the modes in the connector's modelist.
> This adds CEA modes with aspect ratio information too, regardless of
> whether user space requested this information or not.
>
> Th
On Fri, Apr 20, 2018 at 07:01:47PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal
>
> This patch adds helper functions for determining if aspect-ratio is
> expected in user-mode and for allowing/disallowing the aspect-ratio,
> if its not expected.
>
> Signed-off-by: Ankit Nautiyal
> ---
Hi Chandra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc1 next-20180420]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Quoting Mika Kuoppala (2018-04-20 14:45:50)
> We need to be careful to not let compiler evaluate
> the expiration and the operation on it's terms.
>
> Document and enforce that COND will be evaluated
> before checking timeout expiration.
>
> Suggested-by: Chris Wilson
> Cc: Chris Wilson
> Signe
From: Ankit Nautiyal
This patch series is a re-attempt to enable aspect ratio support in
DRM layer. Currently the aspect ratio information gets lost in translation
during a user->kernel mode or vice versa.
The old patch series (https://pw-emeril.freedesktop.org/series/10850/) had
4 patches, out
From: "Sharma, Shashank"
HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135
This patch:
- Adds new DRM flags for to represent these new aspect ratios.
- Adds new cases to handle these aspect ratios while converting
from user->kernel mode or vise versa.
This patch was once
In the next patch, rings are the central timeline as requests may jump
between engines. Therefore in the future as we retire in order along the
engine timeline, we may retire out-of-order within a ring (as the ring now
occurs along multiple engines), leading to much hilarity in miscomputing
the pos
In commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine"), we
moved from a global inflight counter to per-engine counters in the
hope that will be easy to run concurrently in future. However, with the
advent of the desire to move requests between engines, we do need a
global counter to pr
From: Ankit Nautiyal
This patch adds helper functions for determining if aspect-ratio is
expected in user-mode and for allowing/disallowing the aspect-ratio,
if its not expected.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/drm_modes.c | 47 +
i
From: "Sharma, Shashank"
Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.
This patch add
On Fri, Apr 20, 2018 at 07:01:46PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal
>
> To enable aspect-ratio support in DRM, blindly exposing the aspect
> ratio information along with mode, can break things in existing
> user-spaces which have no intention or support to use this aspect
>
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Wednesday, April 18, 2018 2:34 AM
> To: Intel-gfx@lists.freedesktop.org
> Cc: tursu...@ursulin.net; Ursulin, Tvrtko ; Chris
> Wilson ; Bloomfield, Jon
> ; Ye, Tony
> Subject: [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second
From: Ville Syrjälä
Use drm_mode_equal_no_clocks_no_stereo() in
drm_match_hdmi_mode_clock_tolerance() for consistency as we
also use it in drm_match_hdmi_mode() and the cea mode matching
functions.
This doesn't actually change anything since the input mode
comes from detailed timings and we matc
We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When this happens
in a wait_for loop, we return timeout errorneously
much earlier than what the real wallclock would say.
We can't afford our waits to ti
In the future, we want to move a request between engines. To achieve
this, we first realise that we have two timelines in effect here. The
first runs through the GTT is required for ordering vma access, which is
tracked currently by engine. The second is implied by sequential
execution of commands
From: Ville Syrjälä
AVI infoframe can only carry none, 4:3, or 16:9 picture aspect
ratios. Return an error if the user asked for something different.
Cc: Shashank Sharma
Cc: "Lin, Jia"
Cc: Akashdeep Sharma
Cc: Jim Bride
Cc: Jose Abreu
Cc: Daniel Vetter
Cc: Emil Velikov
Cc: Thierry Reding
From: Ville Syrjälä
Make mode matching less confusing by allowing the caller to specify
which parts of the modes should match via some flags.
Signed-off-by: Ville Syrjälä
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_modes.c | 134 ++--
include/d
== Series Details ==
Series: drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated
buffers (rev3)
URL : https://patchwork.freedesktop.org/series/40929/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8763_full =
== Summary - FAILURE ==
We need to be careful to not let compiler evaluate
the expiration and the operation on it's terms.
Document and enforce that COND will be evaluated
before checking timeout expiration.
Suggested-by: Chris Wilson
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_drv.h
From: Ville Syrjälä
If the user mode would specify an aspect ratio other than 4:3 or 16:9
we now silently ignore it. Maybe a better apporoach is to return an
error? Let's try that.
Also we must be careful that we don't try to send illegal picture
aspect in the infoframe as it's only capable of s
From: Ankit Nautiyal
If the user-space does not support aspect-ratio, and requests for a
modeset with mode having aspect ratio bits set, then the given
user-mode must be rejected. Secondly, while preparing a user-mode from
kernel mode, the aspect-ratio info must not be given, if aspect-ratio
is n
From: Ville Syrjälä
commit 6dffd431e229 ("drm: Add aspect ratio parsing in DRM layer")
cause us to not send out any VICs in the AVI infoframes. That commit
was since reverted, but if and when we add aspect ratio handing back
we need to be more careful.
Let's handle this by considering the aspect
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