tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: e2ea2db1734a0e38b89e4d706b5f9ad9f73b1543
commit: 72041f9847abb05b9d4d7dea17631b579191ca99 [7/8] RFC: debugobjects:
capture stack traces at _init() time
config: m68k-allyesconfig (attached as .config)
compiler:
== Series Details ==
Series: drm/i915: Wrap around the tail offset before setting ring->tail (rev2)
URL : https://patchwork.freedesktop.org/series/44500/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4296_full -> Patchwork_9249_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
URL : https://patchwork.freedesktop.org/series/44501/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9248_full =
== Summary - WARNING ==
Minor unknown
guc also uses timer-based sampling and cannot reliably hit our accuracy
requirements for the test, so skip.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R
>Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Remove redundant
hsw_mm_switch()
URL : https://patchwork.freedesktop.org/series/44491/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9245_full =
== Summary - WARNING ==
== Series Details ==
Series: drm/i915: Wrap around the tail offset before setting ring->tail (rev2)
URL : https://patchwork.freedesktop.org/series/44500/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4296 -> Patchwork_9249 =
== Summary - WARNING ==
Minor unknown changes
From: Ville Syrjälä
On SKL+ the dst colorkey is enabled on the primary plane instead of the
sprite plane. That means the restriction of scaling vs. keying doesn't
actually apply here as we never scale the primary. So let's remove
the requirement of having XV_ALWAYS_ON_TOP enabled to get hw
As the swizzling is baked into the tiling pattern, the swizzling has to
be consistent across the entire GTT mmap for our tests to work. However,
under L-shaped memory configurations on older architectures, the
swizzling varied depending on which region the page found itself in --
invalidating our
The HW only accepts offsets within ring->size, and fails peculiarly if
the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we
set ring->head/ring->tail we want to make sure it is within value (using
intel_ring_wrap()).
v2: Double check execlists as well
Signed-off-by: Chris
== Series Details ==
Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev3)
URL : https://patchwork.freedesktop.org/series/44421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9244_full =
== Summary - WARNING ==
Minor unknown changes
Quoting Matthew Auld (2018-06-08 18:54:15)
> On 8 June 2018 at 18:32, Chris Wilson wrote:
> > When we want to unwind an error when allocating the PD for gen6, we call
> > gen6_ppgtt_clear_range() telling to clear upto the PD we've previously
> > cleared. However, we passed it the incorrect
On Tue, Jun 05, 2018 at 08:10:36AM +, Lisovskiy, Stanislav wrote:
> On Tue, 2018-05-29 at 21:28 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On SKL+ the dst colorkey must be configured on the lower
> > plane that contains the colorkey. This is in contrast to
> > most earlier
== Series Details ==
Series: drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
URL : https://patchwork.freedesktop.org/series/44501/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9248 =
== Summary - WARNING ==
Minor unknown changes
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev3)
URL : https://patchwork.freedesktop.org/series/44486/
State : failure
== Summary ==
Applying: drm/i915: Apply batch location restrictions before pinning
Applying:
== Series Details ==
Series: drm/i915: Wrap around the tail offset before setting ring->tail
URL : https://patchwork.freedesktop.org/series/44500/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9246 =
== Summary - WARNING ==
Minor unknown changes coming
== Series Details ==
Series: series starting with [1/5] drm/i915: Move chipset definitions to
intel_chipset.h
URL : https://patchwork.freedesktop.org/series/44488/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9242_full =
== Summary - WARNING ==
On 8 June 2018 at 18:32, Chris Wilson wrote:
> When we want to unwind an error when allocating the PD for gen6, we call
> gen6_ppgtt_clear_range() telling to clear upto the PD we've previously
> cleared. However, we passed it the incorrect length, passing it the
> endpoint instead. Fortunately,
When we want to unwind an error when allocating the PD for gen6, we call
gen6_ppgtt_clear_range() telling to clear upto the PD we've previously
cleared. However, we passed it the incorrect length, passing it the
endpoint instead. Fortunately, as the start was always 0, this has no
impact today,
The discovery with trying to enable full-ppgtt was that we were
completely failing to the load both the mm and context following the
reset. Although we were performing mmio to set the PP_DIR (per-process
GTT) and CCID (context), these were taking no effect (the assumption was
that this would
The HW only accepts offsets within ring->size, and fails peculiarly if
the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we
set ring->head/ring->tail we want to make sure it is within value (using
intel_ring_wrap()).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika
Quoting Chris Wilson (2018-06-08 17:36:28)
> Quoting Patchwork (2018-06-08 17:23:38)
> > == Series Details ==
> >
> > Series: series starting with [01/18] drm/i915: Apply batch location
> > restrictions before pinning (rev2)
> > URL : https://patchwork.freedesktop.org/series/44486/
> > State :
Quoting Patchwork (2018-06-08 17:23:38)
> == Series Details ==
>
> Series: series starting with [01/18] drm/i915: Apply batch location
> restrictions before pinning (rev2)
> URL : https://patchwork.freedesktop.org/series/44486/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev2)
URL : https://patchwork.freedesktop.org/series/44486/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9241_full =
== Summary -
On 06/08/2018 06:31 AM, Imre Deak wrote:
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
== Series Details ==
Series: series starting with [1/5] drm/i915: fix guest virtual PCH detection on
non-PCH systems
URL : https://patchwork.freedesktop.org/series/44484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9239_full =
== Summary - WARNING
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Remove redundant
hsw_mm_switch()
URL : https://patchwork.freedesktop.org/series/44491/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9245 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev3)
URL : https://patchwork.freedesktop.org/series/44421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9244 =
== Summary - SUCCESS ==
No regressions found.
Since vgpu is not supported on Haswell or any other gen6/7, we do not
need to check and act upon it's enablement.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
1 file changed,
On Fri, 08 Jun 2018 15:42:01 +0200, Mika Kuoppala
wrote:
Carve out chipset definitions into new intel_chipset.h
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 194 +
drivers/gpu/drm/i915/intel_chipset.h | 202
== Series Details ==
Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev2)
URL : https://patchwork.freedesktop.org/series/44421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9243 =
== Summary - WARNING ==
Minor unknown changes coming
Quoting Matthew Auld (2018-06-08 15:37:43)
> Ah, in gen6_alloc_va_range() I think we now need:
>
> unwind_out:
> - gen6_ppgtt_clear_range(vm, from, start);
> + gen6_ppgtt_clear_range(vm, from, start - from);
You are very right.
-Chris
___
While checking workarounds related to the CDCLK PLL, I noticed that the
DMC firmware bits for WA#1183 are missing for SKL. After that I
clarified with HW people that it's not needed on SKL, since it doesn't
support eDP1.4 which would be the only thing requiring the problematic
CDCLK clock rates.
On 8 June 2018 at 13:55, Chris Wilson wrote:
> As we were only supporting aliasing_ppgtt on gen7 for some time, we
> saved a few checks by preallocating the page directories on creation.
> However, since we need 2MiB of page directories for each ppgtt, to
> support arbitrary numbers of user
On Fri, Jun 08, 2018 at 05:00:02PM +0300, Imre Deak wrote:
> While checking workarounds related to the CDCLK PLL, I noticed that the
> DMC firmware bits for WA#1183 are missing for SKL. After that I
> clarified with HW people that it's not needed on SKL, since it doesn't
> support eDP1.4 which
Quoting Mika Kuoppala (2018-06-08 14:42:02)
> Store first known production revid into the device info.
>
> This enables us to easily see if we are running on
> a preproduction hardware.
>
> Uninitialized (zero) product revision id means that
> there are no known preliminary hardware for this
Quoting Chris Wilson (2018-06-08 13:55:47)
> @@ -570,42 +585,10 @@ static void reset_ring(struct intel_engine_cs *engine,
> * the restored context.
> */
> if (request) {
> - struct drm_i915_private *dev_priv = request->i915;
> - struct
== Series Details ==
Series: series starting with [1/5] drm/i915: Move chipset definitions to
intel_chipset.h
URL : https://patchwork.freedesktop.org/series/44488/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9242 =
== Summary - WARNING ==
Minor
== Series Details ==
Series: series starting with [1/5] drm/i915: Move chipset definitions to
intel_chipset.h
URL : https://patchwork.freedesktop.org/series/44488/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Move chipset definitions to intel_chipset.h
Chris Wilson writes:
> Since vgpu is not supported on Haswell or any other gen6/7, we do not
> need to check and act upon it's enablement.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
> ---
>
== Series Details ==
Series: series starting with [1/5] drm/i915: Move chipset definitions to
intel_chipset.h
URL : https://patchwork.freedesktop.org/series/44488/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b04c01486105 drm/i915: Move chipset definitions to intel_chipset.h
Chris Wilson writes:
> hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
> redundant specialism.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 24
While checking workarounds related to the CDCLK PLL, I noticed that the
DMC firmware bits for WA#1183 are missing for SKL. After that I
clarified with HW people that it's not needed on SKL, since it doesn't
support eDP1.4 which would be the only thing requiring the problematic
CDCLK clock rates.
Quoting Mika Kuoppala (2018-06-08 14:52:13)
> Chris Wilson writes:
>
> > An issue encountered with switching mm on gen7 is that the GPU likes to
> > hang (with the VS unit busy) when told to force restore the current
> > context. We can simply workaround this by substituting the
> >
Quoting Mika Kuoppala (2018-06-08 14:42:01)
> Carve out chipset definitions into new intel_chipset.h
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Please check with Jani and Rodrigo that this fits in with our new/old
platform strategy.
> diff --git
Quoting Mika Kuoppala (2018-06-08 14:42:03)
> We don't need to have distinct flag for alpha quality if
> we agree that setting the first production revid to be the
> epoch for stepping out from alpha quality on that platform.
>
> v2: rebase, comment beautification
>
> Cc: Joonas Lahtinen
> Cc:
Quoting Mika Kuoppala (2018-06-08 14:42:04)
> We don't need kbl preprod workarounds anymore.
>
> Signed-off-by: Mika Kuoppala
As we now consider cnl stable, and icl the new development branch, we
can rid ourselves of preproduction w/a for anything older than cnl. (By
my understanding of our
Chris Wilson writes:
> An issue encountered with switching mm on gen7 is that the GPU likes to
> hang (with the VS unit busy) when told to force restore the current
> context. We can simply workaround this by substituting the
> MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
Quoting Mika Kuoppala (2018-06-08 14:42:05)
> If we are doing revision checks against a preproduction
> range, when there is already a product, it is a sign
> that there is code to be removed.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_chipset.h | 30
Carve out chipset definitions into new intel_chipset.h
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 194 +
drivers/gpu/drm/i915/intel_chipset.h | 202 +++
2 files changed, 203 insertions(+), 193
Store first known production revid into the device info.
This enables us to easily see if we are running on
a preproduction hardware.
Uninitialized (zero) product revision id means that
there are no known preliminary hardware for this platform,
or that the platform is of gen that we don't care.
If we are doing revision checks against a preproduction
range, when there is already a product, it is a sign
that there is code to be removed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_chipset.h | 30 +---
1 file changed, 23 insertions(+), 7
We don't need kbl preprod workarounds anymore.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 12
drivers/gpu/drm/i915/intel_workarounds.c | 5 -
2 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
We don't need to have distinct flag for alpha quality if
we agree that setting the first production revid to be the
epoch for stepping out from alpha quality on that platform.
v2: rebase, comment beautification
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Tomi Sarvela
Cc: Jani Nikula
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev2)
URL : https://patchwork.freedesktop.org/series/44486/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9241 =
== Summary - WARNING ==
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> On GLK NUC platforms the HDMI retiming buffer needs additional disabled
> time to correctly sync to a faster incoming signal.
> When measured on a scope the highspeed
On Fri, Jun 08, 2018 at 03:50:47PM +0300, Jani Nikula wrote:
> On Fri, 08 Jun 2018, Dan Carpenter wrote:
> > Hello Jani Nikula,
> >
> > The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
> > block v3" from Jan 11, 2016, leads to the following static checker
> > warning:
> >
> >
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev2)
URL : https://patchwork.freedesktop.org/series/44486/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Apply batch location restrictions
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev2)
URL : https://patchwork.freedesktop.org/series/44486/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c1efb9574092 drm/i915: Apply batch location
Quoting Chris Wilson (2018-06-07 21:50:54)
> Recently we discovered that we have a race between swapping and
> suspend in our resume path (we might be trying to page in an object
> after disabling the block devices). Let's try to exercise that by
> exhausting all of system memory before suspend.
>
== Series Details ==
Series: HACK: drm/i915: see what breaks with display disabled
URL : https://patchwork.freedesktop.org/series/44485/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9240 =
== Summary - FAILURE ==
Serious unknown changes coming with
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the
== Series Details ==
Series: series starting with [1/5] drm/i915: fix guest virtual PCH detection on
non-PCH systems
URL : https://patchwork.freedesktop.org/series/44484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9239 =
== Summary - SUCCESS ==
No
The legacy gen6 ppgtt needs a little more hand holding than gen8+, and
so requires a larger structure. As I intend to make this slightly more
complicated in the future, separate the gen6 from the core gen8 hw
struct by subclassing. This patch moves the gen6 only features out to
gen6_hw_ppgtt and
As we cannot reliably change used page tables while the context is
active, the earliest opportunity we have to recover excess pages is when
the context becomes idle. So whenever we unbind the context (it must be
idle, and indeed being evicted) free the unused ptes.
Signed-off-by: Chris Wilson
If we know that the user cannot access the GGTT, by virtue of having a
segregated memory area, we can skip clearing the unused entries as they
cannot be accessed.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
1 file changed, 24 deletions(-)
diff --git
When we update the gen6 ppgtt page directories, we do so by writing the
new address into a reserved slot in the GGTT. It appears that when the
GPU reads that entry from the gsm, it uses its small cache and that we
need to invalidate that cache after writing. We don't see an issue
currently as we
As we were only supporting aliasing_ppgtt on gen7 for some time, we
saved a few checks by preallocating the page directories on creation.
However, since we need 2MiB of page directories for each ppgtt, to
support arbitrary numbers of user contexts, we need to be more prudent
in our allocations,
As the most frequent PTE encoding is for the scratch page, cache it upon
creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
We can stop asserting using WARN_ON as given sufficient CI coverage, we
can rely on using GEM_BUG_ON() to catch problems before merging.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2
Pull the empty stubs together into the top level gen6_ppgtt_create, and
tear each one down on error in proper onion order (rather than use
Joonas' pet hate of calling the cleanup function in indeterminable
state).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew
In order to be able to evict the gen6 ppgtt, we have to unpin it at some
point. We can simply use our context activity tracking to know when the
ppgtt is no longer in use by hardware, and so only keep it pinned while
being used a request.
For the kernel_context (and thus aliasing_ppgtt), it
The discovery with trying to enable full-ppgtt was that we were
completely failing to the load both the mm and context following the
reset. Although we were performing mmio to set the PP_DIR (per-process
GTT) and CCID (context), these were taking no effect (the assumption was
that this would
The GPU hangs in mesa (piglit at least) were resolved, and GPU reset
should now be operational. So as far as CI goes, we should have a clean
bill of health. There is still one outstanding issue as Baytail still
has the habit of writing to somewhere other than the intended mm.
-Chris
If we will completely overwrite the PT with PTEs for the object, we can
forgo filling it with scratch entries.
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by:
Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
let userspace have full control over their own ppgtt, it makes softpinning
far more effective, in turn making GPU dispatch far more efficient and
more
Since vgpu is not supported on Haswell or any other gen6/7, we do not
need to check and act upon it's enablement.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the
To allow ourselves to use a first class vma for the aliasing_ppgtt page
directory, we have to reorder the shutdown on module unload to remove
and unpin the aliasing_ppgtt before complaining about any objects left
in the GGTT.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
We special case the position of the batch within the GTT to prevent
negative self-relocation deltas from underflowing. However, that
restriction is being applied after a trial pin of the batch in its
current position. Thus we are not rejecting an invalid location if the
batch has been before,
An issue encountered with switching mm on gen7 is that the GPU likes to
hang (with the VS unit busy) when told to force restore the current
context. We can simply workaround this by substituting the
MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
forcing the context to be saved
On Fri, 08 Jun 2018, Dan Carpenter wrote:
> Hello Jani Nikula,
>
> The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
> block v3" from Jan 11, 2016, leads to the following static checker
> warning:
>
> drivers/gpu/drm/i915/intel_bios.c:926 goto_next_sequence_v3()
>
We don't properly test the i915.disable_display=1 module parameter. We
have one display info with .num_pipes = 0, but AFAIK there are others
than ivb q. Let's see what CI says of this for platforms with
display. *evil grin*.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.h | 2
Hello Jani Nikula,
The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
block v3" from Jan 11, 2016, leads to the following static checker
warning:
drivers/gpu/drm/i915/intel_bios.c:926 goto_next_sequence_v3()
warn: potentially one past the end of array
From: Lucas De Marchi
There's a difference between PCH_NONE and PCH_NOP: the former means we
don't have a PCH while in the latter we do, but it doesn't have the
south display.
Signed-off-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file
On Thu, 31 May 2018, Lucas De Marchi wrote:
> On Thu, May 31, 2018 at 02:56:21PM +0300, Jani Nikula wrote:
>> Virtualized non-PCH systems such as Broxton or Geminilake should use
>> PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
>> specific case to indicate a PCH system without
Setting PCH type to PCH_NOP before checking whether we actually have a
PCH ends up returning true for HAS_PCH_SPLIT() on all non-PCH split
platforms. Fix this by using PCH_NOP only for platforms that actually
have a PCH.
Cc: Ville Syrjala
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
Use intel_pch_type() also for mapping the no PCH case (PCH id 0) to
PCH_NONE to simplify code.
Also make sure that intel_pch_type() knows all the PCH ids returned by
intel_virt_detect_pch(). Loudly fail if this isn't the case; this
shouldn't happen anyway.
Cc: Colin Xu
Reviewed-by: Ville
HAS_PCH_NOP() implies a PCH platform without south display, not generic
disabled display. Prefer num_pipes == 0 for PCH independent checks.
Cc: Ville Syrjala
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c |
Just a resend of [1] with Lucas' patch added.
BR,
Jani.
[1] 20180531115624.30269-1-jani.nikula@intel.com">http://mid.mail-archive.com/20180531115624.30269-1-jani.nikula@intel.com
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Virtualized non-PCH systems such as Broxton or Geminilake should use
PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
specific case to indicate a PCH system without south display.
Reported-by: Colin Xu
Cc: Colin Xu
Reviewed-by: Ville Syrjälä
Tested-by: Colin Xu
Reviewed-by:
Hi Dave, these missed the main drm-next pull request.
drm-intel-next-fixes-2018-06-08-2:
First batch of i915 fixes for v4.18:
- gvt fixes that missed v4.17, potentially need to be backported
- eDP resolution regression revert
- remove broken nv12 special casing
- remove stale asserts from find
On Wed, 06 Jun 2018, Joonas Lahtinen wrote:
> Quoting Zhenyu Wang (2018-06-06 10:49:54)
>> On 2018.04.19 15:39:48 +0800, Zhenyu Wang wrote:
>> >
>> > Hi,
>> >
>> > Here's current gvt fixes for 4.17 with several kernel warning
>> > and other misc fixes as detailed below.
>> >
>> > p.s: I'll be
On Thu, 07 Jun 2018, Radhakrishna Sripada
wrote:
> From: "Sripada, Radhakrishna"
>
> Expand the Maud/Naud table according to DP 1.4 spec to include entries for
> 810 MHz clock. This is required for audio to work with HBR3.
>
> Cc: Dhinakaran Pandiyan
> Cc: Jani Nikula
> Signed-off-by:
== Series Details ==
Series: series starting with [1/6] drm/i915: Store first production revid into
device info (rev2)
URL : https://patchwork.freedesktop.org/series/44429/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9238 =
== Summary - FAILURE ==
== Series Details ==
Series: series starting with [1/6] drm/i915: Store first production revid into
device info (rev2)
URL : https://patchwork.freedesktop.org/series/44429/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Store first production revid into device
== Series Details ==
Series: series starting with [1/6] drm/i915: Store first production revid into
device info (rev2)
URL : https://patchwork.freedesktop.org/series/44429/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c1df0dd08b23 drm/i915: Store first production revid into
Quoting Mika Kuoppala (2018-06-08 09:39:06)
> Store first known production revid into the device info.
>
> This enables us to easily see if we are running on
> a preproduction hardware.
>
> Uninitialized (zero) product revision id means that
> there are no known preliminary hardware for this
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