== Series Details ==
Series: drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
URL : https://patchwork.freedesktop.org/series/47520/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600_full -> Patchwork_9828_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
URL : https://patchwork.freedesktop.org/series/47520/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9828 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
URL : https://patchwork.freedesktop.org/series/47518/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600_full -> Patchwork_9826_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in
this hook
URL : https://patchwork.freedesktop.org/series/47519/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9827 =
== Summary - FAILURE ==
Serious
We don't have proper watermark NV12 support on ICL due to differences
in how it should be implemented. In commit 234059da0f33
("drm/i915/icl: NV12 y-plane ddb is not in same plane") we avoided
writing the non-existent PLANE_NV12_BUF_CFG registers but we forgot to
also avoid them on the hardware
In case of Legacy DP connector on TypeC port (C, D, E or F), the
flex IO DPMLE register is set to maximum number of lanes since
there is no muxing with other controllers in this case.
While in case of the TypeC connector, it is set to the lane count
obained from DFLEXDPSP register.
This needs to
== Series Details ==
Series: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
URL : https://patchwork.freedesktop.org/series/47518/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9826 =
== Summary - SUCCESS ==
No regressions found.
Unlike the other ports, TC ports are not available to use as soon as
we get a hotplug. The TC PHYs can be shared between multiple
controllers: display, USB, etc. As a result, handshaking through FIA
is required around connect and disconnect to cleanly transfer
ownership with the controller and set
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; dri-de...@lists.freedesktop.org; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v2 03/23] drm/dp: DRM DP
== Series Details ==
Series: drm/i915: Drop stray clearing of rps->last_adj
URL : https://patchwork.freedesktop.org/series/47513/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9822_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP
URL : https://patchwork.freedesktop.org/series/47514/
State : failure
== Summary ==
Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Daniel
>Vetter ; Srivatsa, Anusha ;
>Singh, Gaurav K
>Subject: [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; dri-
>de...@lists.freedesktop.org; Jani Nikula ; Ville
>Syrjala ; Srivatsa, Anusha
>; Singh, Gaurav K
>Subject: [PATCH v2 01/23] drm/dp: Add DP
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions
private to gvt
URL : https://patchwork.freedesktop.org/series/47367/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9821_full =
== Summary - WARNING ==
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP
URL : https://patchwork.freedesktop.org/series/47514/
State : failure
== Summary ==
Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD
== Series Details ==
Series: drm/i915: Drop stray clearing of rps->last_adj
URL : https://patchwork.freedesktop.org/series/47513/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9822 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP
URL : https://patchwork.freedesktop.org/series/47514/
State : failure
== Summary ==
Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD
Quoting Lionel Landwerlin (2018-07-31 13:47:32)
> On 30/07/18 17:43, Chris Wilson wrote:
> > In the aub trace utility, the context images are terminated with a
> > MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
> > Do the same for our protocontext image for completeness,
Quoting Mahesh Kumar (2018-07-31 15:24:44)
> ddb_size is u16 so use same return type for intel_get_ddb_size
> wrapper.
>
> Signed-off-by: Mahesh Kumar
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Mahesh Kumar (2018-07-31 15:24:45)
> + for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> + const struct drm_display_mode *adjusted_mode;
> + int hdisplay, vdisplay;
> + enum pipe pipe;
> +
> + if (!crtc_state->enable)
>
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions
private to gvt
URL : https://patchwork.freedesktop.org/series/47367/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9821 =
== Summary - SUCCESS ==
No
Quoting Manasi Navare (2018-07-31 22:07:06)
> + /* PPS 4 */
> + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> + DSC_PPS_BPP_HIGH_MASK) >>
> + DSC_PPS_MSB_SHIFT) |
To avoid overhanging
From: Gaurav K Singh
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v5 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v4: (From Manasi)
* Rebase on top of revised patches
v3 (From Manasi):
* Use
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
From: Gaurav K Singh
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc:
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h |
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v5:
* Get the max slice width from DPCD
*
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable
DSC is supported on eDP starting GEN 10 display and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: dri-de...@lists.freedesktop.org
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define
We used to reset last_adj to 0 on crossing a power domain boundary, to
slow down our rate of change. However, commit 60548c554be2 ("drm/i915:
Interactive RPS mode") accidentally caused it to be reset on every
frequency update, nerfing the fast response granted by the slow start
algorithm.
Fixes:
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa,
>Anusha
>; Singh, Gaurav K ;
>Navare, Manasi D ; dri-
>de...@lists.freedesktop.org
>Subject:
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
On Tue, 2018-07-24 at 21:15 +0530, Uma Shankar wrote:
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -209,6 +209,17 @@
> #define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
> #define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
>
> +enum extended_colorimetry {
> +
On Tue, Jul 31, 2018 at 7:41 PM, Eric Dumazet wrote:
> On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote:
>
>>
>> If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU?
>
> To allow fast reuse of objects, without going through call_rcu() and
> reducing cache efficiency.
>
>
On Tue, Jul 31, 2018 at 10:10 AM Florian Westphal wrote:
>
> Andrey Ryabinin wrote:
> > Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache
> > without constructor.
> > I think it's nearly impossible to use that combination without having bugs.
> > It's either you don't
On Tue, Jul 31, 2018 at 10:51 AM Dmitry Vyukov wrote:
>
>
> Is it OK to overwrite ct->status? It seems that are some read and
> writes to it right after atomic_inc_not_zero.
If it is after a (successful) atomic_inc_not_zero(),
the object is guaranteed to be alive (not freed or about to be
Andrey Ryabinin wrote:
> Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache
> without constructor.
> I think it's nearly impossible to use that combination without having bugs.
> It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need to
> have a
On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote:
>
> If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU?
To allow fast reuse of objects, without going through call_rcu() and
reducing cache efficiency.
I believe this is mentioned in Documentation/RCU/rculist_nulls.txt
Hi all,
It turned out my cable was defectuous.
Keep up the great work and support, sorry for the noise on the list !
Cheers
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Mika Kuoppala writes:
> Chris Wilson writes:
>
>> A recent trend for cpufreq is to boost the CPU frequencies for
>> iowaiters, in particularly to benefit high frequency I/O. We do the same
>> and boost the GPU clocks to try and minimise time spent waiting for the
>> GPU. However, as the igfx
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9820_full =
== Summary - WARNING ==
Minor unknown changes coming
On Tue, Jul 31, 2018 at 10:49 AM Linus Torvalds
wrote:
>
> So the re-use might initialize the fields lazily, not necessarily using a
> ctor.
In particular, the pattern that nf_conntrack uses looks like it is safe.
If you have a well-defined refcount, and use "atomic_inc_not_zero()"
to guard
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9820 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
Okay!
Commit:
On Tue, 31 Jul 2018, Andrey Ryabinin wrote:
> Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache
> without constructor.
> I think it's nearly impossible to use that combination without having bugs.
> It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need
On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote:
>
> If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU?
.. because the object can be accessed (by RCU) after the refcount has
gone down to zero, and the thing has been released.
That's the whole and only point of
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
27c39427ec85 drm/dp: Add DP DSC DPCD receiver capability size define and
missing SHIFT
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
On 07/31/2018 07:04 PM, Andrey Ryabinin wrote:
>> Somewhat offtopic, but I can't understand how SLAB_TYPESAFE_BY_RCU
>> slabs can be useful without ctors or at least memset(0). Objects in
>> such slabs need to be type-stable, but I can't understand how it's
>> possible to establish type stability
== Series Details ==
Series: drm/i915/skl: distribute DDB based on panel resolution (rev2)
URL : https://patchwork.freedesktop.org/series/47428/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4598_full -> Patchwork_9819_full =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: drm/i915/skl: distribute DDB based on panel resolution (rev2)
URL : https://patchwork.freedesktop.org/series/47428/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4598 -> Patchwork_9819 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4597_full -> Patchwork_9818_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be enabled with 2 low resolution
displays.
Main contributing factor for DDB requirement is width of the display.
This patch
ddb_size is u16 so use same return type for intel_get_ddb_size
wrapper.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index
This series make changes to distribute DDB based on resolution of panel
instead of dividing equally among pipes.
Mahesh Kumar (2):
drm/i915: ddb_size is of u16 type
drm/i915/skl: distribute DDB based on panel resolution
drivers/gpu/drm/i915/intel_pm.c | 66
Hi,
On 7/28/2018 11:18 AM, Rodrigo Vivi wrote:
On Fri, Jul 27, 2018 at 11:40:14AM +0530, Kumar, Mahesh wrote:
Hi Matt,
On 7/27/2018 9:21 AM, Matt Turner wrote:
On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote:
Bspec: 4381
Do we know that these numbers are stable?
yes these numbers
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4597 -> Patchwork_9818 =
== Summary - SUCCESS ==
No regressions found.
External URL:
This will make it easier to test PSR1 on PSR2 capable eDP machines.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_psr.c | 27 ---
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git
Currently tests modify i915.enable_psr and then do a modeset cycle
to change PSR. We can write a value to i915_edp_psr_debug to force
a certain PSR mode without a modeset.
To retain compatibility with older userspace, we also still allow
the override through the module parameter, and add some
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Interactive RPS mode
-O:drivers/gpu/drm/i915/i915_irq.c:1265:22: warning: expression using
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
93827b4e697a drm/i915: Interactive RPS mode
-:27: ERROR:GIT_COMMIT_ID: Please use git commit description style
RPS provides a feedback loop where we use the load during the previous
evaluation interval to decide whether to up or down clock the GPU
frequency. Our responsiveness is split into 3 regimes, a high and low
plateau with the intent to keep the gpu clocked high to cover occasional
stalls under high
Chris Wilson writes:
> A recent trend for cpufreq is to boost the CPU frequencies for
> iowaiters, in particularly to benefit high frequency I/O. We do the same
> and boost the GPU clocks to try and minimise time spent waiting for the
> GPU. However, as the igfx and CPU share the same TDP,
Quoting Chris Wilson (2018-07-23 13:01:00)
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -784,6 +784,8 @@ struct intel_rps {
>
> int last_adj;
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
> + unsigned int interactive;
> + struct mutex power_lock;
Please describe
On Mon, Jul 30, 2018 at 04:57:11PM -0700, Anusha Srivatsa wrote:
> Add Support to load DMC on Icelake.
>
> Cc: Rodrigo Vivi
> Cc: Paulo Zanoni
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++
> 1 file changed, 7 insertions(+)
the firmware also needs to
On 30/07/18 17:43, Chris Wilson wrote:
In the aub trace utility, the context images are terminated with a
MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
Do the same for our protocontext image for completeness, and in passing
apply the magic bit for gen10 to mark the end
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>;
Hi Chris,
Thanks for review.
On 7/30/2018 9:08 PM, Chris Wilson wrote:
Quoting Mahesh Kumar (2018-07-30 15:12:02)
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be
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