== Series Details ==
Series: drm/i915/dp_mst: Fix enabling pipe clock for all streams
URL : https://patchwork.freedesktop.org/series/49025/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4750_full -> Patchwork_10063_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915: Rename full ppgtt configuration to be more generic
URL : https://patchwork.freedesktop.org/series/49021/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4750_full -> Patchwork_10062_full =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: drm/i915: Explicitly mark Global GTT address spaces
URL : https://patchwork.freedesktop.org/series/49018/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4749_full -> Patchwork_10061_full =
== Summary - SUCCESS ==
No regressions found.
==
== Series Details ==
Series: Load DMC v1.07 on Icelake (rev2)
URL : https://patchwork.freedesktop.org/series/48773/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4749_full -> Patchwork_10060_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha ; Navare, Manasi D
>
>Subject: [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling
On Fri, Aug 31, 2018 at 08:47:39PM +0300, Imre Deak wrote:
> commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
> inadvertently stopped enabling the pipe clock for any DP-MST stream
> after the first one. It also rearranged the pipe clock enabling wrt.
> initial MST payload
On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
> >
> > .has_full_48b_ppgtt ->
Tested on my T450s, fixes the regression with MST!
Consider this:
Tested-by: Lyude Paul
Reviewed-by: Lyude Paul
On Fri, 2018-08-31 at 20:47 +0300, Imre Deak wrote:
> commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
> inadvertently stopped enabling the pipe clock for
On Fri, Aug 31, 2018 at 08:47:39PM +0300, Imre Deak wrote:
> commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
> inadvertently stopped enabling the pipe clock for any DP-MST stream
> after the first one. It also rearranged the pipe clock enabling wrt.
> initial MST payload
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, August 6, 2018 12:41 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v3] drm/i915/dp: Configure Display stream splitter registers
>during DSC
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS
>infoframes
>
>DSC
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha ; Navare, Manasi D
>
>Subject: [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink
>
== Series Details ==
Series: drm/i915/dp_mst: Fix enabling pipe clock for all streams
URL : https://patchwork.freedesktop.org/series/49025/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4750 -> Patchwork_10063 =
== Summary - SUCCESS ==
No regressions found.
External
commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
inadvertently stopped enabling the pipe clock for any DP-MST stream
after the first one. It also rearranged the pipe clock enabling wrt.
initial MST payload allocation step (which may or may not be a
problem, but it's
On Fri, 31 Aug 2018 16:51:29 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
> >
> > .has_full_48b_ppgtt ->
On 31/08/2018 12:53, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
There are two issues with the current RPCS programming for Icelake:
Expansion of the slice count bitfield has been missed, as well as the
required programming workaround for the subslice count bitfield size
limitation.
1)
== Series Details ==
Series: drm/i915: Rename full ppgtt configuration to be more generic
URL : https://patchwork.freedesktop.org/series/49021/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4750 -> Patchwork_10062 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/icl: Fix context RPCS programming
URL : https://patchwork.freedesktop.org/series/49005/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4748_full -> Patchwork_10059_full =
== Summary - WARNING ==
Minor unknown changes coming with
On Fri, Aug 31, 2018 at 09:21:32AM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-29 01:35:31)
> > The 2 PCI IDs that are used for the command line overrid mechanism
> > were left defined. The rest can be gone and then we just use the kernel
> > defines.
> >
> > Signed-off-by:
Quoting Lucas De Marchi (2018-08-31 17:06:01)
> On Fri, Aug 31, 2018 at 09:16:23AM +0100, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2018-08-29 01:35:28)
> > > +bool intel_is_genx(unsigned int devid, int gen)
> > > +{
> > > + const struct pci_device *p,
> > > + *pend =
On Fri, Aug 31, 2018 at 09:16:23AM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-29 01:35:28)
> > +static const struct pci_device {
> > + uint16_t device;
> > + uint16_t gen;
> > +} pciids[] = {
>
> Add a comment here as well for the ordering requirement.
>
> /* Keep
Quoting Bob Paauwe (2018-08-31 16:47:04)
> For ppgtt, what we're really interested in is the number of page
> walk levels for each platform. Rename the device info fields to
> reflect this:
>
> .has_full_48b_ppgtt -> .has_full_4lvl_ppgtt
> .has_full_ppgtt -> .has_full_3lvl_ppgtt
>
> Also
Quoting Tvrtko Ursulin (2018-08-31 15:36:43)
> From: Tvrtko Ursulin
>
> So far we have been relying on vm->file pointer being NULL to declare
> something GGTT.
>
> This has the unfortunate consequence that the default kernel context is
> also declared GGTT and interferes with the following
For ppgtt, what we're really interested in is the number of page
walk levels for each platform. Rename the device info fields to
reflect this:
.has_full_48b_ppgtt -> .has_full_4lvl_ppgtt
.has_full_ppgtt -> .has_full_3lvl_ppgtt
Also add a new field, full_ppgtt_bits, that defines the actual
== Series Details ==
Series: drm/i915: Explicitly mark Global GTT address spaces
URL : https://patchwork.freedesktop.org/series/49018/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4749 -> Patchwork_10061 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On 2018-08-30 16:15, Lis, Tomasz wrote:
On 2018-08-30 02:08, Lionel Landwerlin wrote:
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some
Quoting Patchwork (2018-08-13 11:00:57)
> == Series Details ==
>
> Series: Reviewed perf cleanups
> URL : https://patchwork.freedesktop.org/series/48100/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4660_full -> Patchwork_9926_full =
>
> == Summary - SUCCESS ==
== Series Details ==
Series: drm/i915: Explicitly mark Global GTT address spaces
URL : https://patchwork.freedesktop.org/series/49018/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a97af16a4fee drm/i915: Explicitly mark Global GTT address spaces
-:47: WARNING:BOOL_BITFIELD:
== Series Details ==
Series: Load DMC v1.07 on Icelake (rev2)
URL : https://patchwork.freedesktop.org/series/48773/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4749 -> Patchwork_10060 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10060 need to
== Series Details ==
Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL : https://patchwork.freedesktop.org/series/46481/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4748_full -> Patchwork_10058_full =
== Summary - WARNING ==
Minor unknown
From: Tvrtko Ursulin
So far we have been relying on vm->file pointer being NULL to declare
something GGTT.
This has the unfortunate consequence that the default kernel context is
also declared GGTT and interferes with the following patch which wants to
instantiate VMA's and execute requests
On Thu, Aug 23, 2018 at 08:59:44AM +0530, Karthik B S wrote:
> Check added to skip the watermark workarounds intended for Gen10 and
> below platforms in Gen11.
This seems a bit ambiguous for me, could you please improve the commit
message a bit?
>
> Signed-off-by: Karthik B S
> ---
>
On Fri, Aug 31, 2018 at 01:18:53PM +0100, Chris Wilson wrote:
> In a multi-device system there is no guarantee that the fd being probed
> in intel_get_drm_devid() is the same as was opened earlier. Any cache
> may outlive the fd, so is frought with lifetime issues. The primary
> reason for caching
On Fri, Aug 31, 2018 at 12:39:05AM -0400, Jyoti Yadav wrote:
> From: Jyoti
>
> BIOS programs few of PWM related registers during initial boot.
> But during System suspend those registers are cleared.
> This test aim to check whether display programs those registers properly after
> system
On Fri, Aug 31, 2018 at 08:00:41AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
> URL : https://patchwork.freedesktop.org/series/48803/
> State : success
Pushed to -dinq thanks for the patch and review. I also added the
On Fri, Aug 31, 2018 at 04:30:31PM +0300, Imre Deak wrote:
> On Fri, Aug 31, 2018 at 02:08:13PM +0100, Chris Wilson wrote:
> > We want to test that provoking a vblank interrupt works correctly after
> > waking up from runtime-pm. First though, we must wait for the device to
> > enter
On Fri, Aug 31, 2018 at 02:08:13PM +0100, Chris Wilson wrote:
> We want to test that provoking a vblank interrupt works correctly after
> waking up from runtime-pm. First though, we must wait for the device to
> enter runtime-suspend. If the device cannot, e.g. we haven't enabled the
> DMC
We want to test that provoking a vblank interrupt works correctly after
waking up from runtime-pm. First though, we must wait for the device to
enter runtime-suspend. If the device cannot, e.g. we haven't enabled the
DMC firmware, the test should skip because our external requirements are
not met.
Quoting Tvrtko Ursulin (2018-08-30 17:23:43)
>
> On 30/08/2018 11:24, Chris Wilson wrote:
> > +static int steal_hw_id(struct drm_i915_private *i915)
> > +{
> > + struct i915_gem_context *ctx, *cn;
> > + LIST_HEAD(pinned);
> > + int id = -ENOSPC;
> > +
> > +
== Series Details ==
Series: drm/i915/icl: Fix context RPCS programming
URL : https://patchwork.freedesktop.org/series/49005/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4748 -> Patchwork_10059 =
== Summary - SUCCESS ==
No regressions found.
External URL:
In a multi-device system there is no guarantee that the fd being probed
in intel_get_drm_devid() is the same as was opened earlier. Any cache
may outlive the fd, so is frought with lifetime issues. The primary
reason for caching the devid was to avoid extra ioctls in the
dmesg/strace, but
From: Tvrtko Ursulin
There are two issues with the current RPCS programming for Icelake:
Expansion of the slice count bitfield has been missed, as well as the
required programming workaround for the subslice count bitfield size
limitation.
1)
Bitfield width for configuring the active slice
== Series Details ==
Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL : https://patchwork.freedesktop.org/series/46481/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4748 -> Patchwork_10058 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL : https://patchwork.freedesktop.org/series/46481/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/bxt: Decode memory bandwidth and parameters
== Series Details ==
Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL : https://patchwork.freedesktop.org/series/46481/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
441057f30f45 drm/i915/bxt: Decode memory bandwidth and parameters
-:162:
On Fri, Aug 31, 2018 at 07:24:48AM +, Lisovskiy, Stanislav wrote:
> On Thu, 2018-08-30 at 11:15 -0700, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-08-30 at 13:57 +0100, Lisovskiy, Stanislav wrote:
> > > On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
> > > >
> > > > On Wed,
Memory with 16GB dimms require an increase of 1us in level-0 latency.
This patch implements the same.
Bspec: 4381
changes since V1:
- s/memdev_info/dram_info
- make skl_is_16gb_dimm pure function
Changes since V2:
- make is_16gb_dimm more generic
- rebase
Changes since V3:
- Simplify
Found the bad commit:
https://cgit.freedesktop.org/drm-tip/commit/?id=afb2c4437daeed2d0c49e246ad1ad4def5d913cd
drm/i915/ddi: Push pipe clock enabling to encoders
Hope this helps.
If there is anything else I can provide plz let me know.
Regards
Dieter
On Tue, Aug 28, 2018 at 06:51:31PM +0200,
Op 24-08-18 om 11:32 schreef Mahesh Kumar:
> IPC may cause underflows if not used with dual channel symmetric
> memory configuration. Disable IPC for non symmetric configurations in
> affected platforms.
> Display WA #1141
>
> Changes Since V1:
> - Re-arrange the code.
> - update wrapper to
Op 24-08-18 om 11:32 schreef Mahesh Kumar:
> Memory with 16GB dimms require an increase of 1us in level-0 latency.
> This patch implements the same.
> Bspec: 4381
>
> changes since V1:
> - s/memdev_info/dram_info
> - make skl_is_16gb_dimm pure function
> Changes since V2:
> - make is_16gb_dimm
Quoting Chris Wilson (2018-08-31 10:09:00)
> Quoting Bartminski, Jakub (2018-08-31 10:01:57)
> > Looks good to me, thanks for the test case (btw maybe it's worth
> > mentioning in the commit message that the test fails without doing
> > gt.resume?)
>
> That would mean doing actual work to dig out
Quoting Bartminski, Jakub (2018-08-31 10:01:57)
> Looks good to me, thanks for the test case (btw maybe it's worth
> mentioning in the commit message that the test fails without doing
> gt.resume?)
That would mean doing actual work to dig out the original failing bug
reports!
-Chris
Looks good to me, thanks for the test case (btw maybe it's worth
mentioning in the commit message that the test fails without doing
gt.resume?)
Reviewed-by: Jakub Bartmiński
On Thu, 2018-08-30 at 14:48 +0100, Chris Wilson wrote:
> Although we cannot do a full system-level test of
Quoting Lucas De Marchi (2018-08-29 01:35:31)
> The 2 PCI IDs that are used for the command line overrid mechanism
> were left defined. The rest can be gone and then we just use the kernel
> defines.
>
> Signed-off-by: Lucas De Marchi
> ---
> intel/intel_chipset.c | 5 ++
>
Quoting Lucas De Marchi (2018-08-29 17:01:11)
> On Wed, Aug 29, 2018 at 11:32:35AM +0100, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2018-08-29 01:35:31)
> > > The 2 PCI IDs that are used for the command line overrid mechanism
> > > were left defined.
> >
> > What makes them so special? Why
Quoting Lucas De Marchi (2018-08-29 01:35:28)
> +static const struct pci_device {
> + uint16_t device;
> + uint16_t gen;
> +} pciids[] = {
Add a comment here as well for the ordering requirement.
/* Keep ids sorted by gen; latest gen first */
We're unlikely to notice a comment in
Quoting Chris Wilson (2018-08-30 14:48:06)
> Although we cannot do a full system-level test of suspend/hibernate from
> deep with the kernel selftests, we can exercise the GEM subsystem in
> isolation and simulate the external effects (such as losing stolen
> contents and trashing the register
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745_full -> Patchwork_10057_full =
== Summary - WARNING ==
Minor unknown
Quoting Ville Syrjälä (2018-08-22 13:35:52)
> On Fri, Aug 17, 2018 at 09:24:05AM +0100, Chris Wilson wrote:
> > The optimisation inherent in commit 6a2c4232ece1 ("drm/i915: Make the
> > physical object coherent with GTT") relies on that once we allocated a
> > cursor we would have coherent, zero
On Thu, 2018-08-30 at 11:15 -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-08-30 at 13:57 +0100, Lisovskiy, Stanislav wrote:
> > On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
> > >
> > > On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > > > On Wed, Aug 29, 2018 at
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745 -> Patchwork_10057 =
== Summary - SUCCESS ==
No regressions found.
This patch resolves the DMC FW loading issue.
Earlier DMC FW package have only one DMC FW for one stepping. But as such
there is no such restriction from Package side.
For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
So while reading the dmc_offset from package header, for
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