On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring D
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
v2: Changes (Jani N)
- Define _SHIFT and _MASK for bitfields
- Define va
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the
On 10/16/2018 6:36 PM, Jani Nikula wrote:
On Tue, 16 Oct 2018, Madhav Chauhan wrote:
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Will be needed in the future. No functional changes.
Agree, will be needing this while setting up DSI protocol timeouts for ICL.
Cc: Madhav Chauhan
Cc: Ville Syrja
