[Intel-gfx] ✗ Fi.CI.BAT: failure for Enabling the IGT for HDCP1.4 (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: Enabling the IGT for HDCP1.4 (rev4) URL : https://patchwork.freedesktop.org/series/51113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5019 -> Patchwork_10534 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10534 abso

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Enabling the IGT for HDCP1.4 (rev4)

2018-10-22 Thread C, Ramalingam
On 10/22/2018 10:47 PM, Patchwork wrote: == Series Details == Series: Enabling the IGT for HDCP1.4 (rev4) URL : https://patchwork.freedesktop.org/series/51113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10527 = == Summary - FAILURE == Serious unk

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2) URL : https://patchwork.freedesktop.org/series/50951/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5018_full -> Patchwork_10533_full = == Summary - WARNING ==

[Intel-gfx] [PULL] gvt-next-fixes for 4.20

2018-10-22 Thread Zhenyu Wang
Hi, Here's gvt-next-fixes for 4.20 with three changes. Mostly to fix possible arbitrary update on guest GGTT entry and with proper invalidate of old entry. Another one for one chicken reg mask fix. thanks -- The following changes since commit 835fe6d75d14c1513910ed7f5665127fee12acc8: firmware

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2) URL : https://patchwork.freedesktop.org/series/50951/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5018 -> Patchwork_10533 = == Summary - SUCCESS == No regre

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v14,1/2] drm: Add connector property to limit max bpc (rev2) URL : https://patchwork.freedesktop.org/series/50951/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: Add connector property to limit m

[Intel-gfx] ✓ Fi.CI.IGT: success for More watermarks improvements

2018-10-22 Thread Patchwork
== Series Details == Series: More watermarks improvements URL : https://patchwork.freedesktop.org/series/51086/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5018_full -> Patchwork_10532_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10532_ful

[Intel-gfx] [PATCH v15 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp

2018-10-22 Thread Manasi Navare
From: Radhakrishna Sripada Use the newly added "max bpc" connector property to limit pipe bpp. V3: Use drm_connector_state to access the "max bpc" property V4: Initialize the drm property, add suuport to DP(Ville) V5: Use the property in the connector and fix CI failure(Ville) V6: Use the core f

Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

2018-10-22 Thread Paulo Zanoni
Em Seg, 2018-10-22 às 17:06 -0700, Rodrigo Vivi escreveu: > On Mon, Oct 22, 2018 at 04:48:50PM -0700, Paulo Zanoni wrote: > > Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu: > > > Let's add a platform has_sagv instead of having a full > > > function that handle platform by platform. > > >

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

2018-10-22 Thread Rodrigo Vivi
On Mon, Oct 22, 2018 at 05:12:18PM -0700, Paulo Zanoni wrote: > Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu: > > On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote: > > > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > > > > On Tue, Oct 16, 2018 at 03:01:23PM -07

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

2018-10-22 Thread Paulo Zanoni
Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu: > On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote: > > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > > > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote: > > > > BSpec does not show these WAs as appli

[Intel-gfx] ✓ Fi.CI.BAT: success for More watermarks improvements

2018-10-22 Thread Patchwork
== Series Details == Series: More watermarks improvements URL : https://patchwork.freedesktop.org/series/51086/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5018 -> Patchwork_10532 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freed

Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

2018-10-22 Thread Rodrigo Vivi
On Mon, Oct 22, 2018 at 04:48:50PM -0700, Paulo Zanoni wrote: > Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu: > > Let's add a platform has_sagv instead of having a full > > function that handle platform by platform. > > > > The specially case for SKL for not controlled sagv > > is alre

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

2018-10-22 Thread Rodrigo Vivi
On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote: > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote: > > > BSpec does not show these WAs as applicable to GLK, and for CNL it > > > only shows them applicable for

Re: [Intel-gfx] [PATCH v5 13/28] drm/i915/dp: Compute DSC pipe config in atomic check

2018-10-22 Thread Srivatsa, Anusha
From: Navare, Manasi D Sent: Friday, October 05, 2018 4:22 PM To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org Cc: Navare, Manasi D; Jani Nikula; Ville Syrjala; Srivatsa, Anusha; Singh, Gaurav K Subject: [PATCH v5 13/28] drm/i915/dp: Co

Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

2018-10-22 Thread Paulo Zanoni
Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu: > Let's add a platform has_sagv instead of having a full > function that handle platform by platform. > > The specially case for SKL for not controlled sagv > is already taken care inside intel_enable_sagv, so there's > no need to duplicate

Re: [Intel-gfx] [PATCH v5 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC

2018-10-22 Thread Srivatsa, Anusha
From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.nav...@intel.com] Sent: Friday, October 05, 2018 4:22 PM To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v5 17/2

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

2018-10-22 Thread Paulo Zanoni
Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote: > > BSpec does not show these WAs as applicable to GLK, and for CNL it > > only shows them applicable for a super early pre-production > > stepping > > we shouldn't be caring a

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915/guc: rename __create/destroy_doorbell

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [CI,1/6] drm/i915/guc: rename __create/destroy_doorbell URL : https://patchwork.freedesktop.org/series/51353/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5abac044073e drm/i915/guc: rename __create/destroy_doorbell 1e3c4f24671

[Intel-gfx] [CI 4/6] drm/i915/guc: fix comment about fallback to execlists

2018-10-22 Thread Daniele Ceraolo Spurio
We stopped supporting fallback to execlists in commit 121981fafe69 (drm/i915/guc: Combine enable_guc_loading|submission modparams). We do instead reset and retry in some cases, depending on the workarounds required by the platform. Cc: Michal Wajdeczko Cc: Chris Wilson Signed-off-by: Daniele Cer

[Intel-gfx] [CI 5/6] drm/i915/guc: remove unneeded goto from selftest

2018-10-22 Thread Daniele Ceraolo Spurio
commit e346a991f42c ("drm/i915/guc: drop negative doorbell alloc selftest") removed the negative case from the selftest and left no code between the goto from the positive case of the test and the label itself, so we can get rid of it. Reported-by: Lucas De Marchi Cc: Lucas De Marchi Cc: Michal

[Intel-gfx] [CI 1/6] drm/i915/guc: rename __create/destroy_doorbell

2018-10-22 Thread Daniele Ceraolo Spurio
The 2 functions don't create or destroy anything, they just update the doorbell state in memory. Use init and fini instead for clarity. Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 12 ++-- 1

[Intel-gfx] [CI 6/6] HAX enable GuC for CI

2018-10-22 Thread Daniele Ceraolo Spurio
From: Michal Wajdeczko Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 7e56c516c815..c681537bcb92 100644 --- a/drivers/gpu/dr

[Intel-gfx] [CI 2/6] drm/i915/guc: reserve the doorbell before selecting the cacheline

2018-10-22 Thread Daniele Ceraolo Spurio
Cacheline selection is only needed if we actually manage to reserve a doorbell. Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/d

[Intel-gfx] [CI 3/6] drm/i915/guc: doorbell checking cleanup

2018-10-22 Thread Daniele Ceraolo Spurio
A collection of very small cleanups/improvements around doorbell checking that do not deserve their own patch: - Move doorbell-related HW defs to intel_guc_reg.h - use GUC_NUM_DOORBELLS instead of GUC_DOORBELL_INVALID where appropriate - do not stop on error in guc_verify_doorbells - do not p

[Intel-gfx] [RFC v2] GuC firmware versioning change

2018-10-22 Thread Jeff McGee
See https://lists.freedesktop.org/archives/intel-gfx/2018-October/178452.html for RFC v1 and the helpful feedback incorporated into this v2. The GuC firmware team is proposing a change to the firmware versioning scheme. The goal is to more accurately track the firmware interface to help users mana

Re: [Intel-gfx] [PATCH 07/11] drm/i915: move ddb_blocks to be a watermark parameter

2018-10-22 Thread Paulo Zanoni
Em Qui, 2018-10-18 às 16:41 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:29PM -0700, Paulo Zanoni wrote: > > The goal of struct skl_wm_params is to cache every watermark > > parameter so the other functions can just use them without worrying > > about the appropriate place to fetc

Re: [Intel-gfx] [PATCH v5 16/28] drm/i915/dsc: Define & Compute VESA DSC params

2018-10-22 Thread Srivatsa, Anusha
From: Navare, Manasi D Sent: Friday, October 05, 2018 4:22 PM To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org Cc: Singh, Gaurav K; Jani Nikula; Ville Syrjala; Srivatsa, Anusha; Navare, Manasi D Subject: [PATCH v5 16/28] drm/i915/dsc: D

Re: [Intel-gfx] [PATCH 08/11] drm/i915: reorganize the error message for invalid watermarks

2018-10-22 Thread Paulo Zanoni
Em Qui, 2018-10-18 às 16:55 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote: > > Print a more generic "failed to compute watermark levels" whenever > > any > > of skl_compute_wm_levels() fail, and print only the specific error > > message for the specif

Re: [Intel-gfx] [PATCH v5 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants

2018-10-22 Thread Srivatsa, Anusha
From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.nav...@intel.com] Sent: Friday, October 05, 2018 4:22 PM To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v5 15/2

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: ddi_clock_get sort platforms newer-to-older.

2018-10-22 Thread Rodrigo Vivi
On Mon, Oct 22, 2018 at 09:26:42PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/5] drm/i915: ddi_clock_get sort platforms > newer-to-older. > URL : https://patchwork.freedesktop.org/series/51340/ > State : success > > == Summary == > > = CI Bug Log - chan

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: ddi_clock_get sort platforms newer-to-older.

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/5] drm/i915: ddi_clock_get sort platforms newer-to-older. URL : https://patchwork.freedesktop.org/series/51340/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10529_full = == Summary - SUCCESS ==

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Ensure intel_engine_init_execlist() builds with Clang

2018-10-22 Thread Nick Desaulniers
On Mon, Oct 22, 2018 at 2:10 PM Nick Desaulniers wrote: > > On Wed, Oct 17, 2018 at 12:25 AM Jani Nikula wrote: > > > > On Tue, 16 Oct 2018, Nick Desaulniers wrote: > > > On Tue, Oct 16, 2018 at 8:35 AM Stephen Boyd wrote: > > >> > > >> Quoting Jani Nikula (2018-10-16 05:29:38) > > >> > Clang b

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Ensure intel_engine_init_execlist() builds with Clang

2018-10-22 Thread Nick Desaulniers
On Wed, Oct 17, 2018 at 12:25 AM Jani Nikula wrote: > > On Tue, 16 Oct 2018, Nick Desaulniers wrote: > > On Tue, Oct 16, 2018 at 8:35 AM Stephen Boyd wrote: > >> > >> Quoting Jani Nikula (2018-10-16 05:29:38) > >> > Clang build with UBSAN enabled leads to the following build error: > > > > I'm o

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Simplify has_sagv (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Simplify has_sagv (rev2) URL : https://patchwork.freedesktop.org/series/51266/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10528_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_1

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4) URL : https://patchwork.freedesktop.org/series/51274/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10526_full = == Summary -

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout

2018-10-22 Thread Hans de Goede
Hi, On 22-10-18 16:19, Ville Syrjala wrote: From: Ville Syrjälä Let's make sure the DSI port is actually on before we go poking at the plane register to determine which way it's rotated. Otherwise we could be looking at a plane that is feeding a HDMI port for instance. And in order to read th

Re: [Intel-gfx] [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook

2018-10-22 Thread Manasi Navare
On Fri, Oct 19, 2018 at 05:52:14PM -0700, Souza, Jose wrote: > On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote: > > In case of Legacy DP connector on TypeC port, the > > flex IO DPMLE register is set to number of lanes configured > > by the display driver which will be programmed into DDI_BU

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits

2018-10-22 Thread Manasi Navare
On Fri, Oct 19, 2018 at 02:33:35PM -0700, Srivatsa, Anusha wrote: > > > From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi > Navare [manasi.d.nav...@intel.com] > Sent: Thursday, October 18, 2018 3:16 PM > To: intel-gfx@lists.free

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen11: Add support for the NV12 format. (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/gen11: Add support for the NV12 format. (rev4) URL : https://patchwork.freedesktop.org/series/51178/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10524_full = == Summary - WARNING == Minor unknown changes comi

Re: [Intel-gfx] [PATCH v5 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink

2018-10-22 Thread Manasi Navare
On Fri, Oct 05, 2018 at 04:22:56PM -0700, Manasi Navare wrote: > From: Gaurav K Singh > > This patch enables decompression support in sink device > before link training and disables the same during the > DDI disabling. > > v2:(From Manasi) > * Change the enable/disable function to take crtc_stat

Re: [Intel-gfx] [v2 5/6] i915/dp/fec: Configure the Forward Error Correction bits.

2018-10-22 Thread Srivatsa, Anusha
>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Monday, October 22, 2018 11:26 AM >To: Srivatsa, Anusha >Cc: Navare, Manasi D ; intel- >g...@lists.freedesktop.org; Singh, Gaurav K ; Jani >Nikula >Subject: Re: [v2 5/6] i915/dp/fec: Configure the For

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Consolidate cdclk hooks. (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Consolidate cdclk hooks. (rev2) URL : https://patchwork.freedesktop.org/series/51271/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10530 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_1053

Re: [Intel-gfx] [v2 5/6] i915/dp/fec: Configure the Forward Error Correction bits.

2018-10-22 Thread Ville Syrjälä
On Mon, Oct 22, 2018 at 06:04:28PM +, Srivatsa, Anusha wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, October 19, 2018 4:12 PM > >To: Navare, Manasi D > >Cc: Srivatsa, Anusha ; intel- > >g...@lists.freedesktop.org; Sing

Re: [Intel-gfx] [v2 5/6] i915/dp/fec: Configure the Forward Error Correction bits.

2018-10-22 Thread Manasi Navare
On Mon, Oct 22, 2018 at 11:04:28AM -0700, Srivatsa, Anusha wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, October 19, 2018 4:12 PM > >To: Navare, Manasi D > >Cc: Srivatsa, Anusha ; intel- > >g...@lists.freedesktop.org; Sing

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: remove unneeded goto from selftest

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/guc: remove unneeded goto from selftest URL : https://patchwork.freedesktop.org/series/51281/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10520_full = == Summary - FAILURE == Serious unknown changes coming wi

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version

2018-10-22 Thread Daniele Ceraolo Spurio
On 22/10/18 10:13, Tomasz Lis wrote: For Icelake and above, MOCS table for each platform is published within bspec. The table is versioned, and new entries are assigned a version number. Existing entries do not change and their version is constant. This introduces a parameter which allows gett

Re: [Intel-gfx] [v2 5/6] i915/dp/fec: Configure the Forward Error Correction bits.

2018-10-22 Thread Srivatsa, Anusha
>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Friday, October 19, 2018 4:12 PM >To: Navare, Manasi D >Cc: Srivatsa, Anusha ; intel- >g...@lists.freedesktop.org; Singh, Gaurav K ; Jani >Nikula >Subject: Re: [v2 5/6] i915/dp/fec: Configure the Forw

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: ddi_clock_get sort platforms newer-to-older.

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/5] drm/i915: ddi_clock_get sort platforms newer-to-older. URL : https://patchwork.freedesktop.org/series/51340/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10529 = == Summary - SUCCESS == No regres

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake

2018-10-22 Thread Daniele Ceraolo Spurio
On 22/10/18 10:13, Tomasz Lis wrote: The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The pa

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Simplify has_sagv (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Simplify has_sagv (rev2) URL : https://patchwork.freedesktop.org/series/51266/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10528 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Consolidate cdclk hooks.

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Consolidate cdclk hooks. URL : https://patchwork.freedesktop.org/series/51271/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10519_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_105

[Intel-gfx] [PATCH] drm/i915: Consolidate cdclk hooks.

2018-10-22 Thread Rodrigo Vivi
We don't need 2 different blocks. Specially with on in ordered older-to-newer and the other one newer-to-older. Let's start always using newer-to-older order when it makes sense. v2: Accept all good suggestions from Ville: - Remove \n since it is under 80 cols now - Use get/set/calc order

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Simplify has_sagv (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Simplify has_sagv (rev2) URL : https://patchwork.freedesktop.org/series/51266/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Simplify has_sagv -drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warn

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enabling the IGT for HDCP1.4 (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: Enabling the IGT for HDCP1.4 (rev4) URL : https://patchwork.freedesktop.org/series/51113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10527 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10527 abso

[Intel-gfx] [PATCH 5/5] drm/i915: uncore_fw_domains_init sort platforms newer-to-older

2018-10-22 Thread Rodrigo Vivi
No functional change. Just sorting this "if" statement from newer to older platform. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_un

[Intel-gfx] [PATCH 4/5] drm/i915: power_domains_init sort platforms newer-to-older

2018-10-22 Thread Rodrigo Vivi
No functional change. Just sorting this "if" block from newer to older platform. v2: Fix few positions (Ville) Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_runtime_pm.c | 17 - 1 file changed, 8 insertions(+), 9 deletio

[Intel-gfx] [PATCH 3/5] drm/i915: digital_port_connected sort platforms newer-to-older

2018-10-22 Thread Rodrigo Vivi
Just sorting this "if" block from newer to older platform. The main difference here is the addition of a missing case with return false that should never occur. And if it occurs it is better than to raise a warn than use the icl one. The gen >= 11 was already present in the previous logic, althou

[Intel-gfx] [PATCH 1/5] drm/i915: ddi_clock_get sort platforms newer-to-older.

2018-10-22 Thread Rodrigo Vivi
No functional change. Just sorting this "if" block from newer to older platform. v2: Invert gen9_bc and gen9_lp (Ville) Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 16 1 file changed, 8 insertions(+), 8 deleti

[Intel-gfx] [PATCH 2/5] drm/i915: compute_min_voltage_level sort platforms newer-to-older

2018-10-22 Thread Rodrigo Vivi
No functional change. Just sorting this "if" block from newer to older platform. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi

[Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake

2018-10-22 Thread Tomasz Lis
The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Meaning

[Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version

2018-10-22 Thread Tomasz Lis
For Icelake and above, MOCS table for each platform is published within bspec. The table is versioned, and new entries are assigned a version number. Existing entries do not change and their version is constant. This introduces a parameter which allows getting max version number of the MOCS entrie

[Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

2018-10-22 Thread Rodrigo Vivi
Let's add a platform has_sagv instead of having a full function that handle platform by platform. The specially case for SKL for not controlled sagv is already taken care inside intel_enable_sagv, so there's no need to duplicate the check here. v2: Go one step further and remove skl special case.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enabling the IGT for HDCP1.4 (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: Enabling the IGT for HDCP1.4 (rev4) URL : https://patchwork.freedesktop.org/series/51113/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1698e218c4ae drm/i915: Pullout the bksv read and validation e82aaa2cb827 drm/i915: hdcp_check_link only on CP_IRQ

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4) URL : https://patchwork.freedesktop.org/series/51274/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10526 = == Summary - SUCCESS =

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify has_sagv

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Simplify has_sagv URL : https://patchwork.freedesktop.org/series/51266/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017_full -> Patchwork_10517_full = == Summary - SUCCESS == No regressions found. == Known issues == Here

Re: [Intel-gfx] [PATCH xf86-video-intel 4/4] sna/video/textured: Disable textured Xv for depth 8

2018-10-22 Thread Chris Wilson
Quoting Ville Syrjala (2018-10-22 14:59:29) > From: Ville Syrjälä > > We can't output color index formats with the render engine, > so let's disable the textured Xv adaptor for depth 8. Fair enough, there's probably lots more breakage around the place. > Signed-off-by: Ville Syrjälä Reviewed-

Re: [Intel-gfx] [PATCH xf86-video-intel 3/4] sna/video/textured: Enable textured Xv wih depth 30

2018-10-22 Thread Chris Wilson
Quoting Ville Syrjala (2018-10-22 14:59:28) > From: Ville Syrjälä > > Texured Xv works just fine with depth 30. Allow it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org htt

Re: [Intel-gfx] [PATCH xf86-video-intel 2/4] sna/video/sprite: Allow sprite Xv with depth 8 and depth 30

2018-10-22 Thread Chris Wilson
Quoting Ville Syrjala (2018-10-22 14:59:27) > From: Ville Syrjälä > > With the colorkey setup fixed the sprite Xv adaptor works just > fine with depth 30. > > With depth 8 there is one remaining problem with the usage of > the LUT for gamma vs. C8, but that is purely a kernel issue. > > Let's a

Re: [Intel-gfx] [PATCH xf86-video-intel 1/4] sna/video/sprite: Fix colorkey setup for depth != 24

2018-10-22 Thread Chris Wilson
Quoting Ville Syrjala (2018-10-22 14:59:26) > From: Ville Syrjälä > > Set up the colorkey correctly for depth != 24. For 8bpc we > need to replicate the same key value into each channel, for > depth 15/16 we need to mask off the unused low bits in each > channel, and for depth 30 we just use the

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout (rev4) URL : https://patchwork.freedesktop.org/series/51274/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix the VLV/CHV

Re: [Intel-gfx] [PATCH] drm/i915: Ensure proper HDA suspend/resume ordering with a device link

2018-10-22 Thread Ville Syrjälä
On Thu, Oct 18, 2018 at 05:25:58PM +0300, Imre Deak wrote: > In order to ensure that our system suspend and resume callbacks are > called in the correct order wrt. those of the HDA driver add a device > link to the HDA driver during audio component binding time. With i915 as > the supplier and HDA

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enabling the IGT for HDCP1.4 (rev3)

2018-10-22 Thread Patchwork
== Series Details == Series: Enabling the IGT for HDCP1.4 (rev3) URL : https://patchwork.freedesktop.org/series/51113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10525 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10525 abso

[Intel-gfx] [PATCH v4 2/3] drm/i915: hdcp_check_link only on CP_IRQ

2018-10-22 Thread Ramalingam C
HDCP check link is invoked only on CP_IRQ detection, instead of all short pulses. v3: No Changes. v4: Added sean in cc and collected the reviewed-by received. v5: No Change. v6: No Change. v7: No Change. v8: Rebased. Signed-off-by: Ramalingam C cc: Sean Paul Reviewed-by: Uma Shankar

[Intel-gfx] [PATCH v4 1/3] drm/i915: Pullout the bksv read and validation

2018-10-22 Thread Ramalingam C
For reusability purpose, this patch implements the hdcp1.4 bksv's read and validation as a functions. For detecting the HDMI panel's HDCP capability this fucntions will be used. v2: Rebased. v3: No Changes. v4: inline tag is removed with modified error msg. v5: No Changes. v6: No Change

[Intel-gfx] [PATCH v4 3/3] drm/i915/debugfs: hdcp capability of a sink

2018-10-22 Thread Ramalingam C
Add a debugfs entry for providing the hdcp capabilities of the sink connected to the HDCP capable connectors. v2: Squashed the sink's hdcp capability into this patch. [Daniel] Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/i915_debugfs.c | 29 + drivers/gpu/d

[Intel-gfx] [PATCH v4 0/3] Enabling the IGT for HDCP1.4

2018-10-22 Thread Ramalingam C
Adding a debugfs entry for detecting the valid HDCP sinks to perform kms_content_protection. In case of dummy HDMI/DP sinks(EDID whisperers without any parsers) IGT will skip the HDCP test on that connector instead of failing it. Hence false alarm are avoided. For serving above purpose this serie

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enabling the IGT for HDCP1.4 (rev3)

2018-10-22 Thread Patchwork
== Series Details == Series: Enabling the IGT for HDCP1.4 (rev3) URL : https://patchwork.freedesktop.org/series/51113/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7697634d8e93 drm/i915: Pullout the bksv read and validation 0810c07faa41 drm/i915: Detect the hdcp capability of

Re: [Intel-gfx] [PATCH] drm/i915/gen11: Expose planar format support on gen11, v2.

2018-10-22 Thread Ville Syrjälä
On Mon, Oct 22, 2018 at 03:45:14PM +0200, Maarten Lankhorst wrote: > Now that we implemented support for planar formats on gen11, we can > finally advertise it. > > Changes since v1: > - Re-add change to skl_plane_has_planar(), was lost in rebase noise. > > Signed-off-by: Maarten Lankhorst > ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen11: Add support for the NV12 format. (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/gen11: Add support for the NV12 format. (rev4) URL : https://patchwork.freedesktop.org/series/51178/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10524 = == Summary - SUCCESS == No regressions found. External UR

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Avoid initializing framebuffer without pipes

2018-10-22 Thread Chris Wilson
Quoting Jani Nikula (2018-10-22 15:09:06) > On Fri, 19 Oct 2018, Chris Wilson wrote: > > Quoting Mika Kuoppala (2018-10-19 13:30:37) > >> If we try to initialize a framebuffer without pipes, we get oops > >> as we fail to get valid crtc for a PIPE A, on trying to find > >> pitch limits. This is ea

Re: [Intel-gfx] [PATCH] drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.

2018-10-22 Thread Ville Syrjälä
On Mon, Oct 22, 2018 at 03:51:52PM +0200, Maarten Lankhorst wrote: > To make NV12 working on icl, we need to update 2 planes simultaneously. > I've chosen to do this in the CRTC step after plane validation is done, > so we know what planes are (in)visible. The linked Y plane will get > updated in i

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gen11: Add support for the NV12 format. (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/gen11: Add support for the NV12 format. (rev4) URL : https://patchwork.freedesktop.org/series/51178/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix unsigned overflow when calculating total data rate,

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Make number of ddi ports explicit.

2018-10-22 Thread Ville Syrjälä
On Fri, Oct 19, 2018 at 01:19:43PM -0700, Rodrigo Vivi wrote: > Instead of a simple bool that shows if we have ddi ports > or not, let's highlight the number of ddi ports. > > So we can use this information to determine the code > path instead of using platforms codenames. > > Signed-off-by: Rodr

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen11: Add support for the NV12 format. (rev4)

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/gen11: Add support for the NV12 format. (rev4) URL : https://patchwork.freedesktop.org/series/51178/ State : warning == Summary == $ dim checkpatch origin/drm-tip e63515ae7751 drm/i915: Fix unsigned overflow when calculating total data rate, v2. -:43: CHE

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2) URL : https://patchwork.freedesktop.org/series/51275/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10522 = == Summary - FAILURE == Serious unkn

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable Y210, Y212, Y216 formats for ICL (rev3)

2018-10-22 Thread Patchwork
== Series Details == Series: Enable Y210, Y212, Y216 formats for ICL (rev3) URL : https://patchwork.freedesktop.org/series/48729/ State : failure == Summary == Applying: drm: Add Y210, Y212, Y216 format definitions and fourcc Applying: drm/i915/icl: Add Y210, Y212, Y216 plane control definitio

Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/debugfs: hdcp capability of a sink

2018-10-22 Thread Daniel Vetter
On Mon, Oct 22, 2018 at 07:46:05PM +0530, Ramalingam C wrote: > Add a debugfs entry for providing the hdcp capabilities of the sink > connected to the HDCP capable connectors. > > Signed-off-by: Ramalingam C > --- > drivers/gpu/drm/i915/i915_debugfs.c | 29 + > driver

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: hdcp_check_link only on CP_IRQ

2018-10-22 Thread Daniel Vetter
On Mon, Oct 22, 2018 at 07:46:04PM +0530, Ramalingam C wrote: > HDCP check link is invoked only on CP_IRQ detection, instead of all > short pulses. > > v3: > No Changes. > v4: > Added sean in cc and collected the reviewed-by received. > v5: > No Change. > v6: > No Change. > v7: > No Chan

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Detect the hdcp capability of sink and src

2018-10-22 Thread Daniel Vetter
On Mon, Oct 22, 2018 at 07:46:03PM +0530, Ramalingam C wrote: > Implements a function to detect the sink and src's hdcp1.4 > capabilities. > > v2: > const qualifier is maintained at init. > > Signed-off-by: Ramalingam C > --- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Define MOCS table for Icelake

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/icl: Define MOCS table for Icelake URL : https://patchwork.freedesktop.org/series/51258/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5016_full -> Patchwork_10516_full = == Summary - WARNING == Minor unknown changes coming with Patc

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Pullout the bksv read and validation

2018-10-22 Thread Daniel Vetter
On Mon, Oct 22, 2018 at 07:46:02PM +0530, Ramalingam C wrote: > For reusability purpose, this patch implements the hdcp1.4 bksv's > read and validation as a functions. > > For detecting the HDMI panel's HDCP capability this fucntions will be > used. > > v2: > Rebased. > v3: > No Changes. > v4

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2) URL : https://patchwork.freedesktop.org/series/51275/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Make number of ddi ports explici

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915: Make number of ddi ports explicit. (rev2) URL : https://patchwork.freedesktop.org/series/51275/ State : warning == Summary == $ dim checkpatch origin/drm-tip bafa4e7b6635 drm/i915: Make number of ddi ports explicit. a43c4174c54

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: remove unneeded goto from selftest

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915/guc: remove unneeded goto from selftest URL : https://patchwork.freedesktop.org/series/51281/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10520 = == Summary - SUCCESS == No regressions found. External URL: htt

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2)

2018-10-22 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2) URL : https://patchwork.freedesktop.org/series/51223/ State : failure == Summary == Applying: drm/i915/icl: Fix the macros for DFLEXDPMLE register bits error: corrupt patch

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Determine DSI panel orientation from VBT

2018-10-22 Thread Jani Nikula
On Mon, 22 Oct 2018, Ville Syrjala wrote: > From: Ville Syrjälä > > VBT appears to have two (or possibly three) ways to indicate the panel > rotation. The first is in the MIPI config block, but that apparenly > usually (maybe always?) indicates 0 degrees despite the actual panel > orientation. Th

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Consolidate cdclk hooks.

2018-10-22 Thread Patchwork
== Series Details == Series: drm/i915: Consolidate cdclk hooks. URL : https://patchwork.freedesktop.org/series/51271/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5017 -> Patchwork_10519 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork

Re: [Intel-gfx] [PATCH] drm/i915/lspcon: Fix Parade LSPCON scrambling fail

2018-10-22 Thread Ville Syrjälä
On Tue, Oct 16, 2018 at 08:22:26AM +0530, Sharma, Shashank wrote: > Regards > > Shashank > > > On 10/13/2018 12:47 AM, Ville Syrjälä wrote: > > On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote: > >> Regards > >> > >> Shashank > >> > >> > >> On 10/13/2018 12:08 AM, Ville Syrjala w

[Intel-gfx] [PATCH v2 3/3] drm/i915: Remove the hardware readout path for DSI panel orientation

2018-10-22 Thread Ville Syrjala
From: Ville Syrjälä Now that we can actually grab the rotation data from the VBT, maybe we can get rid of the hardware readout path? My VLV FFRD is still happy. v2: Rebase due to moving code to intel_dsi.c Cc: Hans de Goede Acked-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/

  1   2   >