On 11/1/2018 9:03 PM, Jani Nikula wrote:
Allocate DSI host structure for each DSI port available on gen11 and
register them with DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this.
Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI
exported f
On 11/1/2018 9:03 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v3:
* C
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc para
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
C
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_tran
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI er
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of inte
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
This patch series addresses review comments on previous DSC series:
https://patchwork.freedesktop.org/series/47514/
Gaurav K Singh (3):
drm/i915/dsc: Define & Compute VESA DSC params
drm/i915/dsc: Compute Rate Control parameters for DSC
drm/i915/dp: Enable/Disable DSC in DP Sink
Manasi Nav
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Na
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
C
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Mana
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, November 1, 2018 9:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chauhan, Madhav ;
> ville.syrj...@linux.intel.com; Kulkarni, Vandita ;
> Lisovskiy, Stanislav ; Nikula, Jani
>
> Subject: [PATCH v9 04/15] drm/i915/icl: Add get
== Series Details ==
Series: Forward Error Correction (rev5)
URL : https://patchwork.freedesktop.org/series/47848/
State : failure
== Summary ==
Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Applying: drm/dp/fec: DRM helper for Forward Error Correction
Applying: i915/dp/fec: Add f
== Series Details ==
Series: series starting with [CI,1/2] i915/dp/fec: Cache the FEC_CAPABLE DPCD
register
URL : https://patchwork.freedesktop.org/series/51913/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5071_full -> Patchwork_10702_full =
== Summary - SUCCESS ==
No
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, be
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3: Print FEC CAPABILITY value. (Manasi)
Suggested-by: J
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of
Pushed to the dinq, thanks for the patch.
Manasi
On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote:
> On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
> > This patch fixes the naming of the registers:
> >
> > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
> >
> > And also fix the h
== Series Details ==
Series: series starting with [CI,1/2] i915/dp/fec: Cache the FEC_CAPABLE DPCD
register
URL : https://patchwork.freedesktop.org/series/51913/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5071 -> Patchwork_10702 =
== Summary - WARNING ==
Minor unknow
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3: Print FEC CAPABILITY value. (Manasi)
Suggested-by: J
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names (rev2)
URL : https://patchwork.freedesktop.org/series/51901/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070_full -> Patchwork_10700_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation. (rev4)
URL : https://patchwork.freedesktop.org/series/51566/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070_full -> Patchwork_10698_full =
== Summary - SUCCESS ==
No regressions found.
On Thu, Nov 01, 2018 at 05:34:14PM -0700, Rodrigo Vivi wrote:
> On Fri, Nov 02, 2018 at 01:52:20AM +0200, Imre Deak wrote:
> > On Thu, Nov 01, 2018 at 12:33:04PM -0700, Rodrigo Vivi wrote:
> > > On Tue, Oct 30, 2018 at 03:27:35PM -0700, Rodrigo Vivi wrote:
> > > > On Tue, Oct 30, 2018 at 01:45:02AM
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev8)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069_full -> Patchwork_10697_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues =
== Series Details ==
Series: series starting with [CI,1/2] i915/dp/fec: Cache the FEC_CAPABLE DPCD
register
URL : https://patchwork.freedesktop.org/series/51906/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] d
On Fri, Nov 02, 2018 at 01:52:20AM +0200, Imre Deak wrote:
> On Thu, Nov 01, 2018 at 12:33:04PM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 30, 2018 at 03:27:35PM -0700, Rodrigo Vivi wrote:
> > > On Tue, Oct 30, 2018 at 01:45:02AM -0700, Radhakrishna Sripada wrote:
> > > > Display WA_1405510057 asks
On Thu, Nov 01, 2018 at 04:54:14PM -0700, Manasi Navare wrote:
> Thanks for reviewing this patch. Find some comments inline
>
> On Thu, Nov 01, 2018 at 06:46:28PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> > > According to Display Stream compre
On Thu, Nov 01, 2018 at 11:15:07PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev4)
> URL : https://patchwork.freedesktop.org/series/51765/
> State : success
Pushed to -dinq, thanks for the reviews.
>
> == Summary ==
>
> = CI Bug
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3: Print FEC CAPABILITY value. (Manasi)
Suggested-by: J
== Series Details ==
Series: series starting with [1/3] drm/atomic: Use explicit old crtc state in
drm_atomic_add_affected_planes()
URL : https://patchwork.freedesktop.org/series/51894/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069_full -> Patchwork_10696_full =
== Su
On Thu, Nov 01, 2018 at 12:33:04PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 30, 2018 at 03:27:35PM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 30, 2018 at 01:45:02AM -0700, Radhakrishna Sripada wrote:
> > > Display WA_1405510057 asks to not enable YUV 420 HDMI
> > > 10bpc when horizontal blank size
Thanks for reviewing this patch. Find some comments inline
On Thu, Nov 01, 2018 at 06:46:28PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> > According to Display Stream compression spec 1.2, the picture
> > parameter set metadata is sent from sourc
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev4)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069_full -> Patchwork_10695_full =
== Summary - WARNING ==
Minor unknown changes coming w
On Thu, Nov 01, 2018 at 04:02:48PM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Navare, Manasi D
> >Sent: Thursday, November 1, 2018 3:31 PM
> >To: Srivatsa, Anusha
> >Cc: intel-gfx@lists.freedesktop.org; Jani Nikula
> >;
> >Ville Syrjala
> >Subject: Re: [v4 1/7] i
>-Original Message-
>From: Navare, Manasi D
>Sent: Thursday, November 1, 2018 3:31 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Jani Nikula ;
>Ville Syrjala
>Subject: Re: [v4 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
>
>On Tue, Oct 30, 2018 at 05:45:11PM -0
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names (rev2)
URL : https://patchwork.freedesktop.org/series/51901/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070 -> Patchwork_10700 =
== Summary - SUCCESS ==
No regressions found.
External URL:
http
On Tue, Oct 30, 2018 at 05:45:11PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> v2: Avoid using memset and array for a single
>
>-Original Message-
>From: Srivatsa, Anusha
>Sent: Tuesday, October 30, 2018 5:45 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Srivatsa, Anusha ; Singh, Gaurav K
>; Jani Nikula ; Ville
>Syrjala ; Navare, Manasi D
>
>Subject: [v4 5/7] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
>
>If t
On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
> This patch fixes the naming of the registers:
>
> s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>
> And also fix the hex values to lower case, to match
> rest of the definitions.
>
> Manasi noticed this with the patch that was merged.
>
> v2:
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names
URL : https://patchwork.freedesktop.org/series/51901/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070 -> Patchwork_10699 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://pat
This patch fixes the naming of the registers:
s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
And also fix the hex values to lower case, to match
rest of the definitions.
Manasi noticed this with the patch that was merged.
v2: fix "Fixes" tag.
Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
Sugges
On Thu, Nov 01, 2018 at 06:42:17PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:20PM -0700, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names
URL : https://patchwork.freedesktop.org/series/51901/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4ffedc790c0f drm/i915/icl: Fix DSS_CTL register names
-:15: ERROR:GIT_COMMIT_ID: Please use git commit descr
On Thu, Nov 01, 2018 at 02:06:43PM -0700, Anusha Srivatsa wrote:
> This patch fixes the naming of the registers:
>
> s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>
> And also fix the hex values to lower case, to match
> rest of the definitions.
>
> Manasi noticed this with the patch that was merged.
>
> Fix
This patch fixes the naming of the registers:
s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
And also fix the hex values to lower case, to match
rest of the definitions.
Manasi noticed this with the patch that was merged.
Fixes - 8b1b558d690aa (drm/i915/icl: Add DSS_CTL Registers)
Suggested-by: Manasi Navare
== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation. (rev4)
URL : https://patchwork.freedesktop.org/series/51566/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070 -> Patchwork_10698 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev8)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069 -> Patchwork_10697 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchw
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067_full -> Patchwork_10694_full =
== Summary - WARNING ==
Minor unknown changes c
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev8)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ceabdae66c4a drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:64: CHECK:MACRO_ARG_REUSE: Macro argu
== Series Details ==
Series: series starting with [1/3] drm/atomic: Use explicit old crtc state in
drm_atomic_add_affected_planes()
URL : https://patchwork.freedesktop.org/series/51894/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069 -> Patchwork_10696 =
== Summary - SU
On Thu, Nov 01, 2018 at 11:34:20AM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 31, 2018 at 10:19:15PM +0200, Imre Deak wrote:
> > On Wed, Oct 31, 2018 at 01:08:06PM -0700, Rodrigo Vivi wrote:
> > > On Wed, Oct 31, 2018 at 10:02:20PM +0200, Imre Deak wrote:
> > > > On GEN9 LP (BXT/GLK) DC6 is not suppo
On Tue, Oct 30, 2018 at 03:27:35PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 30, 2018 at 01:45:02AM -0700, Radhakrishna Sripada wrote:
> > Display WA_1405510057 asks to not enable YUV 420 HDMI
> > 10bpc when horizontal blank size mod 8 reminder is 2.
> >
> > V2: Rebase(r-b: Anusha)
> > V3: crtc_sta
== Series Details ==
Series: series starting with [1/3] drm/atomic: Use explicit old crtc state in
drm_atomic_add_affected_planes()
URL : https://patchwork.freedesktop.org/series/51894/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f26f227aa8ea drm/atomic: Use explicit old crt
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev4)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5069 -> Patchwork_10695 =
== Summary - SUCCESS ==
No regressions found.
External URL:
>-Original Message-
>From: Roper, Matthew D
>Sent: Thursday, November 1, 2018 5:10 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable ICL Pipe CSC block
>
>On Wed, Oct 24, 2018 at 08:
>-Original Message-
>From: Roper, Matthew D
>Sent: Thursday, November 1, 2018 5:10 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: Add icl pipe degamma and
>gamma support
>
>On Tue, Oct 3
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device
info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067_full -> Patchwork_10693_full =
== Summary
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
v3:
- Remove register offset defines. (Jan
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definitio
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be done
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It
From: Ville Syrjälä
Convert drm_atomic_plane_check() over to using explicit old vs. new
plane states. Avoids the confusion of "what does plane->state mean
again?".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 90 ++--
1 file changed, 46 insert
From: Ville Syrjälä
Replace 'crtc->state' with the explicit old crtc state.
Actually it shouldn't matter whether we use the old or the new
crtc state here since any plane that has been removed from the
crtc since the crtc state was duplicated will have been added
to the atomic state already. Tha
From: Ville Syrjälä
Convert drm_atomic_crtc_check() over to using explicit old vs. new
crtc states. Avoids the confusion of "what does crtc->state mean
again?".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 26 +++---
1 file changed, 15 insertions(+), 11 d
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, November 2, 2018 12:00 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [v8 2/2] drm/i915/icl: Enable Plane Input CSC f
On Wed, Oct 31, 2018 at 10:19:15PM +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 01:08:06PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 31, 2018 at 10:02:20PM +0200, Imre Deak wrote:
> > > On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter
> > > on those platforms. So far we d
On Fri, Nov 02, 2018 at 12:03:12AM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-
On Thu, Nov 01, 2018 at 12:44:02AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/4] drm/i915: Kill WA 0528
> URL : https://patchwork.freedesktop.org/series/51826/
> State : success
series pushed to dinq. thanks for reviews.
>
> == Summary ==
>
> = CI B
On Wed, Oct 31, 2018 at 02:15:09PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 31, 2018 at 01:27:26PM -0700, Anusha Srivatsa wrote:
>
> I intend to modify this commit message while merging with the following:
>
> Add missing block that takes care of inline intel_suspend_complete
> for DC9 on ICL.
>
On Thu, Nov 01, 2018 at 05:17:36PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove the "sizes are 0 based" stuff that is not even true for the
> scaler.
>
> v2: Rebase
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 18 +
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev2)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067_full -> Patchwork_10690_full =
== Summary - WARNING ==
Minor unknown changes
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definitio
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be done
On Thu, Nov 01, 2018 at 05:27:47PM +0200, Jani Nikula wrote:
> On Tue, 30 Oct 2018, Jani Nikula wrote:
> > From: Anusha Srivatsa
> >
> > Add defines for DSS_CTL registers.
> > These registers specify the big joiner, splitter,
> > overlap pixels and info regarding
> > compression enabled on left o
On Thu, Nov 01, 2018 at 05:05:52PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No need for the posting reads in the plane update/disable hooks.
> If we need a posting read for something then a single one at the
> very end would be sufficient. We have that anyway in the form
> of eg. sca
On Thu, Nov 01, 2018 at 07:39:39PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 15, 2018 at 10:38:35AM +0300, Stanislav Lisovskiy wrote:
> > v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> > Added comment about AYUV byte ordering in Gstreamer.
> >
> > v3: Removed sna_composite_op flags rela
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Thursday, November 1, 2018 3:21 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [v7 2/2] drm/i915/icl: Enable Plane Input CSC
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Thursday, November 1, 2018 3:17 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [v7 2/2] drm/i915/icl: Enable Plane Input CSC
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067 -> Patchwork_10694 =
== Summary - SUCCESS ==
No regressions found.
External
On Mon, Oct 15, 2018 at 10:38:35AM +0300, Stanislav Lisovskiy wrote:
> v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> Added comment about AYUV byte ordering in Gstreamer.
>
> v3: Removed sna_composite_op flags related change to the separate patch.
>
> v4: Fixed review comments, done co
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device
info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067 -> Patchwork_10693 =
== Summary - SUCCESS
On Thu, Nov 01, 2018 at 05:33:59PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> This patch read out the current hw state for DSI and
> return true if encoder is active.
>
> v2 by Jani:
> - Squash connector get hw state hook here
> - Squash encode get hw state fix here
>
> v3 by Jani:
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