Regards
Shashank
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch adds a colorspace property enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream
Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5083_full -> Patchwork_10721_full =
== Summary -
Hello Uma,
My comments inline.
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch series creates a new connector property to program
colorspace to sink devices. Modern sink devices support more
than 1 type of colorspace like 601, 709, BT2020 etc. This helps
to switch based on content type
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream
Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5083 -> Patchwork_10721 =
== Summary - SUCCESS ==
== Series Details ==
Series: drm/i915: HPD IRQ storm detection fixes (rev3)
URL : https://patchwork.freedesktop.org/series/51556/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5082_full -> Patchwork_10720_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream
Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc: Define Display Stream
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream
Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e904fd188f2c drm/dsc: Define Display Stream Compression
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v4:
*
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
On Tue, Oct 30, 2018 at 05:45:17PM -0700, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
>
> v2:
> - rebased.
> - Add additional check for compression state. (Gaurav)
>
> v3: rebased.
>
> v4:
> - Move the code to the proper spot
On Fri, Nov 02, 2018 at 02:31:38PM -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
>
> force_dsc_en written through
On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic
== Series Details ==
Series: drm/i915: HPD IRQ storm detection fixes (rev3)
URL : https://patchwork.freedesktop.org/series/51556/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5082 -> Patchwork_10720 =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI
URL : https://patchwork.freedesktop.org/series/51976/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10716_full =
== Summary - FAILURE ==
Serious unknown changes coming
== Series Details ==
Series: drm/i915: HPD IRQ storm detection fixes (rev3)
URL : https://patchwork.freedesktop.org/series/51556/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix possible race in intel_dp_add_mst_connector()
Okay!
Commit:
Currently in intel_hpd_irq_storm_detect() when we detect that the last
recorded hotplug wasn't within the period defined by
HPD_STORM_DETECT_DELAY, we make the mistake of resetting the HPD count
to 0 without incrementing it. This results in us only enabling storm
detection when we go +2 above the
Turns out that if you trigger an HPD storm on a system that has an MST
topology connected to it, you'll end up causing the kernel to eventually
hit a NULL deref:
[ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
00ec
[ 332.340906] PGD 0 P4D 0
[ 332.342750]
This hasn't caused any issues yet that I'm aware of, but as Ville
Syrjälä pointed out - we need to make sure that
intel_connector->mst_port is set before initializing MST connectors,
since in theory we could potentially check intel_connector->mst_port in
i915_hpd_poll_init_work() after registering
This series contains a fix for a problem which is very difficult to
reproduce under normal circumstances without specialized testing
hardware, along with a fix that seems to be required for some especially
rebellious GM45 laptops.
Lyude Paul (5):
drm/i915: Fix possible race in
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having
This is rather confusing to look at as-is:
dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler()
handles disabling the actual HPD IRQ, while
intel_hpd_irq_storm_disable() handles moving the HPD pin state over from
MARK_DISABLED to DISABLED along with enabling polling for it.
Cc:
== Series Details ==
Series: drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
URL : https://patchwork.freedesktop.org/series/51971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10715_full =
== Summary - WARNING ==
Minor unknown changes
On Sat, 2018-11-03 at 01:06 +0200, Imre Deak wrote:
> On Fri, Nov 02, 2018 at 01:39:23PM -0700, José Roberto de Souza
> wrote:
> > When suspending or unloading the driver, it needs to release the
> > TC ports so HW can change it state without wait for driver
> > handshake.
> > Spec also state that
On Fri, Nov 02, 2018 at 01:39:23PM -0700, José Roberto de Souza wrote:
> When suspending or unloading the driver, it needs to release the
> TC ports so HW can change it state without wait for driver handshake.
> Spec also state that if the port is not used by driver it should
> release TC access,
== Series Details ==
Series: drm/i915/icl: Fix combo PHY HW context loss
URL : https://patchwork.freedesktop.org/series/51970/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10714_full =
== Summary - WARNING ==
Minor unknown changes coming with
On Fri, Nov 02, 2018 at 03:28:00PM -0700, Lucas De Marchi wrote:
> On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote:
> > On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> > > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > > > On Fri, Nov 02, 2018 at
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> This patch adds missing programming for static/fixed/legacy TypeC
> HDMI
> outputs. The lack of this resulted in blank screen when booting
> without
> an HDMI display being connected, or after system suspend/resume,
> since
> in these cases
== Series Details ==
Series: series starting with [1/3] drm/lease: debug output for lease creation
(rev2)
URL : https://patchwork.freedesktop.org/series/51944/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC
== Series Details ==
Series: DSC enabling remaining patches respin
URL : https://patchwork.freedesktop.org/series/51986/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5082 -> Patchwork_10718 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10718
On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote:
> On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > > > On Thu, Nov 01, 2018 at
On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > > >
> > > > On 01/11/2018
On Fri, Nov 02, 2018 at 11:06:43PM +0200, Souza, Jose wrote:
> On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> > Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code
> > in a
> > separate file.
> >
> > No functional change.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Paulo
On Fri, Nov 02, 2018 at 10:57:19PM +0200, Souza, Jose wrote:
> On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> > BSpec says to clear the comp init HW flag too during combo PHY
> > uninit,
> > so do that. The lack of this could badly interact with the PHY reinit
> > after a DC6/9 transition
On Fri, Nov 02, 2018 at 11:25:58PM +0200, Souza, Jose wrote:
> On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> > Verify on CNL, ICL that the combo PHY HW state stayed intact after
> > PHY
> > initialization.
> >
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Cc: José Roberto de Souza
> >
== Series Details ==
Series: DSC enabling remaining patches respin
URL : https://patchwork.freedesktop.org/series/51986/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!
Commit: drm/dsc:
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG DP mode needs to be configured for Type C static/fixed/legacy
> HDMI ports too, the same way as it's configured for Type C
> static/fixed/legacy, fix this.
Reviewed-by: José Roberto de Souza
>
> Bspec: 4232, 21735
> Cc: Vandita
On Fri, Nov 02, 2018 at 01:39:22PM -0700, José Roberto de Souza wrote:
> MST ports did not had the post_pll_disable() hook causing the
> references get in pre_pll_enable() never being released causing
> DDI and AUX CH being enabled all the times.
>
> Cc: Imre Deak
> Cc: Manasi Navare
>
== Series Details ==
Series: DSC enabling remaining patches respin
URL : https://patchwork.freedesktop.org/series/51986/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9b21924528e8 drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added,
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG PHY clock gating needs to be configured for Type C
> static/fixed/legacy HDMI ports the same way it's configured for Type
> C
> static/fixed/legacy and aternate mode DP ports, fix this.
>
Reviewed-by: José Roberto de Souza
> Bspec:
It's lockless, and userspace might chance it underneath us. That's not
really a problem, all userspace gets is a slightly dysfunctional
lease with the current code. But this might change, and gcc might
decide to reload a few too many times, and then boom. So better safe
than sorry.
v2: Remove the
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> On ICL DMC/PCODE retains the HW context only for port A across DC
> transitions, for the other port B combo PHY, it doesn't. So we need
> to
> do this manually after exiting from DC6. Do the reinit even after
> exiting from DC5, it won't hurt
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Verify on CNL, ICL that the combo PHY HW state stayed intact after
> PHY
> initialization.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
>
On Fri, Nov 02, 2018 at 01:39:21PM -0700, José Roberto de Souza wrote:
> intel_dp_detect() caches the aux_domain in the beginning of the
> function as it is used twice, so lets also use it as the aux_domain
> don't change in runtime.
>
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
>
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Bspec says we should skip the initialization of combo PHYs that are
> already initialized. We'll need to reinit the PHYs more frequently
> when exiting from DC6 (after the next patch), so let's make sure the
> uninit sequence complies with the
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
This patch series addresses following comments from the previous
series: https://patchwork.freedesktop.org/series/51916/
- no FEC so should reject DSC on external DP
-> Added this to intel_dp_source_supports_dsc
- get_power_domains() thing wasn't right
-> Fixed the logic
-The potentially user
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v3:
*
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Verify on CNL, ICL that the combo PHY HW state stayed intact after
> PHY
> initialization.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
>
== Series Details ==
Series: series starting with [01/25] RFT drm/i915/execlists: Flush memory
before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51967/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10713_full =
== Summary -
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code
> in a
> separate file.
>
> No functional change.
>
> Suggested-by: Ville Syrjälä
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
>
On Fri, Nov 02, 2018 at 07:52:53PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:53PM -0700, Manasi Navare wrote:
> > After encoder->pre_enable() hook, after link training sequence is
> > completed, PPS registers for DSC encoder are configured using the
> > DSC state parameters in
== Series Details ==
Series: series starting with [1/4] drm/i915: Reuse the aux_domain cached
URL : https://patchwork.freedesktop.org/series/51983/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10717 =
== Summary - FAILURE ==
Serious unknown changes
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> BSpec says to clear the comp init HW flag too during combo PHY
> uninit,
> so do that. The lack of this could badly interact with the PHY reinit
> after a DC6/9 transition at least, where (after a follow-up patch
> fixing
> the init code) we'd
On Fri, Nov 02, 2018 at 01:39:22PM -0700, José Roberto de Souza wrote:
> MST ports did not had the post_pll_disable() hook causing the
> references get in pre_pll_enable() never being released causing
> DDI and AUX CH being enabled all the times.
>
> Cc: Imre Deak
> Cc: Manasi Navare
>
== Series Details ==
Series: series starting with [1/4] drm/i915: Reuse the aux_domain cached
URL : https://patchwork.freedesktop.org/series/51983/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reuse the aux_domain cached
Okay!
Commit:
On Fri, Oct 26, 2018 at 06:49:08PM -0400, Lyude Paul wrote:
> Turns out that if you trigger an HPD storm on a system that has an MST
> topology connected to it, you'll end up causing the kernel to eventually
> hit a NULL deref:
>
> [ 332.339041] BUG: unable to handle kernel NULL pointer
Some USB type-C dongles requires some time to power on before being
able to process aux channel transactions.
It was not a problem for older gens because there was a bridge
between DP port and USB-C controller adding some delay but ICL
handles type-C native.
So here trying to do a aux channel
When suspending or unloading the driver, it needs to release the
TC ports so HW can change it state without wait for driver handshake.
Spec also state that if the port is not used by driver it should
release TC access, so here only grabbing control of the TC ports and
marking as unsafe when aux
intel_dp_detect() caches the aux_domain in the beginning of the
function as it is used twice, so lets also use it as the aux_domain
don't change in runtime.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 3 +--
1 file changed, 1 insertion(+), 2
MST ports did not had the post_pll_disable() hook causing the
references get in pre_pll_enable() never being released causing
DDI and AUX CH being enabled all the times.
Cc: Imre Deak
Cc: Manasi Navare
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp_mst.c | 15
On Fri, Nov 02, 2018 at 07:51:18PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote:
> > If a eDP panel supports both PSR2 and VDSC, our HW cannot
> > support both at a time. Give priority to PSR2 if a requested
> > resolution can be supported without
== Series Details ==
Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI
URL : https://patchwork.freedesktop.org/series/51976/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10716 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI
URL : https://patchwork.freedesktop.org/series/51976/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Configure MG PHY gating for HDMI ports too
Okay!
Commit:
Thanks Ville for this detailed review. I will spin this now
with the required fixes and send it over.
Manasi
On Fri, Nov 02, 2018 at 08:06:04PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:40PM -0700, Manasi Navare wrote:
> > This patch series addresses review comments on previous
On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > >
> > > On 01/11/2018 08:35, Lucas De Marchi wrote:
> > > > Instead of using several IS_GEN(),
== Series Details ==
Series: drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
URL : https://patchwork.freedesktop.org/series/51971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10715 =
== Summary - SUCCESS ==
No regressions found.
External
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