[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

== Series Details == Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53185/ State : success == Summary == CI Bug Log - changes from CI_DRM_5216_full -> Patchwork_10936_full

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

Hi, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Rodrigo Vivi > Sent: torstai 29. marraskuuta 2018 8.18 > To: Souza, Jose > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get

Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

On Wed, 2018-11-28 at 22:21 +0100, Daniel Vetter wrote: > On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote: > > On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy > > wrote: > > > Currently kernel might allocate different connector ids > > > for the same outputs in case of

[Intel-gfx] ✗ Fi.CI.BAT: failure for Support 64 bpp half float formats

== Series Details == Series: Support 64 bpp half float formats URL : https://patchwork.freedesktop.org/series/53212/ State : failure == Summary == Applying: drm/fourcc: Add 64 bpp half float formats Applying: drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane Applying: drm/i915:

[Intel-gfx] [PATCH 1/3] drm/fourcc: Add 64 bpp half float formats

Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is formatted in IEEE-754 half-precision float (binary16) 1:5:10 MSb-sign:exponent:fraction form. An 'is_fp' attribute is added to drm_format_info so that drivers can easily distinguish these formats from those that might

[Intel-gfx] [PATCH 2/3] drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane

Add an optional property to allow applications to indicate what range their floating point pixel data is normalized to. Drivers are free to choose what ranges they want to support and can attach this property to each plane that actually supports floating point formats Signed-off-by: Kevin

[Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats

This series defines new formats and adds a plane property to be used for floating point framebuffer content. Implementation is then added to i915. I have shared an IGT branch which adds test coverage for the new formats: https://github.com/strassek/xorg-intel-gpu-tools/tree/fp16 Kevin Strasser

[Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

64 bpp half float formats are supported on hdr planes only and are subject to the following restrictions: * 90/270 rotation not supported * Yf Tiling not supported * Frame Buffer Compression not supported * Color Keying not supported The behavior of pixel normalize with non-float formats

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev3)

== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines (rev3) URL : https://patchwork.freedesktop.org/series/53132/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10945 Summary

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

On Wed, Nov 28, 2018 at 02:13:12PM -0800, Souza, Jose wrote: > On Wed, 2018-11-28 at 21:02 +, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2) > > URL : https://patchwork.freedesktop.org/series/53132/ > > State : failure

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Get pipe id following atomic guidelines (rev3)

== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines (rev3) URL : https://patchwork.freedesktop.org/series/53132/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Get pipe id following atomic guidelines

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2)

== Series Details == Series: drm/i915/cnl: Fix the formulae for register offsets (rev2) URL : https://patchwork.freedesktop.org/series/52960/ State : success == Summary == CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10944 Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the HDMI hot plug disconnection failure (rev4)

== Series Details == Series: drm/i915: Fix the HDMI hot plug disconnection failure (rev4) URL : https://patchwork.freedesktop.org/series/50477/ State : success == Summary == CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10943 Summary

[Intel-gfx] [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets

For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices. v2: Use _PICK instead of formulae(Jani) Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Lucs De Marchi Cc: Daniele Ceraolo Spurio Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 54

[Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v4)

On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes the kernel to believe the HDMI display is still connected. This is because the HDMI DDC lines are disconnected a little bit later after the hot-plug interrupt triggered thus an immediate edid fetch can be made. This problem

Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations

On Wed, 2018-11-28 at 09:17 +0100, Daniel Vetter wrote: > On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote: > > On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote: > > > > We could do this the other way around so it looks like this maybe > > > > struct kref; /* manages kfree() */

[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev9)

== Series Details == Series: HDCP1.4 fixes (rev9) URL : https://patchwork.freedesktop.org/series/38978/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10932_full Summary --- **WARNING**

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp-mst-helper: Remove hotplug callback

== Series Details == Series: drm/dp-mst-helper: Remove hotplug callback URL : https://patchwork.freedesktop.org/series/53192/ State : success == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10942 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp-mst-helper: Remove hotplug callback

== Series Details == Series: drm/dp-mst-helper: Remove hotplug callback URL : https://patchwork.freedesktop.org/series/53192/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0825ba70571a drm/dp-mst-helper: Remove hotplug callback -:167: WARNING:NO_AUTHOR_SIGN_OFF: Missing

[Intel-gfx] ✗ Fi.CI.BAT: failure for HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)

== Series Details == Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2) URL : https://patchwork.freedesktop.org/series/53191/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10940 Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/icl: Release TC ports when unloading or suspending driver (rev2)

== Series Details == Series: series starting with [1/3] drm/i915/icl: Release TC ports when unloading or suspending driver (rev2) URL : https://patchwork.freedesktop.org/series/52195/ State : failure == Summary == Applying: drm/i915/icl: Release TC ports when unloading or suspending driver

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)

== Series Details == Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2) URL : https://patchwork.freedesktop.org/series/53191/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2f174cb3de1c firmware/huc/BXT: Update the HuC version 495993ba9aed firmware/huc/SKL: Update HuC

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) URL : https://patchwork.freedesktop.org/series/53184/ State : success == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10939

[Intel-gfx] ✗ Fi.CI.IGT: failure for Return only active connectors for get_resources ioctl

== Series Details == Series: Return only active connectors for get_resources ioctl URL : https://patchwork.freedesktop.org/series/53163/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10931_full

Re: [Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v2)

On Tue, 13 Nov 2018 13:07:46 +0200 Jani Nikula wrote: > On Mon, 12 Nov 2018, Guang Bai wrote: > > Actually I'm still working on it right now with > > DRM_MODE_CONNECTOR_HDMIA/HDMIB, recommended by James, I'm able to > > differentiate the HDMI or DP even the encoder type is the > >

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) URL : https://patchwork.freedesktop.org/series/53184/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dp:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) URL : https://patchwork.freedesktop.org/series/53184/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6cc046b0e53f drm/i915/dp: Add DSC params

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the HDMI hot plug disconnection failure (rev3)

== Series Details == Series: drm/i915: Fix the HDMI hot plug disconnection failure (rev3) URL : https://patchwork.freedesktop.org/series/50477/ State : success == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10938 Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for Return only active connectors for get_resources ioctl (rev3)

== Series Details == Series: Return only active connectors for get_resources ioctl (rev3) URL : https://patchwork.freedesktop.org/series/53163/ State : success == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10937 Summary

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

On Wed, 2018-11-28 at 21:02 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2) > URL : https://patchwork.freedesktop.org/series/53132/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_5216 ->

[Intel-gfx] [PATCH] drm/dp-mst-helper: Remove hotplug callback

When everyone implements it exactly the same way, among all 4 implementations, there's not really a need to overwrite this at all. Aside: drm_kms_helper_hotplug_event is pretty much core functionality at this point. Probably should move it there. Signed-off-by: Daniel Vetter ---

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Add kbl A0 to preproduction detection list

== Series Details == Series: series starting with [1/2] drm/i915: Add kbl A0 to preproduction detection list URL : https://patchwork.freedesktop.org/series/53162/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10930_full

Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: Release TC ports when unloading or suspending driver

On Wed, 2018-11-28 at 13:34 +0200, Imre Deak wrote: > On Wed, Nov 07, 2018 at 04:05:52PM -0800, José Roberto de Souza > wrote: > > When suspending or unloading the driver, it needs to release the > > TC ports so HW can change it state without wait for driver > > handshake. > > According to >

Re: [Intel-gfx] [PATCH v5 4/5] drm: Add library for shmem backed GEM objects

Daniel Vetter writes: > On Tue, Nov 27, 2018 at 12:38:44PM -0800, Eric Anholt wrote: >> Daniel Vetter writes: >> >> > On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote: >> >> Noralf Trønnes writes: >> >> > +static void drm_gem_shmem_vm_close(struct vm_area_struct *vma) >> >> > +{ >>

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Return only active connectors for get_resources ioctl (rev3)

== Series Details == Series: Return only active connectors for get_resources ioctl (rev3) URL : https://patchwork.freedesktop.org/series/53163/ State : warning == Summary == $ dim checkpatch origin/drm-tip 14116c78b12f Return only active connectors for get_resources ioctl -:26:

[Intel-gfx] [PATCH 5/6] firmware/guc/glk: Load GuC v11.98 for Geminilake.

From: John Spotswood load the v11.98 guC on geminilake. v2: rebased. v3: Change subject prefix. (Anusha) Cc: Tomi Sarvela Cc: Jani Saarinen Signed-off-by: Anusha Srivatsa Signed-off-by: John Spotswood --- drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ 1 file changed, 10

[Intel-gfx] [PATCH 6/6] HAX enable HuC for CI

From: Anusha Srivatsa Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 7e56c516c815..fa65edeb0202 100644 ---

[Intel-gfx] [PATCH 3/6] firmware/huc/KBL: Update HuC for KBL

From: Anusha Srivatsa We have an update of HuC for KBL. Load the latest version. cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c

[Intel-gfx] [PATCH 4/6] firmware/huc/GLK: Load HuC for GLK

From: Anusha Srivatsa Load Huc for GLK. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc_fw.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c index

[Intel-gfx] [PATCH 2/6] firmware/huc/SKL: Update HuC versiom for SKL

From: Anusha Srivatsa We have an update of huC for SKL. Load the latest verion. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c

[Intel-gfx] [PATCH 1/6] firmware/huc/BXT: Update the HuC version

From: Anusha Srivatsa We have an update for HuC for BXT. Load the latest version. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c

[Intel-gfx] [PATCH 0/6] HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK]

Adding PR - The following changes since commit 1baa34868b2c0a004dc595b20678145e3fff83e7: Merge branch 'nxp_mc' of https://github.com/NXP/linux-firmware (2018-10-26 08:13:19 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware firmware_updates for you

Re: [Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v3)

Quoting Guang Bai (2018-11-28 21:18:13) > On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes > the kernel to believe the HDMI display is still connected. This is because > the HDMI DDC lines are disconnected a little bit later after the hot-plug > interrupt triggered thus an

[Intel-gfx] [PATCH v14 02/17] drm/i915/dp: Compute DSC pipe config in atomic check

DSC params like the enable, compressed bpp, slice count and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the

[Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v3)

On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes the kernel to believe the HDMI display is still connected. This is because the HDMI DDC lines are disconnected a little bit later after the hot-plug interrupt triggered thus an immediate edid fetch can be made. Use digital

[Intel-gfx] [PULL v2] drm-misc-fixes

Hi Dave, Here's the updated PR with the mst destroy patch reverted. drm-misc-fixes-2018-11-28-1: - mst: Don't try to validate ports while destroying them (Lyude) - Revert: Don't try to validate ports while destroying them (Lyude) - core: Don't set device to master unless set_master succeeds

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

== Series Details == Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53185/ State : success == Summary == CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10936

Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza wrote: > As stated in struct drm_encoder, crtc field should only be used > by non-atomic drivers. > > So here caching the pipe id in intel_psr_enable() what is way more > simple and efficient than at every call to >

Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

On Wed, Nov 28, 2018 at 10:21:33PM +0100, Daniel Vetter wrote: > On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote: > > On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote: > > > Currently kernel might allocate different connector ids > > > for the same outputs in case

Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote: > On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote: > > Currently kernel might allocate different connector ids > > for the same outputs in case of DP MST, which seems to > > confuse userspace. There are can be

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark up early pre-production Kabylakes

== Series Details == Series: drm/i915: Mark up early pre-production Kabylakes URL : https://patchwork.freedesktop.org/series/53161/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10929_full Summary

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

== Series Details == Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53185/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/ringbuffer: Clear

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2) URL : https://patchwork.freedesktop.org/series/53132/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934 Summary

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state URL : https://patchwork.freedesktop.org/series/53184/ State : failure == Summary == Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote: > Currently kernel might allocate different connector ids > for the same outputs in case of DP MST, which seems to > confuse userspace. There are can be different connector > ids in the list, which could be assigned to the same >

Re: [Intel-gfx] [v4 3/3] drm/i915: Attach colorspace property and enable modeset

Hi Uma, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on next-20181128] [cannot apply to v4.20-rc4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2) URL : https://patchwork.freedesktop.org/series/53132/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Get pipe id following atomic guidelines

Re: [Intel-gfx] [PATCH 4/4] drm/edid: Add display_info.rgb_quant_range_selectable

On Wed, Nov 28, 2018 at 12:19 PM Eric Anholt wrote: > > Ville Syrjala writes: > > > From: Ville Syrjälä > > > > Move the CEA-861 QS bit handling entirely into the edid code. No > > need to bother the drivers with this. > > > > Cc: Alex Deucher > > Cc: "Christian König" > > Cc: "David

Re: [Intel-gfx] [PULL] drm-misc-fixes

On Wed, Nov 28, 2018 at 3:04 PM Sean Paul wrote: > > > Hi Dave, > Happy meson week! A bunch of stellar fixes coming in this week from Lyude, > and a > couple others plugging holes in meson and core. > > > drm-misc-fixes-2018-11-28: > - mst: Don't try to validate ports while destroying them

[Intel-gfx] [PATCH 4/5] drm/i915/selftests: Reorder request allocation vs vma pinning

Impose a restraint that we have all vma pinned for a request prior to its allocation. This is to simplify request construction, and should facilitate unravelling the lock interdependencies later. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--

[Intel-gfx] [PATCH 5/5] drm/i915: Pipeline PDP updates for Braswell

Currently we face a severe problem on Braswell that manifests as invalid ppGTT accesses. The code tries to maintain the PDP (page directory pointers) inside the context in two ways, direct write into the context and a pipelined LRI update. The direct write into the context is fundamentally racy as

[Intel-gfx] [PATCH 1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

Ensure that the sync registers are cleared every time we restart the ring to avoid stale values from creeping in from random neutrinos. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[Intel-gfx] [PATCH 2/5] drm/i915: Allocate a common scratch page

Currently we allocate a scratch page for each engine, but since we only ever write into it for post-sync operations, it is not exposed to userspace nor do we care for coherency. As we then do not care about its contents, we can use one page for all, reducing our allocations and avoid complications

[Intel-gfx] [PATCH 3/5] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly

If all else fails and we are stuck eternally waiting for the undying request, abandon all hope. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] ✓ Fi.CI.IGT: success for Return only active connectors for GET_RESOURCES

== Series Details == Series: Return only active connectors for GET_RESOURCES URL : https://patchwork.freedesktop.org/series/53159/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10928_full Summary

[Intel-gfx] [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits.

From: Anusha Srivatsa If FEC is supported, the corresponding DP_TP_CTL register bits have to be configured. The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and wait till FEC_STATUS in DP_TP_CTL[28] is 1. Also add the warn message to make sure that the control register is

[Intel-gfx] [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION

From: Anusha Srivatsa If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd register: FEC_CONFIGURATION. This has to happen before link training. v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready - change commit message. (Gaurav) v3: rebased. (r-b Manasi)

[Intel-gfx] [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits

1. Disable Left/right VDSC branch in DSS Ctrl reg depending on the number of VDSC engines being used 2. Disable joiner in DSS Ctrl reg v4: * Remove encoder, make crtc_state const (Ville) v3 (From Manasi): * Add Disable PG2 for VDSC on eDP v2 (From Manasi): * Use old_crtc_state to find dsc

[Intel-gfx] [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during

[Intel-gfx] [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params

From: Gaurav K Singh This patches does the following: 1. This patch defines all the DSC parameters as per the VESA DSC specification. These are stored in the encoder and used to compute the PPS parameters to be sent to the Sink. 2. Compute all the DSC parameters which are derived from DSC state

[Intel-gfx] [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI

On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2. v3: * Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville) * Move it around TRANSCODER power domain defs (Ville) v2: * Fix the power well mismatch CI

[Intel-gfx] [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason

[Intel-gfx] [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink

From: Gaurav K Singh This patch enables decompression support in sink device before link training and disables the same during the DDI disabling. v3 (From manasi): * Pass bool state to enable/disable (Ville) v2:(From Manasi) * Change the enable/disable function to take crtc_state instead of

[Intel-gfx] [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC

From: Gaurav K Singh This computation of RC params happens in the atomic commit phase during compute_config() to validate if display stream compression can be enabled for the requested mode. v7 (From Manasi): * Use DRM_DEBUG instead of DRM_ERROR (Ville) * Use Error numberinstead of -1 (Ville)

[Intel-gfx] [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable

Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v4: * Remove redundant comment (Ville) v3: * Use

[Intel-gfx] [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs

Infoframes are used to send secondary data packets. This patch adds support for DSC Picture parameter set secondary data packets in the existing write_infoframe helpers. v3: * Unused variables cleanup (Ville) v2: * Rebase on drm-tip (Manasi) Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha

[Intel-gfx] [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state.

From: Anusha Srivatsa For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error

[Intel-gfx] [CI v13 17/17] drm/i915/fec: Disable FEC state.

From: Anusha Srivatsa Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled. v2: - rebased. - Add additional check for compression state. (Gaurav) v3: rebased. v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi) v5: Remove

[Intel-gfx] [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check

DSC params like the enable, compressed bpp, slice count and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the

[Intel-gfx] [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes

DSC PPS secondary data packet infoframes are filled with DSC picure parameter set metadata according to the DSC standard. These infoframes are sent to the sink device and used during DSC decoding. v3: * Rename to intel_dp_write_pps_sdp (Ville) * Use const intel_crtc_state (Ville) v2: * Rebase ond

[Intel-gfx] [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled

If a eDP panel supports both PSR2 and VDSC, our HW cannot support both at a time. Give priority to PSR2 if a requested resolution can be supported without compression else enable VDSC and keep PSR2 disabled. v4: Fix the unrealted stuff removed during rebase (Ville) v3: * Rebase v2: * Add warning

[Intel-gfx] [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the

Re: [Intel-gfx] [PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully

On Wed, Nov 14, 2018 at 11:07:16PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Here's the remainder of the skl+ ddb/wm programming series. I tried to > split up the ugly monster patch into a few chunks, and I tossed in > a few extra nuggets on top. I also tried to improve the commit >

Re: [Intel-gfx] [PATCH 2/9] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

On Wed, 2018-11-28 at 11:02 -0800, Rodrigo Vivi wrote: > On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza > wrote: > > For PSR2 there is no register to tell HW to keep main link enabled > > while PSR2 is active, so don't configure sink DPCD with a > > misleading value. > > > > Cc:

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, Happy meson week! A bunch of stellar fixes coming in this week from Lyude, and a couple others plugging holes in meson and core. drm-misc-fixes-2018-11-28: - mst: Don't try to validate ports while destroying them (Lyude) - core: Don't set device to master unless set_master succeeds

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume

On 27/11/2018 11:34, Daniele Ceraolo Spurio wrote: On 26/11/2018 06:51, Michal Wajdeczko wrote: On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio wrote: /snip/ diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2)

== Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10927_full

Re: [Intel-gfx] [PATCH v7] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

On Wed, Nov 28, 2018 at 11:09:46AM +0200, Jani Nikula wrote: > On Tue, 27 Nov 2018, Manasi Navare wrote: > > From: Matt Atwood > > > > According to DP spec (2.9.3.1 of DP 1.4) if > > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD > > 02200h through 0220Fh shall contain

Re: [Intel-gfx] [PATCH 2/9] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza wrote: > For PSR2 there is no register to tell HW to keep main link enabled > while PSR2 is active, so don't configure sink DPCD with a > misleading value. > > Cc: Dhinakaran Pandiyan > Cc: Rodrigo Vivi > Signed-off-by: José

Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params (fwd)

; [also build test WARNING on next-20181127] > > [cannot apply to v4.20-rc4] > > [if your patch is applied to the wrong git tree, please drop us a note to > > help improve the system] > > > > url: > > https://github.com/0day-ci/linux/commits/Manasi-Nava

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

== Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10926_full

Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations

On Wed, 2018-11-28 at 09:17 +0100, Daniel Vetter wrote: > On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote: > > On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote: > > > On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote: > > > > On Mon, 2018-11-26 at 22:22 +0100, Daniel

Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params (fwd)

annot apply to v4.20-rc4] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095

Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

On Wed, Nov 28, 2018 at 10:21:05AM -0800, Souza, Jose wrote: > On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote: > > On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza > > wrote: > > > As stated in struct drm_encoder, crtc field should only be used > > > by non-atomic drivers. >

Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote: > On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza > wrote: > > As stated in struct drm_encoder, crtc field should only be used > > by non-atomic drivers. > > > > So here caching the pipe id in intel_psr_enable() what is way

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Been a steady week, and no fixes apart from GVT, so quoting Zhenyu: "One to correct MOCS registers load on engine list, one for rpm lock warning fix, and another for use-after-free fix for partial ggtt list destroy. " Next week, Thursday is a national holiday in Finland, so I'll send

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Fix up drm_atomic_state_helper.[hc] extraction

== Series Details == Series: drm: Fix up drm_atomic_state_helper.[hc] extraction URL : https://patchwork.freedesktop.org/series/53148/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10925_full Summary

Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE

On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote: > On Tue, 06 Nov 2018, Lucas De Marchi wrote: > > From: Rodrigo Vivi > > > > RANGE makes it longer, but clear. We are also going to add a check for > > the display part, so make rename to GT. > > I also still have my doubts about this

Re: [Intel-gfx] [PATCH v2 0/7] Make GEN macros more similar

On Tue, Nov 27, 2018 at 04:19:23PM -0800, Rodrigo Vivi wrote: > > Then on the question of IS_ prefix or not, I don't feel very strongly about > > it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it > > doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote > >

Re: [Intel-gfx] [PATCH 4/4] drm/edid: Add display_info.rgb_quant_range_selectable

Ville Syrjala writes: > From: Ville Syrjälä > > Move the CEA-861 QS bit handling entirely into the edid code. No > need to bother the drivers with this. > > Cc: Alex Deucher > Cc: "Christian König" > Cc: "David (ChunMing) Zhou" > Cc: amd-...@lists.freedesktop.org > Cc: Eric Anholt

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