== Series Details ==
Series: drm/i915/ddi: Check for unexpectedly disabled transcoders
URL : https://patchwork.freedesktop.org/series/53256/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10959_full
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's
host_init (rev2)
URL : https://patchwork.freedesktop.org/series/53295/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10973
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's
host_init
URL : https://patchwork.freedesktop.org/series/53295/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10972
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's
host_init (rev2)
URL : https://patchwork.freedesktop.org/series/53295/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
25b08ad36ccf drm/i915/gvt: mandatory require hypervisor's
This trys to make 'kvmgt' module as self loadable instead of loading
by i915/gvt device model. So hypervisor specific module could be
stand-alone, e.g only after loading hypervisor specific module, GVT
feature could be enabled via specific hypervisor interface, e.g VFIO/mdev.
So this trys to use
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's
host_init
URL : https://patchwork.freedesktop.org/series/53295/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
94364be0a5bd drm/i915/gvt: mandatory require hypervisor's
On Tue, Nov 13, 2018 at 07:23:30PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> SKL+ do not use crtc_state->update_wm_pre, so there is absolutely no
> point it setting it. crtc_state->update_wm_pre only exists as a
> temporary hack for pre-g4x platforms until we redo their
> watermarks
On Tue, Nov 13, 2018 at 07:23:29PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We do return an error when the watermark calculation fails, so
> the FIXME claiming otherwise is outdated. Remove it.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
On Tue, Nov 13, 2018 at 07:23:28PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> skl_compute_wm() wants to compare the old and new watermarks. Currently
> it gets at the old watermarks via crtc->state, which is confusing since
> it can point at either the old or the new state depending
This trys to make 'kvmgt' module as self loadable instead of loading
by i915/gvt device model. So hypervisor specific module could be
stand-alone, e.g only after loading hypervisor specific module, GVT
feature could be enabled via specific hypervisor interface, e.g VFIO/mdev.
So this trys to use
Don't mark hypervisor module's host_init as optional,
but mandatory required.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/mpt.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
index
The parameter 'void *gvt' is not used and required for hypervisor's
exit call. Even for non-merged Xen hypervisor support. So just remove it.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.c | 2 +-
drivers/gpu/drm/i915/gvt/hypercall.h | 2 +-
drivers/gpu/drm/i915/gvt/kvmgt.c
On Thu, Nov 29, 2018 at 06:31:32PM -0800, José Roberto de Souza wrote:
> There is no issues changing the PSR variables even if PSR will be not
> enabled but it avoid having misleading values like have psr2_enabled
> set but enabled unset.
>
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
>
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev3)
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222_full -> Patchwork_10957_full
Summary
== Series Details ==
Series: series starting with [1/2] drm/i915: Check if PSR is globally enabled
before change PSR variables
URL : https://patchwork.freedesktop.org/series/53293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10971
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev6)
URL : https://patchwork.freedesktop.org/series/51011/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222_full -> Patchwork_10956_full
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915: Check if PSR is globally enabled
before change PSR variables
URL : https://patchwork.freedesktop.org/series/53293/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3558d3c4ede6 drm/i915: Check if PSR is globally
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10970
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53291/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable PSR in Apple panels
Okay!
There is no issues changing the PSR variables even if PSR will be not
enabled but it avoid having misleading values like have psr2_enabled
set but enabled unset.
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
Changing the i915_edp_psr_debug was enabling, disabling or switching
PSR version by directly calling intel_psr_disable_locked() and
intel_psr_enable_locked(), what is not the default PSR path that is
executed in a regular modesets.
So lets force a modeset in the PSR CRTC to trigger the requested
EDP_PSR2_FRAME_BEFORE_SU() is the number of frames that PSR2 HW will
wait before enter in PSR2 activation state, important to note here is
that it will wait for X frames not X idle frames.
So lets reuse the previous approch to get the maximum number of
frames between 6 and sink_sync_latency to
Selective updates have a default granularity requirements as stated
by eDP spec, so check if HW can match those requirements before
enable PSR2.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 12
1 file
According to eDP spec, sink can required specific selective update
granularity that source must comply.
Here caching the value if required and checking if source supports
it.
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h |
i915 yet don't support PSR in Apple panels, so lets keep it disabled
while we work on that.
v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
DP_DPCD_QUIRK_NO_PSR (Ville)
Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Dhinakaran
For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
unset in gen10 + GLK we can just drop it and fix for both gens.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
and this bit is only set for PSR1 move it to that block to make it
more easy to read.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 5 +++--
1 file
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
misleading value.
v2: Moving the set of DP_PSR_CRC_VERIFICATION to the else block
of 'if (dev_priv->psr.psr2_enabled)' to another patch. (Rodrigo)
Cc: Dhinakaran Pandiyan
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
Our frontbuffer tracking improved over the years + the WA #0884
helped us keep PSR2 enabled while triggering screen updates when
necessary so this FIXME is not valid anymore.
Acked-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
- Reusing the EDP_PSR2_FRAME_BEFORE_SU_SHIFT in EDP_PSR2_FRAME_BEFORE_SU
- Removing unused EDP_PSR2_FRAME_BEFORE_SU_MASK
- Adding EDP_PSR2_FRAME_BEFORE_SU_MAX
- Adding EDP_PSR2_IDLE_FRAME()
- Adding EDP_PSR2_IDLE_FRAME_MAX
In the next patch the new macros will be used.
Cc: Dhinakaran Pandiyan
Source is required to comply to sink SU granularity when
DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
so adding the registers offsets.
v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: drm/i915/icl: Remove Wa_1604302699
URL : https://patchwork.freedesktop.org/series/53244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222_full -> Patchwork_10955_full
Summary
---
== Series Details ==
Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev3)
URL : https://patchwork.freedesktop.org/series/53191/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10969
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915/backlight: Restore backlight on
resume (rev2)
URL : https://patchwork.freedesktop.org/series/53239/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222_full -> Patchwork_10953_full
On Wed, Nov 28, 2018 at 12:13:30PM -0800, Souza, Jose wrote:
> On Wed, 2018-11-28 at 11:02 -0800, Rodrigo Vivi wrote:
> > On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza
> > wrote:
> > > For PSR2 there is no register to tell HW to keep main link enabled
> > > while PSR2 is active,
== Series Details ==
Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev3)
URL : https://patchwork.freedesktop.org/series/53191/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31a2d0868104 firmware/huc/BXT: Update the HuC version
6615988330bb firmware/huc/SKL: Update HuC
On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> On Mon, 2018-11-26 at 16:37 -0800, José Roberto de Souza wrote:
> > EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the number
> > of
> > frames that it should wait to enter PSR, what is wrong.
> > Here it is setting this
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..c681537bcb92 100644
---
From: Anusha Srivatsa
Load Huc for GLK.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index
Adding the PR-
The following changes since commit 1baa34868b2c0a004dc595b20678145e3fff83e7:
Merge branch 'nxp_mc' of https://github.com/NXP/linux-firmware (2018-10-26
08:13:19 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware firmware_updates
From: Anusha Srivatsa
We have an update for HuC for BXT.
Load the latest version.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
From: Anusha Srivatsa
We have an update of huC for SKL.
Load the latest verion.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
From: Anusha Srivatsa
We have an update of HuC for KBL.
Load the latest version.
cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
From: John Spotswood
load the v11.98 guC on geminilake.
v2: rebased.
v3: Change subject prefix. (Anusha)
Cc: Tomi Sarvela
Cc: Jani Saarinen
Signed-off-by: Anusha Srivatsa
Signed-off-by: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10
On Thu, 2018-11-29 at 15:10 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:09PM -0800, José Roberto de Souza
> wrote:
> > EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the number
> > of
> > frames that it should wait to enter PSR, what is wrong.
> > Here it is setting this
On Thu, 2018-11-29 at 15:25 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 15:07 -0800, Rodrigo Vivi wrote:
> > On Mon, Nov 26, 2018 at 04:37:08PM -0800, José Roberto de Souza
> > wrote:
> > > The first 8 bits of PSR2_CTL have 2 fields to set frames count,
> > > the
> > > first one is
Daniel Vetter writes:
> Cc: Keith Packard
Reviewed-by: Keith Packard
--
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 2018-11-29 at 15:03 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:07PM -0800, José Roberto de Souza
> wrote:
> > According to eDP spec, sink can required specific selective update
> > granularity that source must comply.
> > Here caching the value if required and checking
Daniel Vetter writes:
> On Wed, Nov 28, 2018 at 01:52:56PM -0800, Eric Anholt wrote:
>> Daniel Vetter writes:
>>
>> > On Tue, Nov 27, 2018 at 12:38:44PM -0800, Eric Anholt wrote:
>> >> Daniel Vetter writes:
>> >>
>> >> > On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote:
>> >> >>
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
URL : https://patchwork.freedesktop.org/series/53132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10968
Summary
On Thu, 2018-11-29 at 14:15 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:05PM -0800, José Roberto de Souza
> wrote:
> > For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
> > touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
> > unset in gen10 + GLK we
On Tue, 2018-11-27 at 13:55 -0800, Souza, Jose wrote:
> On Tue, 2018-11-27 at 15:38 +0200, Ville Syrjälä wrote:
> > On Mon, Nov 26, 2018 at 04:37:02PM -0800, José Roberto de Souza
> > wrote:
> > > i915 yet don't support PSR in Apple panels, so lets keep
Replace "Apple" with specific model name?
>
== Series Details ==
Series: drm/i915: Signal the fences as they are cancelled due to wedging (rev2)
URL : https://patchwork.freedesktop.org/series/53226/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5221_full -> Patchwork_10952_full
On Thu, Nov 29, 2018 at 10:26:04PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Get pipe id following atomic guidelines (rev4)
> URL : https://patchwork.freedesktop.org/series/53132/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5226 ->
On Thu, 2018-11-29 at 14:04 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:04PM -0800, José Roberto de Souza
> wrote:
> > eDP spec states 2 different bits to enable sink to trigger a
> > interruption when there is a CRC mismatch.
> > DP_PSR_CRC_VERIFICATION is for PSR only and
> >
On Thu, Nov 29, 2018 at 10:54:50PM +, Atwood, Matthew S wrote:
> On Thu, 2018-11-29 at 14:00 -0800, Manasi Navare wrote:
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 02200h
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
URL : https://patchwork.freedesktop.org/series/53132/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Get pipe id following atomic guidelines
On Mon, 2018-11-26 at 16:37 -0800, José Roberto de Souza wrote:
> EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the number of
> frames that it should wait to enter PSR, what is wrong.
> Here it is setting this field with the highest value to avoid PSR2
> exits frequently, as when HW exit
On Thu, 2018-11-29 at 15:11 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:10PM -0800, José Roberto de Souza
> wrote:
> > Our frontbuffer tracking improved over the years + the WA #0884
> > helped us keep PSR2 enabled while triggering screen updates when
> > necessary so this FIXME is
On Thu, 2018-11-29 at 15:07 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:08PM -0800, José Roberto de Souza
> wrote:
> > The first 8 bits of PSR2_CTL have 2 fields to set frames count, the
> > first one is to set how many idle frames PSR2 HW needs to wait
> > before
> > enter in deep
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20181129]
[cannot apply to v4.20-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
On Mon, Nov 26, 2018 at 04:37:10PM -0800, José Roberto de Souza wrote:
> Our frontbuffer tracking improved over the years + the WA #0884
> helped us keep PSR2 enabled while triggering screen updates when
> necessary so this FIXME is not valid anymore.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo
On Mon, Nov 26, 2018 at 04:37:09PM -0800, José Roberto de Souza wrote:
> EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the number of
> frames that it should wait to enter PSR, what is wrong.
> Here it is setting this field with the highest value to avoid PSR2
> exits frequently, as when
On Mon, Nov 26, 2018 at 04:37:08PM -0800, José Roberto de Souza wrote:
> The first 8 bits of PSR2_CTL have 2 fields to set frames count, the
> first one is to set how many idle frames PSR2 HW needs to wait before
> enter in deep sleep and the second one it is how many frames(it don't
> need to be
On Thu, Nov 29, 2018 at 08:21:41PM +0530, Uma Shankar wrote:
> Add support for icl pipe degamma and gamma.
>
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
>
>
On Mon, Nov 26, 2018 at 04:37:07PM -0800, José Roberto de Souza wrote:
> According to eDP spec, sink can required specific selective update
> granularity that source must comply.
> Here caching the value if required and checking source supports it.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226 -> Patchwork_10967
On Thu, 2018-11-29 at 14:00 -0800, Manasi Navare wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match
On Thu, Nov 29, 2018 at 10:42 AM Daniel Vetter wrote:
>
> Sending the exact same hotplug event is not great uapi. Luckily the
> only already merged implementation of leases (in the -modesetting
> driver) doesn't care about what kind of uevent it gets, and
> unconditionally processes both hotplug
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev4)
URL : https://patchwork.freedesktop.org/series/53132/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5226 -> Patchwork_10966
Summary
On 11/29/18 1:05 PM, Chris Wilson wrote:
> 248 "multiple definition of ...". E.g.:
>
> LD [M] drivers/gpu/drm/i915/i915.o
> ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume':
> i915_irq.c:(.text+0x58f0): multiple definition of `intel_opregion_resume';
>
On Mon, Nov 26, 2018 at 04:37:06PM -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the register here.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto
On Mon, Nov 26, 2018 at 04:37:05PM -0800, José Roberto de Souza wrote:
> For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
> touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
> unset in gen10 + GLK we can just drop it and fix for both gens.
>
> Cc: Dhinakaran
On Mon, Nov 26, 2018 at 04:37:04PM -0800, José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
>
> Cc: Dhinakaran
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev4)
URL : https://patchwork.freedesktop.org/series/53132/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Get pipe id following atomic guidelines
== Series Details ==
Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
URL : https://patchwork.freedesktop.org/series/53284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226 -> Patchwork_10965
From: Matt Atwood
According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 0h through Fh, except for DPCD_REV,
MAX_LINK_RATE,
== Series Details ==
Series: drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
URL : https://patchwork.freedesktop.org/series/53237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5221_full -> Patchwork_10950_full
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:10PM -0800, Kevin Strasser wrote:
>> This series defines new formats and adds a plane property to be used for
>> floating point framebuffer content. Implementation is then added to i915.
>>
>> I have shared an IGT branch which adds test coverage
== Series Details ==
Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
URL : https://patchwork.freedesktop.org/series/53284/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c77019cf17a0 drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:13PM -0800, Kevin Strasser wrote:
>> 64 bpp half float formats are supported on hdr planes only and are subject
>> to the following restrictions:
>> * 90/270 rotation not supported
>> * Yf Tiling not supported
>> * Frame Buffer Compression
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:12PM -0800, Kevin Strasser wrote:
>> Add an optional property to allow applications to indicate what range their
>> floating point pixel data is normalized to. Drivers are free to choose what
>> ranges they want to support and can attach this
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:11PM -0800, Kevin Strasser wrote:
>> + { .format = DRM_FORMAT_XRGB16161616H, .depth = 48,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true },
>> + { .format = DRM_FORMAT_XBGR16161616H,
== Series Details ==
Series: series starting with [1/6] drm/i915: Signal the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53283/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5226 -> Patchwork_10964
On Thu, Nov 29, 2018 at 08:26:31PM +, Souza, Jose wrote:
> On Thu, 2018-11-29 at 06:33 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev3)
> > URL : https://patchwork.freedesktop.org/series/53132/
> > State : failure
== Series Details ==
Series: series starting with [1/6] drm/i915: Signal the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53283/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Signal the fences
== Series Details ==
Series: series starting with [1/6] drm/i915: Signal the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53283/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
63398c8a4108 drm/i915: Signal the fences as they are
248 "multiple definition of ...". E.g.:
LD [M] drivers/gpu/drm/i915/i915.o
ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume':
i915_irq.c:(.text+0x58f0): multiple definition of `intel_opregion_resume';
drivers/gpu/drm/i915/i915_drv.o:i915_drv.c:(.text+0x2d40):
On Thu, Nov 29, 2018 at 10:18:40PM +0200, Souza, Jose wrote:
> On Thu, 2018-11-29 at 15:52 +0200, Imre Deak wrote:
> > On Wed, Nov 28, 2018 at 11:54:21PM +0200, Souza, Jose wrote:
> > > On Wed, 2018-11-28 at 13:34 +0200, Imre Deak wrote:
> > > > On Wed, Nov 07, 2018 at 04:05:52PM -0800, José
== Series Details ==
Series: Return only active connectors for get_resources ioctl (rev4)
URL : https://patchwork.freedesktop.org/series/53163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5221_full -> Patchwork_10949_full
Hi all,
On Thu, 29 Nov 2018 09:09:25 -0800 Randy Dunlap wrote:
>
> on i386:
>
> 248 "multiple definition of ...". E.g.:
>
> LD [M] drivers/gpu/drm/i915/i915.o
> ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume':
> i915_irq.c:(.text+0x58f0): multiple definition of
pushed the latest version of this series
(https://patchwork.freedesktop.org/series/53184/) and
first 5 from https://patchwork.freedesktop.org/series/53113/ to dinq
Thanks for the patches and reviews!
Manasi
On Tue, Nov 20, 2018 at 10:37:13AM -0800, Manasi Navare wrote:
> This patch series
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
We inspect the requests under the assumption that they will be marked as
completed/signaled when they are removed from the queue. Currently
however, in the process of wedging the requests will be removed from the
queue before they are completed, so rearrange the code to signal the
fences before
Pushed to dinq, thanks for the patch and the review.
Manasi
On Wed, Nov 28, 2018 at 12:26:12PM -0800, Manasi Navare wrote:
> Basic DSC parameters and DSC configuration data needs to be computed
> for each of the requested mode during atomic check. This is
> required since for certain modes,
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