On Fri, Nov 30, 2018 at 11:35:25PM +, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-11-30 23:19:18)
> > On Fri, Nov 30, 2018 at 09:59:53PM +, Chris Wilson wrote:
> > > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > > From: Tomasz Lis
> > > >
> > > > The MOCS tables are going to
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/53341/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10985
S
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
> and this bit is only set for PSR1 move it to that block to make it
> more easy to read.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Rob
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
With PSR short pulse handling
== Series Details ==
Series: i915/dp/fec: Fix static check warning
URL : https://patchwork.freedesktop.org/series/53342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10986
Summary
---
**SUCCESS**
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the registers offsets.
>
> v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
>
> Cc: Dhinakaran Pandiyan
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10987
S
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Selective updates have a default granularity requirements as stated
> by eDP spec
Needs reference to the location in the spec.
> , so check if HW can match those requirements before
> enable PSR2.
typo: enabling*
>
> Cc: Dhinakara
Fix the intel_link_compute_m_n in case of display stream
compression. This patch passes the compressed_bpp to
intel_link_compute_m_n if compression is enabled.
Fixes: a4a15c80 ("drm/i915/dp: Compute DSC pipe config in atomic check")
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi
== Series Details ==
Series: drm/i915/dp: Fix link compute m_n calc for DSC
URL : https://patchwork.freedesktop.org/series/53347/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10988
Summary
---
**SU
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10975_full
==
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10976_full
===
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10979_full
Sum
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy request.
Thanks to Chris for helping with reset magic.
Signed-off-by: Tvrtko Ursulin
C
From: Tvrtko Ursulin
Pull out spinner code to a standalone file to enable it to be shortly used
by other and new test cases.
Plain code movement - no functional changes.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/selftests/igt
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
URL : https://patchwork.freedesktop.org/series/53298/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
afa57c2cbca8 drm/i915/selftests: Extract spinner code
-:28: WARNING:FILE_PATH_CHA
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
URL : https://patchwork.freedesktop.org/series/53298/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Extract spinner code
+./include/ua
== Series Details ==
Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3)
URL : https://patchwork.freedesktop.org/series/53243/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10960_full
On Sat, Nov 03, 2018 at 11:41:10PM +0200, Jani Nikula wrote:
> On Fri, 12 Oct 2018, José Roberto de Souza wrote:
> > num_pipes is set to 0 if disable_display is set inside
> > intel_device_info_runtime_init() but when that happen PCH will
> > already be set in intel_detect_pch().
> >
> > i915_driv
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10974
Su
On Thu, Nov 29, 2018 at 05:52:28PM +, Strasser, Kevin wrote:
> Daniel Vetter wrote:
> > Do we have end-to-end userspace for this?
>
> I have patches for IGT and I'm planning on adding usage code to Weston. Apart
> from that there is a Windows use case that Tina mentioned previously. I take
> i
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy request.
Thanks to Chris for helping with reset magic.
v2:
* Grab RPM ref over reset.
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_h
Quoting Tvrtko Ursulin (2018-11-30 08:02:53)
> From: Tvrtko Ursulin
>
> Pull out spinner code to a standalone file to enable it to be shortly used
> by other and new test cases.
>
> Plain code movement - no functional changes.
>
> Signed-off-by: Tvrtko Ursulin
Shiver me conflicts.
Reviewed-by
Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--
.../gpu/d
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ri
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the code to complete the fences before the
locks
Quoting Tvrtko Ursulin (2018-11-30 08:02:54)
> From: Tvrtko Ursulin
>
> The test was missing some magic ingredients to actually trigger the
> resets.
>
> In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
> case of engine reset we need a busy request.
>
> Thanks to Chris
On Thu, Nov 29, 2018 at 04:06:56PM -0800, Keith Packard wrote:
> Daniel Vetter writes:
>
> > Cc: Keith Packard
>
> Reviewed-by: Keith Packard
Thanks for review, pushed to drm-misc-fixes.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
__
== Series Details ==
Series: series starting with [1/2] drm/i915:
s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
URL : https://patchwork.freedesktop.org/series/53275/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10961_full
=
Quoting Randy Dunlap (2018-11-29 22:16:08)
> On 11/29/18 1:05 PM, Chris Wilson wrote:
> > 248 "multiple definition of ...". E.g.:
> >
> > LD [M] drivers/gpu/drm/i915/i915.o
> > ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume':
> > i915_irq.c:(.text+0x58f0): multip
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.
Reported-by: M
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bcfddfda17f5 drm/i915/selftests: Extract spinner code
-:29: WARNING:FILE_
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Extract spinner code
+./in
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1826a0f0e99f drm/i915: Complete the fences as they are
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Complete the fenc
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was discovere
From: Tvrtko Ursulin
Analogue to the previous patch we add at runtime verification that after
engine reset all respective workarounds have been correctly applied.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is a
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 13 +
1 f
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
At this stage these are the driver initialization and engine rese
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration o
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
Signed-off-by: Tvrtko Ursulin
---
d
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
> From: Tvrtko Ursulin
>
> Since we now have all the GT workarounds in a table, by adding a simple
> shared helper function we can now verify that their values are still
> applied after some interesting events in the lifetime of the driver.
>
> At thi
Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
> From: Tvrtko Ursulin
>
> Two simple selftests which test that both GT and engine workarounds are
> not lost after either a full GPU reset, or after the per-engine ones.
>
> (Including checks that one engine reset is not affecting workarounds not
> b
Quoting Tvrtko Ursulin (2018-11-30 11:31:59)
> -static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
> +static void
> +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> {
> - if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
> - return;
> -
> -
Quoting Tvrtko Ursulin (2018-11-30 11:32:00)
> From: Tvrtko Ursulin
>
> Convert the per context workaround handling code to run against the newly
> introduced common workaround framework and fuse the two to use the
> existing smarter list add helper, the one which does the sorted insert and
> mer
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10976
=
Quoting Tvrtko Ursulin (2018-11-30 11:32:01)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> d
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
> From: Tvrtko Ursulin
>
> Since we now have all the GT workarounds in a table, by adding a simple
> shared helper function we can now verify that their values are still
> applied after some interesting events in the lifetime of the driver.
>
> At thi
Chris Wilson writes:
> Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> actually broke the force-mmio mode for our execlists implementation. No
> one noticed, so ergo no one is actually using an old vGPU host (where we
> required the older method) and so can simply remove the
On 30/11/2018 11:38, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling
URL : https://patchwork.freedesktop.org/series/53313/
State : failure
== Summary ==
Applying: drm/i915: Record GT workarounds in a list
Applying: drm/i915: Introduce per-engine workarounds
Applying: dr
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10977
Summary
---
*
On 30/11/2018 09:53, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 08:02:54)
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy
== Series Details ==
Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC
config to intel_crtc_state (rev3)
URL : https://patchwork.freedesktop.org/series/53184/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10963_full
===
Quoting Tvrtko Ursulin (2018-11-30 12:17:13)
>
> On 30/11/2018 09:53, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-30 08:02:54)
> >> From: Tvrtko Ursulin
> >>
> >> The test was missing some magic ingredients to actually trigger the
> >> resets.
> >>
> >> In case of the full reset we ne
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.
v2: csb_read c
On 29/11/2018 19:36, Rodrigo Vivi wrote:
> On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
>> Hi,
>>
>>> -Original Message-
>>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>>> Of
>>> Rodrigo Vivi
>>> Sent: torstai 29. marraskuuta 2018 8.18
On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
> Hi,
>
> I am looking for a way to export the color encoding and range selection
> to user space. I came across those properties and am wondering, why
> they are meant only for non RGB color encodings. Would it be okay, to
> mo
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10979
Summary
-
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions
a bit by moving the pll to port mapping and unmapping functions to the
ddi encoder hooks. This allows removal of a bunch of boilerplate code
from the functions.
Additionally, the IC
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add dummy debug logging GPIO element execution function for ICL.
Looks fine to me.
Reviewed-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +-
1 file changed, 9 insertions(+),
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add encoder specific pll mapping for DSI. The differences with the DDI
version are big enough to warrant a separate function.
Cc: Madhav Chauhan
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 24
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Some machines seem to have a broken opregion where the VBT overflows the
mailbox. Ignore this until properly fixed.
Right, otherwise DSI modeset doesn't progress further.
Acked-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani Nikula
---
dr
On 11/2/2018 5:17 PM, Jani Nikula wrote:
Next version of [1]. Sorry for the spam, needed to get the authorship
straight. Fixed power domains and compute config hook initialization.
Overall, with this series ICL DSI dual link video mode feature looks
complete to me. Thanks!!
Regards,
Madhav
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Madhav Chauhan
> Sent: Friday, November 30, 2018 7:43 PM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
>
> O
On Thu, Nov 29, 2018 at 09:39:52PM +, Strasser, Kevin wrote:
> Ville Syrjälä wrote:
> > On Wed, Nov 28, 2018 at 10:38:10PM -0800, Kevin Strasser wrote:
> >> This series defines new formats and adds a plane property to be used for
> >> floating point framebuffer content. Implementation is then a
Hi Ville,
As Christoph cannot respond till middle next week I can try to respond
in his absence, as I am familiar with the subject.
On 30.11.2018 14:25, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
>> Hi,
>>
>> I am looking for a way to export the c
On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond till middle next week I can try to respond
> in his absence, as I am familiar with the subject.
>
> On 30.11.2018 14:25, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Ch
Quoting Tvrtko Ursulin (2018-11-30 12:02:56)
>
> On 30/11/2018 11:38, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
> >> From: Tvrtko Ursulin
> >>
> >> Since we now have all the GT workarounds in a table, by adding a simple
> >> shared helper function we can now verify that
On 11/30/18 15:20, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond till middle next week I can try to respond
> in his absence, as I am familiar with the subject.
>
> On 30.11.2018 14:25, Ville Syrjälä wrote:
>> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote
On 11/30/18 15:29, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
>> Hi Ville,
>>
>> As Christoph cannot respond till middle next week I can try to respond
>> in his absence, as I am familiar with the subject.
>>
>> On 30.11.2018 14:25, Ville Syrjälä wrote:
>>
On 30/11/2018 11:24, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975
===
On 29/11/2018 14:47, Patchwork wrote:
== Series Details ==
Series: drm/i915/icl: Remove Wa_1604302699
URL : https://patchwork.freedesktop.org/series/53244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222 -> Patchwork_10955
On 29/11/2018 17:48, Patchwork wrote:
== Series Details ==
Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3)
URL : https://patchwork.freedesktop.org/series/53243/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5224 -> Patchwork_10960
=
On 30/11/2018 11:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is
On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
> On 11/30/18 15:29, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> >> Hi Ville,
> >>
> >> As Christoph cannot respond till middle next week I can try to respond
> >> in his absence, as I am fam
On 30/11/2018 11:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:00)
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one whi
On 30/11/2018 11:45, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:59)
-static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
-
On 30/11/2018 11:49, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:01)
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
Signed-off
On 30/11/2018 11:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the
Quoting Tvrtko Ursulin (2018-11-30 15:15:28)
>
> On 30/11/2018 11:43, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
> >> From: Tvrtko Ursulin
> >>
> >> Two simple selftests which test that both GT and engine workarounds are
> >> not lost after either a full GPU reset, or af
>-Original Message-
>From: Roper, Matthew D
>Sent: Friday, November 30, 2018 4:38 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ;
>Sharma,
>Shashank
>Subject: Re: [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support
>
>On Thu,
On 11/30/18 16:16, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
>> On 11/30/18 15:29, Ville Syrjälä wrote:
>>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
Hi Ville,
As Christoph cannot respond till middle next week I can try
On Thu, Nov 29, 2018 at 10:36:13AM -0500, Sean Paul wrote:
> On Wed, Nov 28, 2018 at 5:07 AM Daniel Vetter wrote:
> >
> > I've misplaced two functions by accident:
> > - drm_atomic_helper_duplicate_state is really part of the
> > resume/suspend/shutdown device-wide helpers.
> > - drm_atomic_help
On Fri, 30 Nov 2018 14:51:24 +0800
Zhenyu Wang wrote:
> This trys to make 'kvmgt' module as self loadable instead of loading
> by i915/gvt device model. So hypervisor specific module could be
> stand-alone, e.g only after loading hypervisor specific module, GVT
> feature could be enabled via spec
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev3)
URL : https://patchwork.freedesktop.org/series/53094/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56cf8aa074f9 drm/fbdev: Make skip_vt_switch the default
-:22: ERROR:GIT_COMMIT_ID: Please use git c
Hi,
On Fri, Nov 30, 2018 at 04:34:54PM +0100, Hans Verkuil wrote:
> On 11/30/18 16:16, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
> >> On 11/30/18 15:29, Ville Syrjälä wrote:
> >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi
== Series Details ==
Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
URL : https://patchwork.freedesktop.org/series/53284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10965_full
===
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev3)
URL : https://patchwork.freedesktop.org/series/53094/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5234 -> Patchwork_10980
Summary
---
*
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10967_full
On Fri, Nov 30, 2018 at 07:31:01AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ddi: Check for unexpectedly disabled transcoders
> URL : https://patchwork.freedesktop.org/series/53256/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5224_full ->
On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
>
>
> On 29/11/2018 19:36, Rodrigo Vivi wrote:
> > On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
> >> Hi,
> >>
> >>> -Original Message-
> >>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] O
Hi,
I am looking for a way to export the color encoding and range selection
to user space. I came across those properties and am wondering, why
they are meant only for non RGB color encodings. Would it be okay, to
modify them and use with RGB formats as well?
Regards,
Chris
On 02/19/2018 09:28
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