[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp: Set the connector's TILE property even for DP SST connectors

== Series Details == Series: drm/dp: Set the connector's TILE property even for DP SST connectors URL : https://patchwork.freedesktop.org/series/57916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5742_full -> Patchwork_12449_full =

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

Hi, On Wed, Mar 13, 2019 at 09:35:05AM +0100, Daniel Vetter wrote: > On Tue, Mar 12, 2019 at 11:13:03PM +0100, Ahmed S. Darwish wrote: > > On Mon, Mar 11, 2019 at 11:33:15PM +0100, Noralf Trønnes wrote: > > > Den 11.03.2019 20.23, skrev Daniel Vetter: [……] > > > > > > > > class_for_each_device use

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Also use new comparative stuff for more ICP+ stuff

== Series Details == Series: drm/i915: Also use new comparative stuff for more ICP+ stuff URL : https://patchwork.freedesktop.org/series/57961/ State : success == Summary == CI Bug Log - changes from CI_DRM_5743 -> Patchwork_12456 Summary -

[Intel-gfx] ✗ Fi.CI.BAT: failure for Compartmentalize uncore code

== Series Details == Series: Compartmentalize uncore code URL : https://patchwork.freedesktop.org/series/57962/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gvt/scheduler.o drivers/gpu/drm

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)

== Series Details == Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2) URL : https://patchwork.freedesktop.org/series/57900/ State : success == Summary == CI Bug Log - changes from CI_DRM_5743 -> Patchwork_12455

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)

== Series Details == Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2) URL : https://patchwork.freedesktop.org/series/57900/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix PSR2 selective update corruption afte

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs

== Series Details == Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs URL : https://patchwork.freedesktop.org/series/57959/ State : success == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12454

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

[[ Adding Sebastian, who is quite experienced in intricate locking situations due to daily PREEMPT_RT work.. ]] On Wed, Mar 13, 2019 at 09:37:10AM +0100, Daniel Vetter wrote: > On Wed, Mar 13, 2019 at 08:49:17AM +0100, John Ogness wrote: > > On 2019-03-12, Ahmed S. Darwish wrote: > > > On Wed

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs

== Series Details == Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs URL : https://patchwork.freedesktop.org/series/57959/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/ehl: Add EHL platform info and PCI ID

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs

== Series Details == Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs URL : https://patchwork.freedesktop.org/series/57959/ State : warning == Summary == $ dim checkpatch origin/drm-tip 62bc6b41a37f drm/i915/ehl: Add EHL platform info and PCI IDs -:60: ERROR:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Disable preemption while setting up fence-timers

== Series Details == Series: drm/i915/selftests: Disable preemption while setting up fence-timers URL : https://patchwork.freedesktop.org/series/57958/ State : success == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12453 S

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Always kick the execlists tasklet after reset

== Series Details == Series: drm/i915: Always kick the execlists tasklet after reset URL : https://patchwork.freedesktop.org/series/57947/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12452 Summary --

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Always kick the execlists tasklet after reset

== Series Details == Series: drm/i915: Always kick the execlists tasklet after reset URL : https://patchwork.freedesktop.org/series/57947/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1e079bce5d0e drm/i915: Always kick the execlists tasklet after reset -:12: WARNING:COMMIT_LOG

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2] drm/i915: Hold a ref to the ring while retiring (rev2)

== Series Details == Series: series starting with [v2] drm/i915: Hold a ref to the ring while retiring (rev2) URL : https://patchwork.freedesktop.org/series/57899/ State : success == Summary == CI Bug Log - changes from CI_DRM_5739_full -> Patchwork_12446_full

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/39] drm/i915: Hold a ref to the ring while retiring

== Series Details == Series: series starting with [01/39] drm/i915: Hold a ref to the ring while retiring URL : https://patchwork.freedesktop.org/series/57942/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12451 ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/39] drm/i915: Hold a ref to the ring while retiring

== Series Details == Series: series starting with [01/39] drm/i915: Hold a ref to the ring while retiring URL : https://patchwork.freedesktop.org/series/57942/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Hold a ref to the ring while retir

[Intel-gfx] [PATCH i-g-t] i915/gem_exec_latency: Measure the latency of context switching

Measure the baseline latency between contexts in order to directly compare that with the additional cost of preemption. Signed-off-by: Chris Wilson --- tests/i915/gem_exec_latency.c | 118 ++ 1 file changed, 118 insertions(+) diff --git a/tests/i915/gem_exec_late

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/39] drm/i915: Hold a ref to the ring while retiring

== Series Details == Series: series starting with [01/39] drm/i915: Hold a ref to the ring while retiring URL : https://patchwork.freedesktop.org/series/57942/ State : warning == Summary == $ dim checkpatch origin/drm-tip 526bf4d5618e drm/i915: Hold a ref to the ring while retiring 848d7519ed

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2)

== Series Details == Series: series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2) URL : https://patchwork.freedesktop.org/series/57937/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12450 ===

[Intel-gfx] [RFC 09/10] drm/i915: add uncore flags

Save some uncore properties to avoid having to jump back to dev_priv every time Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c

[Intel-gfx] [RFC 03/10] drm/i915: use intel_uncore for all forcewake get/put

Now that the internal code all works on intel_uncore, flip the external-facing interface. Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +-- drivers/gpu/drm/i915/i915_debugfs.c | 12 ++--- drivers/gpu/drm/i915/i915_gem.c

[Intel-gfx] [RFC 08/10] drm/i915: make raw access function work on uncore

This allows us to ditch i915 in some more places. RFC: should we just make them work directly on the regs pointer instead? Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.h | 14 ++--- drivers/gpu/drm/i915/i915_vgpu.c| 8 ++- drivers/gpu/drm/i9

[Intel-gfx] [RFC 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore

The full read/write ops can now work on the intel_uncore struct Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.h | 25 ++- drivers/gpu/drm/i915/intel_uncore.c | 26 +--- drivers/gpu/drm/i915/intel_un

[Intel-gfx] [RFC 01/10] drm/i915: do not pass dev_priv to low-level forcewake functions

The only usage we have for it is for the regs pointer. Save a pointer to the set and ack registers instead of the register offsets to remove this requirement Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uncore.c | 100 +--- driver

[Intel-gfx] [RFC 05/10] drm/i915: make find_fw_domain work on intel_uncore

Remove unneeded usage of dev_priv from 1 extra function. Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uncore.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/d

[Intel-gfx] [RFC 02/10] drm/i915: use intel_uncore in fw get/put internal paths

Get/put functions used outside of uncore.c are updated in the next patch for a nicer split Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [RFC 04/10] drm/i915: make more uncore function work on intel_uncore

Move the init, fini, prune, suspend, resume function to work on intel_uncore instead of dev_priv Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 20 +- drivers/gpu/drm/i915/intel_uncore.c | 290 +- drivers/gpu

[Intel-gfx] [RFC 06/10] drm/i915: reduce the dev_priv->uncore dance in uncore.c

Use a local variable where it makes sense. Cc: Paulo Zanoni Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uncore.c | 79 - 1 file changed, 43 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i9

[Intel-gfx] [RFC 07/10] drm/i915: move regs pointer inside the uncore structure

This will allow futher simplifications in the uncore handling. RFC: if we want to keep the pointer logically separate from the uncore, we could also move both the regs pointer and the uncore struct inside a new structure (intel_mmio?) and pass that around instead, or just take a copy of the pointe

[Intel-gfx] [RFC 00/10] Compartmentalize uncore code

In some areas of the driver we do a really bad job in compartmentalizing the code. While passing dev_priv everywhere is always an easy solution, our driver is growing in ways in which this is getting in the way. We really want to compartmentalize our classes and keep as much code as we can under a

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2)

== Series Details == Series: series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2) URL : https://patchwork.freedesktop.org/series/57937/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Hold a ref to the ring whil

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp: Set the connector's TILE property even for DP SST connectors

== Series Details == Series: drm/dp: Set the connector's TILE property even for DP SST connectors URL : https://patchwork.freedesktop.org/series/57916/ State : success == Summary == CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12449 S

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2)

== Series Details == Series: series starting with [01/17] drm/i915: Hold a ref to the ring while retiring (rev2) URL : https://patchwork.freedesktop.org/series/57937/ State : warning == Summary == $ dim checkpatch origin/drm-tip d62cd9df9172 drm/i915: Hold a ref to the ring while retiring 4a3

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Add support for retrying hotplug

== Series Details == Series: series starting with [1/2] drm/i915: Add support for retrying hotplug URL : https://patchwork.freedesktop.org/series/57912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5741 -> Patchwork_12448

[Intel-gfx] [PATCH] drm/i915: Also use new comparative stuff for more ICP+ stuff

I just noticed that initial PCH comparative patch left some >= PCH_ICP cases behind. Let's also cover these cases and leave only the pin map behind now. No functional change. Hence no fixes tag. Cc: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_irq.c| 8 ---

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

On Wed, 2019-03-13 at 19:33 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v4,1/3] drm/i915/vbt: Parse and use the > new field with PSR2 TP2/3 wakeup time > URL : https://patchwork.freedesktop.org/series/57896/ > State : failure > > == Summary == > > CI Bug Lo

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Add support for retrying hotplug

== Series Details == Series: series starting with [1/2] drm/i915: Add support for retrying hotplug URL : https://patchwork.freedesktop.org/series/57912/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add support for retrying hotplug -drivers/

Re: [Intel-gfx] [PATCH 08/39] drm/i915: Create/destroy VM (ppGTT) for use with contexts

On Wed, Mar 13, 2019 at 08:47:41PM +, Chris Wilson wrote: > Quoting Rodrigo Vivi (2019-03-13 20:11:21) > > On Wed, Mar 13, 2019 at 02:43:30PM +, Chris Wilson wrote: > > > + /* > > > + * We need to flush any requests using the current ppgtt before > > > + * we release it as the

[Intel-gfx] ✗ Fi.CI.BAT: failure for Support 64 bpp half float formats (rev7)

== Series Details == Series: Support 64 bpp half float formats (rev7) URL : https://patchwork.freedesktop.org/series/53212/ State : failure == Summary == Applying: drm/fourcc: Add 64 bpp half float formats Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_fourcc.c M

[Intel-gfx] [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform

From: Bob Paauwe Add ElkhartLake as a unique platform as there are some differences between it and Icelake. Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_dev

[Intel-gfx] [PATCH 4/9] drm/i915/ehl: Add dpll mgr

From: Lucas De Marchi Elkhart Lake has a different set of PLLs as compared to Ice Lake, although programming them is very similar. Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++- 1 file changed, 15 insertions(+), 1 de

[Intel-gfx] [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs

From: James Ausmus Add known EHL PCI IDs. Cc: Bob Paauwe Signed-off-by: James Ausmus Signed-off-by: Rodrigo Vivi --- arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/i915_pci.c | 9 + include/drm/i915_pciids.h | 7 +++ 3 files changed, 17 insertions(+) diff --gi

[Intel-gfx] [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support

From: Bob Paauwe While EHL does support 4 level extended ppgtt, it only makes use of 36 bits instead of the 48 like the other platforms that have 4 level extended ppgtt. Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++--- 1 file changed

[Intel-gfx] [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys

From: Bob Paauwe Unlike ICL, all of the output ports are combo phys so just return true in is_port_combophy for all EHL ports to indicate that. Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a

[Intel-gfx] [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL

From: Anusha Srivatsa EHL uses the same firmware as ICL. Cc: Bob Paauwe Signed-off-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11

From: Bob Paauwe Most of the conditional code for ICELAKE also applies to ELKHARTLAKE so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now. Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_runtime_

[Intel-gfx] [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL

From: Bob Paauwe Configure the correct set of outputs for EHL. EHL has three DDI's plus MIPI. Cc: Lucas De Marchi Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/g

[Intel-gfx] [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL

From: Bob Paauwe EHL has a different number of subslices. Cc: Lucas De Marchi Signed-off-by: Bob Paauwe Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_device_info.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_

[Intel-gfx] [PATCH] drm/i915/selftests: Disable preemption while setting up fence-timers

The impossible happens and a future fence expired while we were still initialising. The probable cause is that the test was preempted and we lost our scheduler cpu slice. Disable preemption during this test to rule out preemption as a source of timer disruption. References: https://bugs.freedeskto

Re: [Intel-gfx] [PATCH 08/39] drm/i915: Create/destroy VM (ppGTT) for use with contexts

Quoting Rodrigo Vivi (2019-03-13 20:11:21) > On Wed, Mar 13, 2019 at 02:43:30PM +, Chris Wilson wrote: > > + /* > > + * We need to flush any requests using the current ppgtt before > > + * we release it as the requests do not hold a reference themselves, > > + * only indirect

[Intel-gfx] ✗ Fi.CI.IGT: failure for skl+ cursor DDB allocation fixes

== Series Details == Series: skl+ cursor DDB allocation fixes URL : https://patchwork.freedesktop.org/series/57901/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5737_full -> Patchwork_12445_full Summary --- **FAILUR

Re: [Intel-gfx] [PATCH 08/39] drm/i915: Create/destroy VM (ppGTT) for use with contexts

On Wed, Mar 13, 2019 at 02:43:30PM +, Chris Wilson wrote: > In preparation to making the ppGTT binding for a context explicit (to > facilitate reusing the same ppGTT between different contexts), allow the > user to create and destroy named ppGTT. > > v2: Replace global barrier for swapping ove

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE

On Wed, Mar 13, 2019 at 10:30:52AM -0700, Lucas De Marchi wrote: > On Fri, Mar 08, 2019 at 01:43:00PM -0800, Rodrigo Vivi wrote: > > In order to make it easier to bring up new platforms > > without having to take care about all corner cases > > that was previously taken care for previous platforms

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

On Wed, Mar 13, 2019 at 04:38:01PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] > >Sent: Tuesday, February 19, 2019 1:02 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: Shankar, Uma ; Roper, Matthew D > > > >Subject: [

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

== Series Details == Series: series starting with [v4,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time URL : https://patchwork.freedesktop.org/series/57896/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5737_full -> Patchwork_12443_full =

[Intel-gfx] [PULL] drm-misc-next-fixes

Hi Daniel, Dave, Here is what should be the last drm-misc-next-fixes PR. Thanks! Maxime drm-misc-next-fixes-2019-03-13: - qxl: Remove the conflicting framebuffers earlier - Split out some i915 code into the fb_helper to allow the above The following changes since commit e552f0851070fe4975d610

Re: [Intel-gfx] [PATCH] drm/dp: Set the connector's TILE property even for DP SST connectors

On Tue, Mar 12, 2019 at 10:15 PM Manasi Navare wrote: > > Current driver sets the tile property only for DP MST connectors. > However there are some tiled displays where each SST connector > carries a single tile. So we need to attach this property object > for every connector and set it for every

Re: [Intel-gfx] [PULL] topic/hdr-formats

On Wed, Mar 13, 2019 at 12:21:46PM +0100, Maarten Lankhorst wrote: > Hey Sean and Joonas, > > One more pull request for the hdr-formats topic branch. FP16 support > is now also implemented. > > Can this be pulled to drm-misc-next and dinq? Merged in drm-misc-next. Sean > > ~Maarten > > topic

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

Am 13.03.19 um 18:33 schrieb Michel Dänzer: > [SNIP] >>> Copy how? Using a GPU engine? >> CPU maybe? Though I suppose that won't work if the buffer isn't CPU >> accesible :/ > Well we do have a debug path for accessing invisible memory with the > CPU. > > E.g. three regi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915: Hold a ref to the ring while retiring (rev2)

== Series Details == Series: series starting with [v2] drm/i915: Hold a ref to the ring while retiring (rev2) URL : https://patchwork.freedesktop.org/series/57899/ State : success == Summary == CI Bug Log - changes from CI_DRM_5739 -> Patchwork_12446 ==

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

On 3/13/19 1:33 PM, Michel Dänzer wrote: > On 2019-03-13 5:16 p.m., Kazlauskas, Nicholas wrote: >> On 3/13/19 11:54 AM, Christian König wrote: >>> Am 13.03.19 um 16:38 schrieb Michel Dänzer: On 2019-03-13 2:37 p.m., Christian König wrote: > Am 13.03.19 um 14:31 schrieb Ville Syrjälä: >

[Intel-gfx] [PATCH i-g-t 3/5] tests/i915/i915_pm_dc: Added test for DC6 during PSR

From: Jyoti Yadav This patch add subtest to check DC6 entry on PSR for the supported platforms. v2: Rename the subtest with more meaningful name. v3: Rebased. v4: Rebased, to fix compilation error in psr_enable(). Addressed review comment by fixing typo in comment description of DC6 PSR

[Intel-gfx] [PATCH i-g-t 4/5] tests/i915/i915_pm_dc: Added test for DC5 during DPMS

From: Jyoti Yadav Added new subtest for DC5 entry during DPMS on/off cycle. During DPMS on/off cycle DC5 counter is incremented. v2: Rename the subtest with meaningful name. v3: Rebased. v4: Addressed review comments by removing leftover code cleanup(). v5: Addressed the review comment by re

[Intel-gfx] [PATCH i-g-t 5/5] tests/i915/i915_pm_dc: Added test for DC6 during DPMS

From: Jyoti Yadav Added new subtest for DC6 entry during DPMS on/off cycle. During DPMS on/off cycle DC6 counter is incremented. v2: Renamed the subtest name. v3: Rebased. v4: Addressed review comment by replacing igt_display_init() to igt_display_require(), changes got done in patch set 2.

[Intel-gfx] [PATCH i-g-t 2/5] tests/i915/i915_pm_dc: Added new test to verify Display C States

From: Jyoti Yadav Currently this test validates DC5 upon PSR entry for supported platforms. Added new file for compilation inside Makefile and Meson. v2: Used the debugfs entry for DC counters instead of Registers. Used shorter names for variables. Introduced timeout to read DC counters.

[Intel-gfx] [PATCH i-g-t 1/5] lib/igt_pm: igt lib helper routines to support DC5/6 tests

From: Jyoti Yadav dmc_loaded() will be used by new test i915_pm_dc.c which will validate Display C States. So moving the same to igt_pm library. Introduced igt_disable_runtime_pm() inorder to disable runtime suspend for the function which support dc9. v2: Simplify the comment section. v3: Remove

[Intel-gfx] [PATCH i-g-t] lib/sw_sync: Fix querying fence status

To query the fence status, and only the fence status, you only need to pass .num_fences = 0. Signed-off-by: Chris Wilson Cc: Petri Latvala --- lib/sw_sync.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/lib/sw_sync.c b/lib/sw_sync.c index f20860331..d671923c

[Intel-gfx] [PATCH i-g-t 0/5] DC states igt tests patch series v8

This patch series adds new tests to validate Display C states. DC states like DC5 and DC6 are validated during PSR entry/exit and during DPMS on/off cycle. Sending new revision of patch series after addressing review comments and other relevant changes. 1. Changing the name of test from pm_dc to

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

On 2019-03-13 5:16 p.m., Kazlauskas, Nicholas wrote: > On 3/13/19 11:54 AM, Christian König wrote: >> Am 13.03.19 um 16:38 schrieb Michel Dänzer: >>> On 2019-03-13 2:37 p.m., Christian König wrote: Am 13.03.19 um 14:31 schrieb Ville Syrjälä: > On Wed, Mar 13, 2019 at 10:35:08AM +0100, Mich

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE

On Fri, Mar 08, 2019 at 01:43:00PM -0800, Rodrigo Vivi wrote: In order to make it easier to bring up new platforms without having to take care about all corner cases that was previously taken care for previous platforms we already use comparative INTEL_GEN statements. Let's start doing the same

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

Am 13.03.19 um 17:16 schrieb Kazlauskas, Nicholas: > On 3/13/19 11:54 AM, Christian König wrote: >> Am 13.03.19 um 16:38 schrieb Michel Dänzer: >>> On 2019-03-13 2:37 p.m., Christian König wrote: Am 13.03.19 um 14:31 schrieb Ville Syrjälä: > On Wed, Mar 13, 2019 at 10:35:08AM +0100, Michel

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling > >From: Ville Syrjäl

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Clean the csc limited range/identity programming

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 6/7] drm/i915: Clean the csc limited range/identity programming > >From: V

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Extract ilk_csc_convert_ctm()

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 5/7] drm/i915: Extract ilk_csc_convert_ctm() > >From: Ville Syrjälä > >St

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming > >From: Ville

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

On Wed, Mar 13, 2019 at 03:30:43PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] > >Sent: Tuesday, February 19, 2019 1:02 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: Shankar, Uma ; Roper, Matthew D > > > >Subject: [

[Intel-gfx] [PATCH] drm/i915: Always kick the execlists tasklet after reset

With direct submission being disabled while the reset in progress, we have a small window where we may forgo the submission of a new request and not notice its addition during execlists_reset_finish. To close this window, always schedule the submission tasklet on coming out of reset to catch any re

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

On 3/13/19 11:54 AM, Christian König wrote: > Am 13.03.19 um 16:38 schrieb Michel Dänzer: >> On 2019-03-13 2:37 p.m., Christian König wrote: >>> Am 13.03.19 um 14:31 schrieb Ville Syrjälä: On Wed, Mar 13, 2019 at 10:35:08AM +0100, Michel Dänzer wrote: > On 2019-03-12 6:15 p.m., Noralf Trøn

[Intel-gfx] ✓ Fi.CI.BAT: success for skl+ cursor DDB allocation fixes

== Series Details == Series: skl+ cursor DDB allocation fixes URL : https://patchwork.freedesktop.org/series/57901/ State : success == Summary == CI Bug Log - changes from CI_DRM_5737 -> Patchwork_12445 Summary --- **SUCCESS** No

Re: [Intel-gfx] [PATCH] drm/i915/ddi: Fix default eDP detection on port A

On Thu, 07 Mar 2019, Jani Nikula wrote: > On Thu, 07 Mar 2019, Thomas Preston wrote: >> Would you like me to resubmit with the suggested changes? > > Nah, we can tweak the commit message while applying. Pushed to dinq, thanks for the patch. BR, Jani. -- Jani Nikula, Intel Open Source Graphics

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

Hi, [[ CCing John for the trylock parts ]] On Mon, Mar 11, 2019 at 11:33:15PM +0100, Noralf Trønnes wrote: > > > Den 11.03.2019 20.23, skrev Daniel Vetter: > > On Mon, Mar 11, 2019 at 06:42:16PM +0100, Noralf Trønnes wrote: > >> This adds support for outputting kernel messages on panic(). > >> A

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix PSR2 selective update corruption after PSR1 setup

== Series Details == Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup URL : https://patchwork.freedesktop.org/series/57900/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5737 -> Patchwork_12444 Summar

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

On 2019-03-12, Ahmed S. Darwish wrote: + +static void drm_panic_kmsg_dump(struct kmsg_dumper *dumper, + enum kmsg_dump_reason reason) +{ + class_for_each_device(drm_class, NULL, dumper, drm_panic_dev_iter); >>> >>> class_for_each_device uses klist

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

Am 13.03.19 um 16:38 schrieb Michel Dänzer: On 2019-03-13 2:37 p.m., Christian König wrote: Am 13.03.19 um 14:31 schrieb Ville Syrjälä: On Wed, Mar 13, 2019 at 10:35:08AM +0100, Michel Dänzer wrote: On 2019-03-12 6:15 p.m., Noralf Trønnes wrote: Den 12.03.2019 17.17, skrev Ville Syrjälä: On

Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for panic message output

On 2019-03-13 2:37 p.m., Christian König wrote: > Am 13.03.19 um 14:31 schrieb Ville Syrjälä: >> On Wed, Mar 13, 2019 at 10:35:08AM +0100, Michel Dänzer wrote: >>> On 2019-03-12 6:15 p.m., Noralf Trønnes wrote: Den 12.03.2019 17.17, skrev Ville Syrjälä: > On Tue, Mar 12, 2019 at 11:47

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for skl+ cursor DDB allocation fixes

== Series Details == Series: skl+ cursor DDB allocation fixes URL : https://patchwork.freedesktop.org/series/57901/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Accept alloc_size == blocks Okay! Commit: drm/i915: Don't pass plane state to

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range() > >From: Ville Syrjälä > >

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode Typo in precompute

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix PSR2 selective update corruption after PSR1 setup

== Series Details == Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup URL : https://patchwork.freedesktop.org/series/57900/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix PSR2 selective update corruption after PSR1

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Readout and check csc_mode

>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, February 19, 2019 1:02 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH 1/7] drm/i915: Readout and check csc_mode > >From: Ville Syrjälä > >Add t

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

== Series Details == Series: series starting with [v4,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time URL : https://patchwork.freedesktop.org/series/57896/ State : success == Summary == CI Bug Log - changes from CI_DRM_5737 -> Patchwork_12443 ===

[Intel-gfx] [PATCH 26/39] drm/i915: Move more GEM objects under gem/

Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Makefile | 25 ++- .../gpu/drm/i915/{ => gem}/i915_gem_clflush.c | 27 +++ drivers/gpu/drm/i915/gem/i915_gem_clflush.h | 20 + .../gpu/drm/i915/{

[Intel-gfx] [PATCH 37/39] drm/i915: Replace engine->timeline with a plain list

To continue the onslaught of removing the assumption of a global execution ordering, another casualty is the engine->timeline. Without an actual timeline to track, it is overkill and we can replace it with a much less grand plain list. We still need a list of requests inflight, for the simple purpo

Re: [Intel-gfx] [PATCH 35/39] drm/i915: Keep contexts pinned until after the next kernel context switch

Quoting Chris Wilson (2019-03-13 14:43:57) > We need to keep the context image pinned in memory until after the GPU > has finished writing into it. Since it continues to write as we signal > the final breadcrumb, we need to keep it pinned until the request after > it is complete. Currently we know

[Intel-gfx] [PATCH 03/39] drm/i915: Hold a reference to the active HW context

For virtual engines, we need to keep the HW context alive while it remains in use. For regular HW contexts, they are created and kept alive until the end of the GEM context. For simplicity, generalise the requirements and keep an active reference to each HW context. Signed-off-by: Chris Wilson --

[Intel-gfx] [PATCH 23/39] drm/i915: Move phys objects to its own file

Continuing the decluttering of i915_gem.c, this time the legacy physical object. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 + .../gpu/drm/i915/gem/i915_gem_object_types.h

[Intel-gfx] [PATCH 25/39] drm/i915: Move GEM domain management to its own file

Continuing the decluttering of i915_gem.c, that of the read/write domains, perhaps the biggest of GEM's follies? Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_domain.c| 764 +

[Intel-gfx] [PATCH 10/39] drm/i915: Allow contexts to share a single timeline across all engines

Previously, our view has been always to run the engines independently within a context. (Multiple engines happened before we had contexts and timelines, so they always operated independently and that behaviour persisted into contexts.) However, at the user level the context often represents a singl

[Intel-gfx] [PATCH 13/39] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]

Allow the user to specify a local engine index (as opposed to class:index) that they can use to refer to a preset engine inside the ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES. This will be useful for setting SSEU parameters on virtual engines that are local to the context

[Intel-gfx] [PATCH 19/39] drm/i915: Split GEM object type definition to its own header

For convenience in avoiding inline spaghetti, keep the type definition as a separate header. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/Makefile | 3 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 285 + .../test_i915_gem

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