== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev3)
URL : https://patchwork.freedesktop.org/series/58299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12540
== Series Details ==
Series: series starting with [1/5] drm/i915: Enable transition watermarks for
glk (rev2)
URL : https://patchwork.freedesktop.org/series/56859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5784_full -> Patchwork_12536_full
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev3)
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_chann
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev3)
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
77f4b2fd475a drm/i915: Turn dram_info.num_channels into a bit
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev2)
URL : https://patchwork.freedesktop.org/series/58299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12539
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev2)
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_chann
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask (rev2)
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f4885c7c00de drm/i915: Turn dram_info.num_channels into a bit
Hi,
Sorry that I might miss 5.1-rc1 window as I was in full day event
during this week. Here's re-generated gvt-fixes against
drm-intel-fixes. This contains fixes for newer version of Windows
driver, e.g fixing parser for MI_FLUSH_DW command and fixed windows
font render error, with other stable
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev2)
URL : https://patchwork.freedesktop.org/series/58081/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12538
Summary
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev2)
URL : https://patchwork.freedesktop.org/series/58081/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e6d81755e1a drm/i915/icl: Fix clockgating issue when using scalers
-:55: CHECK:PARENTH
On Wed, Mar 20, 2019 at 03:26:54PM -0700, Jose Souza wrote:
Please sync(copy) the whole file, there is other PCI id additions in
kernel that are missed in here, the same for your lib drm patch.
and the commit message should be that you are synchronizing the kernel
header. See e.g. b2920f54 ("li
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
Cc: Chris Wilson
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Aditya Swarup
Signed-off-by: Radhakrishna Sripada
---
dri
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5781_full -> Patchwork_12531_full
=
Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:42)
> Save some uncore properties to avoid having to jump back to
> dev_priv every time
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
I wanted to push "always use flags" separately just to have a better
look at whether we survived,
Quoting Chris Wilson (2019-03-20 12:35:51)
> The cost of the extra flushes is a worry, but not enough for me to be
> concerned about. I think the convention that get_pages == coherent on
> gpu improves quite a bit of our internal rummaging around and prevents
> the ABI nightmare of mmap_gtt/mmap_of
From: "Venkata Sandeep, Dhanalakota"
Sparse object is a proxy object that can link the pages from
other objects. Typical use case are huge continuos framebuffer
that is too big to handle scanout. Sparse object can used as
any other regular object after the pages from source object
are linked.
Thi
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask
URL : https://patchwork.freedesktop.org/series/58299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5784 -> Patchwork_12537
===
== Series Details ==
Series: series starting with [1/5] drm/i915: Enable transition watermarks for
glk (rev2)
URL : https://patchwork.freedesktop.org/series/56859/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5784 -> Patchwork_12536
==
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_channels int
== Series Details ==
Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
bitmask
URL : https://patchwork.freedesktop.org/series/58299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cf425d8d7a31 drm/i915: Turn dram_info.num_channels into a bitmask
8d
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: use intel_uncore in fw get/put
internal paths
URL : https://patchwork.freedesktop.org/series/58295/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5784 -> Patchwork_12534
=
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI
IDs (rev3)
URL : https://patchwork.freedesktop.org/series/57959/
State : failure
== Summary ==
Applying: drm/i915/ehl: Add EHL platform info and PCI IDs
Using index info to reconstruct a base t
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: use intel_uncore in fw get/put
internal paths
URL : https://patchwork.freedesktop.org/series/58295/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: use intel_uncore in fw ge
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: use intel_uncore in fw get/put
internal paths
URL : https://patchwork.freedesktop.org/series/58295/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4cfa03897df drm/i915: use intel_uncore in fw get/put internal
On Mon, Mar 18, 2019 at 06:13:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Provide a separate .color_check() for BDW+ where we currently
> provide the split gamma mode etc.
>
> Signed-off-by: Ville Syrjälä
Patches #5-7:
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/int
On Mon, Mar 18, 2019 at 06:13:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We now bypass the legacy LUT when it's not needed, so
> no point in filling it up with a linear LUT.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_color.c |
On Mon, Mar 18, 2019 at 06:13:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't load the linear degamma LUT on ICL. The hardware no longer
> has any silly linkages between the CSC enable and degamma LUT
> enable so the degamma LUT is only needed when it's actually
> enabled.
>
> A
On Mon, Mar 18, 2019 at 06:13:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With everything else moved out of the way only ilk+
> remains using _intel_color_check(). Streamline the logic
> into ilk_color_check().
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_
== Series Details ==
Series: lib: Add PCI IDs for Comet Lake
URL : https://patchwork.freedesktop.org/series/58302/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5784 -> IGTPW_2674
Summary
---
**FAILURE**
Serious u
On Wed, Mar 20, 2019 at 05:31:07PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 20, 2019 at 08:14:56AM -0700, Matt Roper wrote:
> > On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> > > On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > > > On Mon, Mar 18, 2019 at 06:13:08P
Please sync(copy) the whole file, there is other PCI id additions in
kernel that are missed in here, the same for your lib drm patch.
On Wed, 2019-03-20 at 15:00 -0700, Anusha wrote:
> From: Anusha Srivatsa
>
> Sync PCI IDs with that of kernel.
>
> Cc: Lucas De Marchi
> Signed-off-by: Anusha S
From: Anusha Srivatsa
Sync PCI IDs with that of kernel.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
lib/i915_pciids.h | 28 +++-
lib/intel_device_info.c | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/i915_pciids.h b/lib/i91
Add PCI IDS for CML. Sync the iDS with that
of kernel.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
intel/i915_pciids.h | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
index d2fad7b0..3c960703 1
From: Ville Syrjälä
ICL has so many planes that it can easily exceed the maximum
effective memory bandwidth of the system. We must therefore check
that we don't exceed that limit.
The algorithm is very magic number heavy and lacks sufficient
explanation for now. We also have no sane way to query
From: Ville Syrjälä
We want to know out which channels are actually occupied so that
later on we can read the memory timings from the right registers.
To that end convert num_channels into a bitmask.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 28 +++-
On Wed, 2019-03-20 at 14:15 -0700, Bob Paauwe wrote:
> Unlike ICL, all of the output ports are combo phys so just return
> true in intel_port_is_combophy for all EHL ports to indicate that.
>
> v2: Return false in intel_port_is_tc since no EHL ports are TC.
> (Jose)
Reviewed-by: José Roberto de S
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/
From: Daniele Ceraolo Spurio
Now that the internal code all works on intel_uncore, flip the
external-facing interface.
v2: fix GVT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msg
From: Daniele Ceraolo Spurio
This allows us to ditch i915 in some more places.
v2: use local var in check_vgpu (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/2019031918
From: Daniele Ceraolo Spurio
Remove unneeded usage of dev_priv from 1 extra function.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-6-daniele.ceraolospu...
From: Daniele Ceraolo Spurio
Get/put functions used outside of uncore.c are updated in the next
patch for a nicer split.
v2: use dev_priv where we still have it (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https:
From: Daniele Ceraolo Spurio
Move the init, fini, prune, suspend, resume function to work on
intel_uncore instead of dev_priv.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/201
From: Daniele Ceraolo Spurio
This will allow futher simplifications in the uncore handling.
v2: move register access setup under uncore (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patch
From: Daniele Ceraolo Spurio
Use a local variable where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-7-daniele.ceraolospu...@intel.com
---
Quoting Ville Syrjälä (2019-03-20 19:26:29)
> On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> > Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> > igt_device")
> > Signed-off-by: Chris Wilson
Hi Dave and Daniel,
Here goes the first round of fixes for 5.1-rc cycle.
I will be out on vacation next week, so next week's pull request
might come from Jani. Although things looks calm right now.
only 3 patches on top of -rc1:
drm-intel-fixes-2019-03-20:
A protection on our mmap against atte
== Series Details ==
Series: drm/i915: always use masks on FW regs
URL : https://patchwork.freedesktop.org/series/58246/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12530_full
Summary
---
**S
On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> igt_device")
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> ---
> tests/i915/gem_shrink
Pushed to dinq, thanks for the review!
Regards
Manasi
On Wed, Mar 20, 2019 at 11:17:49AM +0200, Jani Nikula wrote:
> On Tue, 19 Mar 2019, Manasi Navare wrote:
> > This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> > to correctly do the left shifting to set the port sync
> > master select
Thanks for checking, appreciate it.
-DK
> -Original Message-
> From: Runyan, Arthur J
> Sent: Wednesday, March 20, 2019 11:58 AM
> To: Souza, Jose ; Vivi, Rodrigo
> ; Pandiyan, Dhinakaran
>
> Cc: Aigal, Pavana A ; 'intel-
> g...@lists.freedesktop.org'
> Subject: RE: [PATCH] drm/i915: Fi
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12529_full
==
PSR2 logic is incorrectly looking at this register bit during DC5 exit.
Not a DMC problem, but DMC enables DC5.
I'll update Bspec to require the bit to be not set when PSR2 is used.
> -Original Message-
> From: Runyan, Arthur J
> Sent: Tuesday, 12 March, 2019 4:42 PM
> To: Souza, Jose ; V
Quoting Chris Wilson (2019-03-04 09:43:43)
> Quoting Andy Shevchenko (2019-03-04 09:29:07)
> > Switch to bitmap_zalloc() to show clearly what we are allocating.
> > Besides that it returns pointer of bitmap type instead of opaque void *.
> >
> > Signed-off-by: Andy Shevchenko
> Reviewed-by: Chris
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5781 -> Patchwork_12531
===
== Series Details ==
Series: drm/i915: Use __is_constexpr()
URL : https://patchwork.freedesktop.org/series/58278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ae1e5b1f498 drm/i915: Use __is_constexpr()
-:38: WARNING:LONG_LINE: line over 100 characters
#38: FILE: drivers/gpu/d
>-Original Message-
>From: Syrjala, Ville
>Sent: Tuesday, March 19, 2019 10:29 PM
>To: Lankhorst, Maarten
>Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>Sharma, Shashank ; Roper, Matthew D
>
>Subject: Re: [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
>
>On Tue, M
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Force 2*96
Thank you very much for your reply. Do you mean if I track the argument to the
callers, I should be able to figure out that the pin is always valid? I think I
have two questions for this approach. First, does it mean that the branch
returning NULL is practically dead code? Second, the driver cod
On 3/20/19 8:40 AM, Chris Wilson wrote:
> gcc-4.8 and older dislike the use of __builtin_constant_p() within a
> constant expression context, and so we must use the magical
> __is_constexpr() instead.
>
> For example, with gcc-4.8.5:
> ../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argume
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
igt_device")
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
---
tests/i915/gem_shrink.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --
Op 20-03-2019 om 16:48 schreef Adam Jackson:
> On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote:
>> There has unfortunately been a conflict with the following 3 commits:
>>
>> commit e9961ab95af81b8d29054361cd5f0c575102cf87
>> Author: Ayan Kumar Halder
>> Date: Fri Nov 9 17:21:12 2018
On 19/03/2019 11:57, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the
From: Ville Syrjälä
The hardware never sees the uv_wm values (apart from
uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
is no point in comparing uv_wm to determine if we need to
reprogram the watermark registers. So let's check only the
rgb/y watermark in skl_plane_wm_equals(). But
On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORMAT_XVYU
gcc-4.8 and older dislike the use of __builtin_constant_p() within a
constant expression context, and so we must use the magical
__is_constexpr() instead.
For example, with gcc-4.8.5:
../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argument to
‘__builtin_choose_expr’ not a constant
../inc
On Wed, Mar 20, 2019 at 08:14:56AM -0700, Matt Roper wrote:
> On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> >
On Tue, Mar 19, 2019 at 01:29:58PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > To allow unsetting .is_mobile for the desktop variant
> > of PNV fix up the cdclk code to select the mobile HPLLVCO register
> > for both PNV variants.
>
On Mon, Mar 18, 2019 at 05:10:49PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:42PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Clean up skl_allocate_pipe_ddb() a bit by moving the 'wm' variable
> > to tighter scope. We'll also consitify it where appropriate.
> >
> >
On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > In prepartion for per-platform color_check() functions extract the
On Mon, 18 Mar 2019 at 08:58, Chris Wilson wrote:
>
> Signed-off-by: Chris Wilson
Should do the trick,
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
== Series Details ==
Series: drm/i915: always use masks on FW regs
URL : https://patchwork.freedesktop.org/series/58246/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12530
Summary
---
**SUCCESS**
Chris Wilson writes:
> Don't try to evaluate whether reads executed on an absent ring do
> anything.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_mocs_settings.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/gem_m
On Mon, Mar 18, 2019 at 07:05:29PM -0300, Rodrigo Siqueira wrote:
> On 03/18, Liviu Dudau wrote:
> > On Wed, Mar 06, 2019 at 06:30:05PM -0300, Rodrigo Siqueira wrote:
> > > Hi Liviu,
> > >
> > > I’m using your patchset to guide my implementation of writeback in the
> > > VKMS, so, first of all, th
On Tue, Mar 19, 2019 at 06:24:47PM +0200, Jani Nikula wrote:
> On Mon, 18 Mar 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Tue, Mar 19, 2019 at 03:00:26PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:11PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Since CHV has the CGM unit we require a custom implementation
> > of .color_check().
> >
> > This fixes the computation of gamma_enable as
On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville S
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12529
Su
On Wed, 20 Mar 2019 at 12:36, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 12:26:00)
> > On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> > >
> > > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > > wrote:
> > > > > @@ -2534,6 +2
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev6)
URL : https://patchwork.freedesktop.org/series/25091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12528
Summary
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe
We copied the original state into the atomic state already earlier in
the function, so no need to do it a second time.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu
The old state will be needed by an upcoming patch to determine if the
commit increases or decreases CDCLK, so move the old state to the atomic
state (while keeping the new one in dev_priv). cdclk.logical and
cdclk.actual in the atomic state isn't used atm anywhere after the
atomic check phase, so t
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to a
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev6)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ffebb6ddcbf drm: Add HDR source metadata property
6d0a7b41e79c drm: Parse HDR metadata inf
== Series Details ==
Series: drm/i915/selftests: Mark up preemption tests for hang detection
URL : https://patchwork.freedesktop.org/series/58236/
State : failure
== Summary ==
Applying: drm/i915/selftests: Mark up preemption tests for hang detection
Using index info to reconstruct a base tree
== Series Details ==
Series: drm/i915: Ensure minimum CDCLK requirement for audio (rev4)
URL : https://patchwork.freedesktop.org/series/58132/
State : failure
== Summary ==
Applying: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
Applying: drm/i915: Skip modeset for cdcl
On 19/03/2019 11:57, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on vi
On 19/03/2019 11:57, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance)
On 19/03/2019 11:57, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy
On 19/03/2019 11:57, Chris Wilson wrote:
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
On 19/03/2019 11:57, Chris Wilson wrote:
The timeline->name is only used for convenience in pretty printing the
i915_request.fence->ops->get_timeline_name() and it is just as
convenient to pull it from the gem_context directly. The few instances
of its use inside GEM_TRACE() has proven more of a
Quoting Matthew Auld (2019-03-20 12:26:00)
> On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > wrote:
> > > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > > drm_i915
From: Daniele Ceraolo Spurio
Upper bits are reserved on gen6, so no issue if we write them. Note that
we're already doing this in the non-MT case of IVB, which uses the same
register.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Reviewed-b
On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 11:41:52)
> > On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > drm_i915_gem_object *obj,
> > >
> > > lockdep_assert_held(&obj
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Imre
>Deak
>Sent: Wednesday, March 20, 2019 4:38 PM
>To: Kulkarni, Vandita
>Cc: Nikula, Jani ; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix
>-Original Message-
>From: Kulkarni, Vandita
>Sent: Wednesday, March 20, 2019 3:39 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani ; Shankar, Uma ;
>Chauhan, Madhav ; Kulkarni, Vandita
>
>Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
You can drop dsi from commit
Quoting Matthew Auld (2019-03-20 11:41:52)
> On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > drm_i915_gem_object *obj,
> >
> > lockdep_assert_held(&obj->mm.lock);
> >
> > + /* Make the pages coherent with the G
On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
>
> When we return pages to the system, we ensure that they are marked as
> being in the CPU domain since any external access is uncontrolled and we
> must assume the worst. This means that we need to always flush the pages
> on acquisition if we n
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
Quoting Chris Wilson (2019-03-19 18:59:04)
> Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:33)
> > Compared to v1 [1], there is a new patch for further simplification of
> > low-level fw get/put by always using the bitmasks since the upper bits
> > of the fw reg are reserved on gen6 and I couldn
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