== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12641_full
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12640_full
Summary
---
**S
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures (rev2)
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12639_full
Su
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12641
Summary
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5839_full -> Patchwork_12636_full
Summary
-
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12640
Summary
---
**SUCCESS**
No functional change. Renaming the function to reflect the specific WA.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/in
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
V5: Split
RMW is used only in the disable path. Using it in enable path
for consistency.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3f3b4a23cc5 drm/i915: Engine relative MMIO
-:89: ERROR:SPACING: space prohibited after that open parenthesis '
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures (rev2)
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12639
Summary
Quoting Patchwork (2019-03-30 00:34:48)
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_gttfill@basic:
> - {fi-icl-guc}: NOTRUN -> SKIP
What CI doesn't say is that in th
== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12638
Summary
---
**FAI
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12637
Summary
---
**FAILURE**
Serious unknown changes c
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engi
== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a8460dd85471 drm/i915: add immutable zpos plane properties
-:75: WARNING:NO_AUTHOR_SIGN_OFF: Missing Si
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Don't allow GuC submission on pre-Gen11
Okay!
Commit: drm/i915/guc: Simplify preparation of GuC
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
07625b512895 drm/i915/guc: Don't allow GuC submission on pre-Gen11
a79bbfbbcaeb drm/i915/guc: Simplify preparation of GuC parameter block
Currently we only retry to load GuC firmware if the load fails due to
timeout. On Gen9 GuC loading may fail for different reasons, not just
hang/timeout. Direction from the GuC team is to retry for all cases of
GuC load failure on Gen9, not just for timeout.
Bugzilla: https://bugs.freedesktop.org/
On Fri, 2019-03-29 at 20:39 +0200, Ville Syrjälä wrote:
> On Thu, Mar 28, 2019 at 10:35:19AM -0700, Radhakrishna Sripada wrote:
> > Fixes the clock-gating issue when pipe scaling is enabled.
> > (Lineage #2006604312)
> >
> > V2: Fix typo in headline(Chris)
> > Handle the non double buffered na
Quoting Michal Wajdeczko (2019-03-29 22:11:16)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3dd971c09d52..c1b4fbd5f496 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -573,6 +573,44 @@ static void gen9_disable_g
Quoting Michal Wajdeczko (2019-03-29 22:11:08)
> From: Oscar Mateo
>
> The new context descriptor format contains two assignable fields:
> the SW Context ID (technically 11 bits, but practically limited to 2032
> entries due to some being reserved for future use by the GuC) and the
> SW Counter (
From: emersion
This adds basic immutable support for the zpos property. The zpos increases
from bottom to top: primary, sprites, cursor.
Signed-off-by: Simon Ser
---
This is based on a previous patch by Ville [1] that I wanted to review.
Unfortunately the patch no longer applies, so here is a
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/g
Since fw version 25.161, GuC lets us know when an engine had to be reset
due to a hang in another dependent engine, by setting BIT(engine_class) in
the queue_engine_error field. GuC will ignore any other wq item until this
flag is cleared.
To restart the workqueue processing for that engine, we mu
From: Oscar Mateo
With the new interrupt re-partitioning in Gen11, GuC controls by itself
the interrupts it receives, so steering bits and registers have been
defeatured. Being this the case, when the GuC is in control of
submissions we won't know what to do with the ctx switch interrupt
in the d
From: Daniele Ceraolo Spurio
Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dereferences in some existing GuC
functions that use the guc_id to dereference arrays but these functio
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko Ursuli
From: Oscar Mateo
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belg
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gp
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal W
From: Oscar Mateo
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files cha
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: MichaĹ Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.h | 2
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
Format of the ENGINE_RESET H2G message has been updated. Additionally,
the firmware will send a G2H ENGINE_RESET_COMPLETE message (with the
engine's guc_class in data[2]) to confirm that the reset has been
completed (but this will be handled in a other patch).
Co-Developed-by: Michel Thierry
Sign
Work queue items definitions were updated.
To simplify the scheduling logic in the GuC firmware,
only out-of-order mode of scheduling is now supported.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał Winia
From: Daniele Ceraolo Spurio
With the new interface, GuC now requires every lrc to be registered in
one of the stage descriptors, which have been re-designed so that each
descriptor can store up to 64 lrc per class (i.e. equal to the possible
SW counter values).
Similarly to what happened with th
For now, we only want to test "enable_guc=2" configuration.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/d
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel
Some Gen9 CI systems are still prepared to run no longer supported
configuration "enable_guc=3"
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1e7a
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: John Spotswood
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc.c
New GuC firmwares require updated boot parameters.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 36 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Jeff Mcgee
--
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_submission.c | 4
drivers/gpu/drm/i915/intel_uc.
There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 6 ++
2 files
New GuC firmwares use updated sleep status definitions.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/in
Due to the GuC interface changes, new firmware releases will
stop support GuC submission mode for pre-Gen11 platforms.
Sanitize the enable_guc option so that only HuC authentication
would be possible.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spuri
New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface.
Gen9 will only support HuC authentication.
GuC submission is optional only for Gen11.
Note: we're seeing some issues on specific machines, compare [1] and [2]
[1]
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4030/fi-icl-g
== Series Details ==
Series: drm/i915: Always backoff after a drm_modeset_lock() deadlock
URL : https://patchwork.freedesktop.org/series/58753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12635_full
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5839 -> Patchwork_12636
Summary
---
== Series Details ==
Series: drm/i915: fix i9xx irq enable/disable (rev2)
URL : https://patchwork.freedesktop.org/series/58748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12634_full
Summary
---
Quoting Robert M. Fosha (2019-03-29 20:36:09)
> Currently we only retry to load GuC firmware if the load fails due to
> timeout. On Gen9 GuC loading may fail for different reasons, not just
> hang/timeout. Direction from the GuC team is to retry for all cases of
> GuC load failure on Gen9, not just
Currently we only retry to load GuC firmware if the load fails due to
timeout. On Gen9 GuC loading may fail for different reasons, not just
hang/timeout. Direction from the GuC team is to retry for all cases of
GuC load failure on Gen9, not just for timeout.
Signed-off-by: Robert M. Fosha
Cc: Dan
== Series Details ==
Series: drm/i915: Move the decision to use the breadcrumb tasklet to the backend
URL : https://patchwork.freedesktop.org/series/58745/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12632_full
=
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> + spin_lock(&engine->i915->vgpu.shared_page_lock);
> + shared_page->ring_id = engine->id;
> + for (n = 0; n < execlists_num_ports(execlists); n++)
> + shared_page->descs[n] = descs[n];
> +
> + __raw_i915_write32(unc
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff (rev2)
URL : https://patchwork.freedesktop.org/series/58698/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12631_full
Summary
---
On Fri, Mar 29, 2019 at 04:51:52PM +, Chris Wilson wrote:
> If drm_modeset_lock() reports a deadlock it sets the ctx->contexted
> field and insists that the caller calls drm_modeset_backoff() or else it
> generates a WARN on cleanup.
I call the drm_modeset_backoff() for the second
drm_modeset_
On Thu, Mar 28, 2019 at 10:35:19AM -0700, Radhakrishna Sripada wrote:
> Fixes the clock-gating issue when pipe scaling is enabled.
> (Lineage #2006604312)
>
> V2: Fix typo in headline(Chris)
> Handle the non double buffered nature of the register(Ville)
> V3: Fix checkpatch warning. BAT failur
On Fri, Mar 29, 2019 at 07:59:14PM +0530, Uma Shankar wrote:
> Register offsets used to program GC max were not correct. This series
> fixes the same, also limits the values to accurately clamp at 1.0.
> Also added support to program EXT2 GC Max needed for values from 3.0
> to 7.0. Limiting it agai
== Series Details ==
Series: drm/i915: Always backoff after a drm_modeset_lock() deadlock
URL : https://patchwork.freedesktop.org/series/58753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12635
Summary
-
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12630_full
Summ
Quoting Patchwork (2019-03-29 17:54:17)
> == Series Details ==
>
> Series: drm/i915: fix i9xx irq enable/disable (rev2)
> URL : https://patchwork.freedesktop.org/series/58748/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12634
> ===
== Series Details ==
Series: drm/i915: Always backoff after a drm_modeset_lock() deadlock
URL : https://patchwork.freedesktop.org/series/58753/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ca38f8d7b726 drm/i915: Always backoff after a drm_modeset_lock() deadlock
-:10: WARNING:
== Series Details ==
Series: drm/i915: fix i9xx irq enable/disable (rev2)
URL : https://patchwork.freedesktop.org/series/58748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12634
Summary
---
**SUCC
Op 29-03-2019 om 10:20 schreef Daniel Vetter:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Um
== Series Details ==
Series: drm/i915: fix i9xx irq enable/disable
URL : https://patchwork.freedesktop.org/series/58748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12633
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12629_full
=
If drm_modeset_lock() reports a deadlock it sets the ctx->contexted
field and insists that the caller calls drm_modeset_backoff() or else it
generates a WARN on cleanup.
<4> [1601.870376] WARNING: CPU: 3 PID: 8445 at
drivers/gpu/drm/drm_modeset_lock.c:228 drm_modeset_drop_locks+0x35/0x40
<4> [160
== Series Details ==
Series: drm/i915: Move the decision to use the breadcrumb tasklet to the backend
URL : https://patchwork.freedesktop.org/series/58745/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12632
===
Quoting Daniele Ceraolo Spurio (2019-03-29 16:41:55)
>
>
> On 3/29/19 9:32 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
> >> Those functions are used on gen4 as well and gen4 does have a non-RCS
> >> engine, so remove the BUG_ON and flip back the logic to what
Those functions are used on gen4 as well and gen4 does have a non-RCS
engine, so remove the BUG_ON and flip back the logic to what it was
before the ENGINE_READ/WRITE update
v2: update the posting read as well (Chris, Ville).
Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engin
On 3/29/19 9:32 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
Those functions are used on gen4 as well and gen4 does have a non-RCS
engine, so remove the BUG_ON and flip back the logic to what it was
before the ENGINE_READ/WRITE update
Oh, silly me, gm45.
F
On Fri, Mar 29, 2019 at 09:19:00AM -0700, Daniele Ceraolo Spurio wrote:
> Those functions are used on gen4 as well and gen4 does have a non-RCS
> engine, so remove the BUG_ON and flip back the logic to what it was
> before the ENGINE_READ/WRITE update
>
> Fixes: baba6e572b38 ("drm/i915: take a ref
Quoting Daniele Ceraolo Spurio (2019-03-29 16:20:48)
>
>
> On 3/29/19 9:19 AM, Daniele Ceraolo Spurio wrote:
> > Those functions are used on gen4 as well and gen4 does have a non-RCS
> > engine, so remove the BUG_ON and flip back the logic to what it was
> > before the ENGINE_READ/WRITE update
>
Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
> Those functions are used on gen4 as well and gen4 does have a non-RCS
> engine, so remove the BUG_ON and flip back the logic to what it was
> before the ENGINE_READ/WRITE update
Oh, silly me, gm45.
> Fixes: baba6e572b38 ("drm/i915: take a re
On 3/29/19 9:19 AM, Daniele Ceraolo Spurio wrote:
Those functions are used on gen4 as well and gen4 does have a non-RCS
engine, so remove the BUG_ON and flip back the logic to what it was
before the ENGINE_READ/WRITE update
Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engi
== Series Details ==
Series: drm: prefix header search paths with $(srctree)/ (rev2)
URL : https://patchwork.freedesktop.org/series/56020/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12627_full
Summ
Those functions are used on gen4 as well and gen4 does have a non-RCS
engine, so remove the BUG_ON and flip back the logic to what it was
before the ENGINE_READ/WRITE update
Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and
use it")
Signed-off-by: Daniele Ceraolo Spurio
Quoting Xiaolin Zhang (2019-03-29 13:32:36)
> To improve vgpu performance, it could implement some PV optimization
> such as to reduce the mmio access trap numbers or eliminate certain piece
> of HW emulation within guest driver to reduce vm exit/vm enter cost.
Where's the CI for this patchset? Th
On 3/29/19 10:20 AM, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Um
Use the engine->flags to store whether we want to kick the submission
tasklet on receipt of a breadcrumb interrupt, so that this decision can
be made by the submission backend and not dependent on a limited feature
test within the interrupt handler. This should make it easier to adapt
different sub
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f78829..28e8ee0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -37,6 +37,7 @@
> #include "i915_drv.h"
> #include "i915
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff (rev2)
URL : https://patchwork.freedesktop.org/series/58698/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12631
Summary
---
**SUCCE
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
On 3/28/19 8:18 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20190328:
>
> The pidfd tree lost its build failures.
>
on x86_64, when # CONFIG_ACPI is not set/enabled:
ld: drivers/gpu/drm/i915/intel_panel.o: in function
`intel_backlight_device_register':
intel_panel.c:(.text+0x2c49)
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12630
Summary
--
>-Original Message-
>From: Landwerlin, Lionel G
>Sent: Friday, March 29, 2019 8:00 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma
>luts
>
>On 29/03/2019 14:29
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
88164253880f drm/i915: Fix GCMAX color register programming
cad25ef86aee drm/i915: Program EX
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
On 29/03/2019 14:29, Uma Shankar wrote:
Register offsets used to program GC max were not correct. This series
fixes the same, also limits the values to accurately clamp at 1.0.
Also added support to program EXT2 GC Max needed for values from 3.0
to 7.0. Limiting it again to 1.0 due to ABI limitat
On 29/03/2019 09:20, Daniel Vetter wrote:
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0x.
Cc: Uma Shankar
Cc: V
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
On Fri, Mar 29, 2019 at 08:32:41PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> t
Quoting Patchwork (2019-03-29 14:16:21)
> == Series Details ==
>
> Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
> URL : https://patchwork.freedesktop.org/series/58738/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12629
>
1 - 100 of 147 matches
Mail list logo
