== Series Details ==
Series: GuC 32.0.3 (rev3)
URL : https://patchwork.freedesktop.org/series/58760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926_full -> Patchwork_12789_full
Summary
---
**SUCCESS**
No regre
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926_full -> Patchwork_12787_full
S
== Series Details ==
Series: drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead (rev2)
URL : https://patchwork.freedesktop.org/series/59363/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5925_full -> Patchwork_12786_full
==
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is a
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.
I don't see any inject_load_failure() in the guc paths (WOPCM aside).
Can you sprinkle a few of them around to make sure this is solid?
Thanks,
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Tomasz Lis
---
== Series Details ==
Series: GuC 32.0.3 (rev3)
URL : https://patchwork.freedesktop.org/series/58760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926 -> Patchwork_12789
Summary
---
**SUCCESS**
No regressions fou
== Series Details ==
Series: series starting with [1/2] drm/i915: Teach intel_workarounds to use
uncore mmio access
URL : https://patchwork.freedesktop.org/series/59421/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5924_full -> Patchwork_12785_full
==
== Series Details ==
Series: GuC 32.0.3 (rev3)
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Change platform default GuC mode
Okay!
Commit: drm/i915/guc: Don't allow GuC submission
O
On 4/12/19 5:06 PM, Daniele Ceraolo Spurio wrote:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
New GuC firmwares use updated sleep status definitions.
There is also no need to poll on resume anymore. We're not failing on it
in CI because the wait timeout comes out as a debug message and t
From: Michal Wajdeczko
New GuC firmwares use updated sleep status definitions.
The polling on scratch register 14 is also now required only on suspend
and there is no need to provide the shared page.
v2: include changes for polling and shared page
Signed-off-by: Michal Wajdeczko
Signed-off-by:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
New GuC firmwares use updated sleep status definitions.
There is also no need to poll on resume anymore. We're not failing on it
in CI because the wait timeout comes out as a debug message and the guc
is obviously still fine and responsive since
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59424/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5926 -> Patchwork_12788
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
New GuC firmwares require updated boot parameters.
Matches the FW headers.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
--
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926 -> Patchwork_12787
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915: Flatten and rename
haswell_set_pipemisc()
URL : https://patchwork.freedesktop.org/series/59419/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5924_full -> Patchwork_12784_full
==
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59424/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/bdw+: Move misc d
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59424/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f0a6bbb4f8c drm/i915/bdw+: Move misc display IRQ han
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: refactor the IRQ init/reset macros
+drivers/gpu/drm/i
On Fri, Apr 12, 2019 at 10:45:16PM +, Souza, Jose wrote:
> On Fri, 2019-04-12 at 15:40 -0700, Rodrigo Vivi wrote:
> > On Fri, Apr 12, 2019 at 03:29:07PM -0700, José Roberto de Souza
> > wrote:
> > > Just moving it to reduce the tabs and avoid break code lines.
> > > No behavior changes intended
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.
AFAICS GuC loading is also broken between patch 4 and patch 9 (i.
On Fri, 2019-04-12 at 15:40 -0700, Rodrigo Vivi wrote:
> On Fri, Apr 12, 2019 at 03:29:07PM -0700, José Roberto de Souza
> wrote:
> > Just moving it to reduce the tabs and avoid break code lines.
> > No behavior changes intended here.
>
> this function is indeed big and deserves a split.
> I wonde
On Fri, Apr 12, 2019 at 03:29:09PM -0700, José Roberto de Souza wrote:
> PSR registers are a mess, some have the full address while others just
> have the additional offset from psr_mmio_base.
>
> psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
> using it makes more difficult
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-
On Fri, Apr 12, 2019 at 03:29:08PM -0700, José Roberto de Souza wrote:
> i915 does not support enabling PSR on any transcoder other than eDP.
> Clean up the misleading non-eDP code that currently exists to allow
> for the rework of PSR register definitions in the next patch.
>
> v2:
> - Commit mes
On Fri, Apr 12, 2019 at 03:29:07PM -0700, José Roberto de Souza wrote:
> Just moving it to reduce the tabs and avoid break code lines.
> No behavior changes intended here.
this function is indeed big and deserves a split.
I wonder why haven't you moved the entire de_misc block to a separated
funct
== Series Details ==
Series: drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead (rev2)
URL : https://patchwork.freedesktop.org/series/59363/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5925 -> Patchwork_12786
i915 does not support enabling PSR on any transcoder other than eDP.
Clean up the misleading non-eDP code that currently exists to allow
for the rework of PSR register definitions in the next patch.
v2:
- Commit message updated (Rodrigo and Dhinakaran)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
S
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
v2:
- Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
other irq handlers (Dhinakaran)
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_ir
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
using it makes more difficult for people with an PSR register address
from BSpec to search the register name in
On Fri, Apr 12, 2019 at 12:27:46PM -0700, Souza, Jose wrote:
> On Fri, 2019-04-12 at 11:09 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > v2:
Quoting Daniele Ceraolo Spurio (2019-04-12 22:45:29)
>
>
> On 4/12/19 1:24 PM, Chris Wilson wrote:
> > @@ -924,27 +924,22 @@ wa_list_apply(struct drm_i915_private *dev_priv,
> > const struct i915_wa_list *wal)
> > if (!wal->count)
> > return;
> >
> > - fw = wal_get_fw_
== Series Details ==
Series: drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
URL : https://patchwork.freedesktop.org/series/59364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12783_full
Summa
On 4/12/19 1:24 PM, Chris Wilson wrote:
Start weaning ourselves off the implicit I915_WRITE macro madness and
start using the explicit intel_uncore mmio access.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_worka
This is one of the patches to start replacing drm pointers
and use the intel_atomic_state and intel_crtc to derive
the necessary intel state variables required for the intel
modeset functions.
v2:
* Flip the function arguments (Ville)
* Remove some remaining instances of drm pointers (Ville)
* Use
Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore (rev2)
> URL : https://patchwork.freedesktop.org/series/59202/
> State : success
So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
ema
== Series Details ==
Series: series starting with [1/2] drm/i915: Teach intel_workarounds to use
uncore mmio access
URL : https://patchwork.freedesktop.org/series/59421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5924 -> Patchwork_12785
Immediately after writing the workaround, verify that it stuck in the
register.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 +---
1 file changed, 18 insertion
Start weaning ourselves off the implicit I915_WRITE macro madness and
start using the explicit intel_uncore mmio access.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_workarounds.c | 65 +--
drive
== Series Details ==
Series: series starting with [1/2] drm/i915: Shortcut readiness to reset check
(rev3)
URL : https://patchwork.freedesktop.org/series/59413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12782_full
===
On Fri, Apr 12, 2019 at 09:11:58AM +0300, Ville Syrjälä wrote:
> On Thu, Apr 11, 2019 at 04:02:54PM -0700, Manasi Navare wrote:
> > This is one of the patches to start replacing drm pointers
> > and use the intel_atomic_state and intel_crtc to derive
> > the necessary intel state variables required
== Series Details ==
Series: series starting with [1/2] drm/i915: Flatten and rename
haswell_set_pipemisc()
URL : https://patchwork.freedesktop.org/series/59419/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5924 -> Patchwork_12784
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12780_full
===
On Fri, 2019-04-12 at 11:09 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe
>
> Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
> v2: - Rename commit (Jose)
> - Include a wm workaround (Jose and Lucas)
>
== Series Details ==
Series: drm: Add detection of changing of edid on between suspend and resume
(rev3)
URL : https://patchwork.freedesktop.org/series/59352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12778_full
=
== Series Details ==
Series: drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
URL : https://patchwork.freedesktop.org/series/59364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12783
Summary
---
Quoting Ville Syrjala (2019-04-12 19:30:08)
> From: Ville Syrjälä
>
> Move the platform checks out from haswell_set_pipemisc() and
> rename it to bdw_set_pipemisc() to make it clear when to call it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
-Chris
_
From: Ville Syrjälä
Move the platform checks out from haswell_set_pipemisc() and
rename it to bdw_set_pipemisc() to make it clear when to call it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 68 ++--
1 file changed, 33 insertions(+), 35 delet
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously this fixes the kms_color gamma/degamma tests when
using a HDR plane, which is always the case unless one hacks
the test to use an SDR plane. If one does hack the tes
From: Bob Paauwe
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
v2: - Rename commit (Jose)
- Include a wm workaround (Jose and Lucas)
- Include display core init (Jose and Lucas)
v3: Add a missing case
== Series Details ==
Series: series starting with [1/2] drm/i915: Shortcut readiness to reset check
(rev3)
URL : https://patchwork.freedesktop.org/series/59413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12782
=
On Fri, Apr 12, 2019 at 5:56 AM Bartlomiej Zolnierkiewicz
wrote:
>
> 'default n' is the default value for any bool or tristate Kconfig
> setting so there is no need to write it explicitly.
>
> Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
> is not set' for visible symbols") th
Quoting Mika Kuoppala (2019-04-12 17:53:53)
> If cat error is set, we need to clear it by acking it. Further,
> if it is set, we must not do a normal request for reset.
>
> v2: avoid goto (Chris)
> v3: comment, error format, direct assign (Chris)
> Bspec: 12567
> Cc: Chris Wilson
> Signed-off-by:
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.
v2: avoid goto (Chris)
v3: comment, error format, direct assign (Chris)
Bspec: 12567
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 6
If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.
v2: reg (Chris)
v3: request, ack, mask from following patch (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reset.c | 23 ++-
1 file changed, 14 i
== Series Details ==
Series: series starting with [1/2] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59413/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12781
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12780
== Series Details ==
Series: drm/i915: Flush the CSB pointer reset
URL : https://patchwork.freedesktop.org/series/59389/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5922_full -> Patchwork_12777_full
Summary
---
**S
Quoting Mika Kuoppala (2019-04-12 17:16:29)
> If cat error is set, we need to clear it by acking it. Further,
> if it is set, we must not do a normal request for reset.
>
> v2: avoid goto (Chris)
>
> Bspec: 12567
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i9
Quoting Mika Kuoppala (2019-04-12 17:16:28)
> If the engine says it is ready for reset, it is ready
> so avoid further dancing and proceed.
>
> v2: reg (Chris)
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
Just starting at this to see if it's worth pulling a bit more of patch 2
(mask, ac
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.
v2: avoid goto (Chris)
Bspec: 12567
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 6 --
drivers/gpu/drm/i915/i915_reset.c | 32 +
If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.
v2: reg (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reset.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i9
== Series Details ==
Series: drm: Add detection of changing of edid on between suspend and resume
(rev3)
URL : https://patchwork.freedesktop.org/series/59352/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12778
===
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-04-12 16:37:22)
>> If cat error is set, we need to clear it by acking it. Further,
>> if it is set, we must not do a normal request for reset.
>>
>> Bspec: 12567
>> Signed-off-by: Mika Kuoppala
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 6
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b2a7ac10e21f drm/i915: Shortcut readiness to reset check
-:9: ERROR:BAD_SIGN_O
Quoting Mika Kuoppala (2019-04-12 16:47:11)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2019-04-12 16:37:23)
> >> Add a log entry to indicate if engine reported an intr
> >> condition that is a sign of halted command streamer.
> >
> > It's a user error. Isn't that we spam the "there has b
Quoting Mika Kuoppala (2019-04-12 16:37:21)
> If the engine says it is ready for reset, it is ready
> so avoid further dancing and proceed.
>
> Cc: Chris Wilson Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reset.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/
Quoting Mika Kuoppala (2019-04-12 16:37:22)
> If cat error is set, we need to clear it by acking it. Further,
> if it is set, we must not do a normal request for reset.
>
> Bspec: 12567
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 +++--
> drivers/gpu/drm/i915/i9
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-04-12 16:37:23)
>> Add a log entry to indicate if engine reported an intr
>> condition that is a sign of halted command streamer.
>
> It's a user error. Isn't that we spam the "there has been an error;
> resetting the gpu" message enough?
>
> You
Quoting Mika Kuoppala (2019-04-12 16:37:23)
> Add a log entry to indicate if engine reported an intr
> condition that is a sign of halted command streamer.
It's a user error. Isn't that we spam the "there has been an error;
resetting the gpu" message enough?
You could just look at the iir in the
If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 68875ba43b8d..c
Add a log entry to indicate if engine reported an intr
condition that is a sign of halted command streamer.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 24 +---
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 25 insertions(
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.
Bspec: 12567
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++--
drivers/gpu/drm/i915/i915_reset.c | 39 +--
2 files cha
== Series Details ==
Series: series starting with [01/50] drm/i915: Introduce struct class_instance
for engines across the uAPI (rev3)
URL : https://patchwork.freedesktop.org/series/59379/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
On Fri, 12 Apr 2019 at 09:54, Chris Wilson wrote:
>
> Use the per-object local lock to control the cache domain of the
> individual GEM objects, not struct_mutex. This is a huge leap forward
> for us in terms of object-level synchronisation; execbuffers are
> coordinated using the ww_mutex and pre
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical per-engine
On 10/04/2019 04:17, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> In order to support additional features in hex_dump_to_buffer, replace
> the ascii bool parameter with flags.
>
> Signed-off-by: Alastair D'Silva
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c| 2 +-
> dr
On 12/04/2019 14:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-12 14:31:31)
On 12/04/2019 09:53, Chris Wilson wrote:
@@ -875,22 +927,27 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
i915_active_init(i915, &cb->base, cb_retire);
i915_active_acquire(&
On Thu, 2019-04-11 at 16:51 -0700, Rodrigo Vivi wrote:
> On Thu, Apr 11, 2019 at 04:16:41PM -0700, Souza, Jose wrote:
> > On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> > > From: Bob Paauwe
> > >
> > > Most of the conditional code for ICELAKE also applies to
> > > ELKHARTLAKE
> > > so u
== Series Details ==
Series: drm/i915: Flush the CSB pointer reset
URL : https://patchwork.freedesktop.org/series/59389/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5922 -> Patchwork_12777
Summary
---
**SUCCESS**
On 4/12/2019 8:10 PM, Tvrtko Ursulin wrote:
On 12/04/2019 08:14, Chris Wilson wrote:
SSEU reprogramming of the context introduced the notion of engine class
and instance for a forwards compatible method of describing any engine
beyond the old execbuf interface. We wish to adopt this class:inst
On Wed 2019-04-10 13:17:19, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> In order to support additional features in hex_dump_to_buffer, replace
> the ascii bool parameter with flags.
>
> Signed-off-by: Alastair D'Silva
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c| 2 +-
>
Quoting Gwan-gyeong Mun (2019-04-12 15:06:17)
> After suspend/resume process, hotplug detection is handled by
> i915_hpd_poll_init_work() workqueue. While intel_hdmi_detect() or
> intel_dp_detect() are called, intel_hdmi_set_edid() or intel_dp_set_edid()
> only update an internal detect_edid variab
After suspend/resume process, hotplug detection is handled by
i915_hpd_poll_init_work() workqueue. While intel_hdmi_detect() or
intel_dp_detect() are called, intel_hdmi_set_edid() or intel_dp_set_edid()
only update an internal detect_edid variable of intel_connector.
A missed update of edid propert
The hotplug detection routine of drm_helper_hpd_irq_event() can detect
changing of status of connector, but it can not detect changing of edid.
Following scenario requires detection of changing of edid.
1) plug display device to a connector
2) system suspend
3) unplug 1)'s display device and p
This patch series fix missed detection of changing of edid on between
suspend and resume.
First patch fixes drm_helper_hdp_irq_event() in order to fix a below use
case.
Following scenario requires detection of changing of edid.
1) plug display device to a connector
2) system suspend
3)
On Wed 2019-04-10 13:17:18, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Some buffers may only be partially filled with useful data, while the rest
> is padded (typically with 0x00 or 0xff).
>
> This patch introduces flags which allow lines of padding bytes to be
> suppressed, making the
On Wed 2019-04-10 13:17:17, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> With modern high resolution screens, we can display more data, which makes
> life a bit easier when debugging.
I have quite some doubts about this feature.
We are talking about more than 256 characters per-line. I
Quoting Tvrtko Ursulin (2019-04-12 14:31:31)
>
> On 12/04/2019 09:53, Chris Wilson wrote:
> > @@ -875,22 +927,27 @@ static int context_barrier_task(struct
> > i915_gem_context *ctx,
> > i915_active_init(i915, &cb->base, cb_retire);
> > i915_active_acquire(&cb->base);
> >
> > -
On Thu, Apr 11, 2019 at 07:49:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We are no longer calling bxt_ddi_phy_calc_lane_lat_optim_mask() when
> intel{hdmi,dp}_compute_config() succeeds, and instead only call it
> when those fail. This is fallout from the bool->int
> .compute_confi
On Fri, Apr 12, 2019 at 11:29:17AM +0300, Imre Deak wrote:
> On Thu, Apr 11, 2019 at 05:33:49PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On ICL the DMC doesn't reinit combo PHY B so we should not warn
> > about its state being bogus during the display core uninit.
> >
> > Sign
On 12/04/2019 09:53, Chris Wilson wrote:
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW
To continue the onslaught of removing the assumption of a global
execution ordering, another casualty is the engine->timeline. Without an
actual timeline to track, it is overkill and we can replace it with a
much less grand plain list. We still need a list of requests inflight,
for the simple purpo
Quoting Tvrtko Ursulin (2019-04-12 13:59:30)
>
> On 12/04/2019 09:53, Chris Wilson wrote:
> > For controlling runtime pm of the GT and engines, we would like to have
> > a callback to do extra work the first time we wake up and the last time
> > we drop the wakeref. This first/last access needs se
On 12/04/2019 09:53, Chris Wilson wrote:
We wish to start segregating the power management into different control
domains, both with respect to the hardware and the user interface. The
first step is that at the lowest level flow of requests, we want to
process a context event (and not a global G
On 12/04/2019 09:53, Chris Wilson wrote:
For controlling runtime pm of the GT and engines, we would like to have
a callback to do extra work the first time we wake up and the last time
we drop the wakeref. This first/last access needs serialisation and so
we encompass a mutex with the regular in
== Series Details ==
Series: Add Multi Segment Gamma Support (rev3)
URL : https://patchwork.freedesktop.org/series/58169/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5922 -> Patchwork_12776
Summary
---
**FAILURE**
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-04-12 13:22:12)
>> Chris Wilson writes:
>>
>> > The HW resets it CSB tail pointer on resetting the engine. Most of the
>> > time. In case it doesn't (and for system resume) we write the expected
>> > value anyway. For extra paranoia, flush the
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