Quoting Tvrtko Ursulin (2019-04-18 07:47:51)
>
> On 17/04/2019 08:56, Chris Wilson wrote:
> > +static void
> > +virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
> > +{
> > + struct virtual_engine *ve = to_virtual_engine(rq->engine);
> > + struct ve_bond *bond;
> > +
On 17/04/2019 08:56, Chris Wilson wrote:
Some users require that when a master batch is executed on one particular
engine, a companion batch is run simultaneously on a specific slave
engine. For this purpose, we introduce virtual engine bonding, allowing
maps of master:slaves to be constructed t
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5951_full -> Patchwork_12825_full
==
On Wednesday, April 17, 2019 11:35 PM, Simon Ser wrote:
> In terms of graphs, if a plane is a node and a two-plane overlap is an
> edge, it means we want a complete graph (each node has an edge to all
> other nodes). If we only have square planes, it's already impossible to
> get a solution for 4
On Wed, 2019-04-17 at 15:37 -0700, José Roberto de Souza wrote:
> A new macro that is going to be added in a further patch will need to
> adjust the offset returned by _MMIO_TRANS2(), so here adding
> _TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
> it and while at it taking t
On Wed, 2019-04-17 at 15:37 -0700, José Roberto de Souza wrote:
> Just moving it to reduce the tabs and avoid break code lines.
> No behavior changes intended here.
>
> v2:
> - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
> other irq handlers (Dhinakaran)
>
> Cc: Dhinakaran P
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev8)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5949_full -> Patchwork_12824_full
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation (rev3)
URL : https://patchwork.freedesktop.org/series/59655/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5948_full -> IGTPW_2888_full
=
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation (rev2)
URL : https://patchwork.freedesktop.org/series/59655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948_full -> IGTPW_2886_full
=
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation
URL : https://patchwork.freedesktop.org/series/59655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948_full -> IGTPW_2885_full
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify whitelist of
context registers
URL : https://patchwork.freedesktop.org/series/59649/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948_full -> Patchwork_12823_full
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5951 -> Patchwork_12825
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59672/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/bdw+: Move misc d
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59672/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a6f3b42a779 drm/i915/bdw+: Move misc display IRQ han
A new macro that is going to be added in a further patch will need to
adjust the offset returned by _MMIO_TRANS2(), so here adding
_TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
it and while at it taking the opportunity to rename pipe to trans.
Cc: Rodrigo Vivi
Signed-off-by
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
v2:
- Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
other irq handlers (Dhinakaran)
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
d
Lets make PSR register macros explicit about what transcoder is used
to calculate the register offset.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++
drivers/gpu/drm/i915/i915_reg.h | 24 +++---
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
using it makes more difficult for people with an PSR register address
or PSR register name from from BSpec as i
== Series Details ==
Series: drm/i915: Avoid use-after-free in reporting create.size
URL : https://patchwork.freedesktop.org/series/59645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5947_full -> Patchwork_12821_full
Summ
On Tuesday, April 16, 2019 10:04 PM, Ville Syrjälä
wrote:
> On Tue, Apr 16, 2019 at 08:13:12PM +0200, Maarten Lankhorst wrote:
>
> > Op 16-04-2019 om 15:42 schreef Ville Syrjälä:
> >
> > > On Tue, Apr 16, 2019 at 03:28:15PM +0200, Maarten Lankhorst wrote:
> > >
> > > > Op 16-04-2019 om 15:20 schr
== Series Details ==
Series: series starting with [1/2] drm/i915: remove DRM_AUTH from IOCTLs which
also have DRM_RENDER_ALLOW
URL : https://patchwork.freedesktop.org/series/59641/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5946_full -> Patchwork_12820_full
===
Quoting Mika Kuoppala (2019-04-17 16:28:34)
> Libify resetting a spin for reuse.
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.
Quoting Mika Kuoppala (2019-04-17 16:28:33)
> There is no guarantee that spinners are and will be implemented
> using batches. As we have igt_spin_t, manipulate it through
> igt_spin_* functions consistently and hide the batch nature.
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
Reviewed-
Quoting Mika Kuoppala (2019-04-17 17:43:39)
> Instead of opencoding the poll into the spinner, use
> a helper to check if spinner has started.
>
> v2: use zero as presumed offset (Chris)
> v3: cleanup the relocs (Chris)
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> static int
>
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev8)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5949 -> Patchwork_12824
Summary
On Mon, 2019-04-15 at 18:32 +0200, Daniel Vetter wrote:
> On Thu, Apr 11, 2019 at 05:36:30PM +0300, Gwan-gyeong Mun wrote:
> > This patch series fix missed detection of changing of edid on
> > between
> > suspend and resume.
> > First patch fixes drm_helper_hdp_irq_event() in order to fix a
> > bel
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
V5: Split
Den 16.04.2019 10.41, skrev Daniel Vetter:
> On Sun, Apr 07, 2019 at 06:52:31PM +0200, Noralf Trønnes wrote:
>> This moves the modesetting code from drm_fb_helper to drm_client so it
>> can be shared by all internal clients.
>>
>> The main change this time is to attach the modeset array to
>> drm
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation (rev3)
URL : https://patchwork.freedesktop.org/series/59655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948 -> IGTPW_2888
===
Den 16.04.2019 10.38, skrev Daniel Vetter:
> On Sun, Apr 07, 2019 at 06:52:39PM +0200, Noralf Trønnes wrote:
>> Move the modeset commit code to drm_client_modeset.
>> No changes except exporting API.
>>
>> v2: Move to drm_client_modeset.c instead of drm_client.c
>>
>> Signed-off-by: Noralf Trønne
On 4/16/19 10:39 PM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
v2: use reg/mask/value instead of dedicated functions (Daniele)
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo
On 4/16/19 10:39 PM, Michal Wajdeczko wrote:
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
v2: add note about Gen9 definition mismatch (Daniele)
rename __intel_engine_context_size (Daniele)
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Cera
On 4/16/19 10:39 PM, Michal Wajdeczko wrote:
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
v2: drop deprecated prod_preprod_fw field, replace unions with bit defs
On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 15:16:41)
> > From: Ville Syrjälä
> >
> > Since SKL the eLLC has been sitting on the far side of the system
> > agent, meaning the display engine can utilize it. Let's enable that.
> >
> > I chose W
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation (rev2)
URL : https://patchwork.freedesktop.org/series/59655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948 -> IGTPW_2886
===
Hi,
On Tue, Apr 16, 2019 at 04:57:58PM +0200, Noralf Trønnes wrote:
> Den 16.04.2019 11.42, skrev Maxime Ripard:
> > Hi,
> >
> > On Sun, Apr 07, 2019 at 06:52:40PM +0200, Noralf Trønnes wrote:
> >> All drivers add all their connectors so there's no need to keep around an
> >> array of available co
Instead of opencoding the poll into the spinner, use
a helper to check if spinner has started.
v2: use zero as presumed offset (Chris)
v3: cleanup the relocs (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
lib/igt_dummyload.c| 66 +-
lib/ig
== Series Details ==
Series: series starting with [1/3] lib/igt_dummyload: libify checks for spin
batch activation
URL : https://patchwork.freedesktop.org/series/59655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948 -> IGTPW_2885
==
Quoting Mika Kuoppala (2019-04-17 16:54:56)
> Instead of opencoding the poll into the spinner, use
> a helper to check if spinner has started.
>
> v2: use zero as presumed offset (Chris)
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> lib/igt_dummyload.c| 35 +++
Instead of opencoding the poll into the spinner, use
a helper to check if spinner has started.
v2: use zero as presumed offset (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
lib/igt_dummyload.c| 35 +++---
lib/igt_dummyload.h| 17 +
Quoting Mika Kuoppala (2019-04-17 16:28:32)
> Instead of opencoding the poll into the spinner, use
> a helper to check if spinner has started.
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> lib/igt_dummyload.c| 35 +++---
> lib/igt_dummyload.
Libify resetting a spin for reuse.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
lib/igt_dummyload.c | 20
lib/igt_dummyload.h | 2 ++
tests/i915/gem_exec_latency.c | 19 ---
tests/i915/gem_sync.c | 34 ++-
There is no guarantee that spinners are and will be implemented
using batches. As we have igt_spin_t, manipulate it through
igt_spin_* functions consistently and hide the batch nature.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
lib/drmtest.c | 4 +-
lib/igt_core.c
Instead of opencoding the poll into the spinner, use
a helper to check if spinner has started.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
lib/igt_dummyload.c| 35 +++---
lib/igt_dummyload.h| 17 ++---
tests/i915/gem_ctx_exec
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify whitelist of
context registers
URL : https://patchwork.freedesktop.org/series/59649/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5948 -> Patchwork_12823
==
Den 17.04.2019 15.26, skrev Daniel Vetter:
> On Wed, Apr 17, 2019 at 03:24:00PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 16, 2019 at 08:46:24PM +0200, Noralf Trønnes wrote:
>>>
>>>
>>> Den 16.04.2019 09.59, skrev Daniel Vetter:
On Sun, Apr 07, 2019 at 06:52:33PM +0200, Noralf Trønnes wrote
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev5)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5947 -> Patchwork_12822
Summary
---
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev5)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce vfunc intel_get_color_config to create hw l
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev5)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3100439817a3 drm/i915: Introduce vfunc intel_get_color_config to create hw lut
153c16eea81
== Series Details ==
Series: drm/i915: Avoid use-after-free in reporting create.size
URL : https://patchwork.freedesktop.org/series/59645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5947 -> Patchwork_12821
Summary
--
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
From: Tvrtko Ursulin
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Whitelist the register to allow media re-configuring it to their liking.
Signed-off-by: Tvrtko Ursulin
Cc: kevin...@intel.com
Cc: xiaogan
v3: Rebase
v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() (Jani)
-Added the default label above the correct label (Jani)
-Corrected smatch warn "variable dereferenced before check" (Dan Carpenter)
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 5
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 2e3b35c..28cb490 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 48 +-
2 files changed, 50 insertions(+
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 41 --
2 files changed, 42 insertions(+
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 28cb490..0d0d57c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 38 ++
2 files changed, 41 insertions(+
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 49 --
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
Thanks to Jani N, Matt and Ville for the review comments. Hopefully
I have addressed all the current review comments and ready to receive more :)
In this patch series, added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the st
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 38 ++
2 files changed, 41 insertions(+
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 50 ++
2 files changed, 53 insertions(+
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Added the user early on such that support for get_color_config()
can be added platform by platform incrementally [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 i
v3: Rebase
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Wrapped get_color_config() [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 8
drivers/gpu/drm/i915/intel_color.h | 1 +
3 files chan
Quoting Tvrtko Ursulin (2019-04-17 12:26:04)
>
> On 17/04/2019 08:56, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> > b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> > index e19f84b006cc..f900f0680647 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.
On 17/04/2019 14:25, Chris Wilson wrote:
We have to avoid chasing after a userspace race!
<3>[ 473.114328] BUG: KASAN: use-after-free in i915_gem_create+0x1d2/0x1f0
[i915]
<3>[ 473.114389] Read of size 8 at addr 88815bf1d840 by task
gem_flink_race/1541
<4>[ 473.114464] CPU: 1 PID: 154
On Thu, 04 Apr 2019, Vandita Kulkarni wrote:
> In case of dual link mode, the mode clock that we get
> from the VBT is halved.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/d
== Series Details ==
Series: drm/i915: Avoid use-after-free in reporting create.size
URL : https://patchwork.freedesktop.org/series/59645/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0d3fa8a91d19 drm/i915: Avoid use-after-free in reporting create.size
-:11: WARNING:COMMIT_LOG
On 17/04/2019 13:46, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-17 13:35:29)
On 17/04/2019 12:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-17 12:43:49)
On 17/04/2019 08:56, Chris Wilson wrote:
Allow the user to direct which physical engines of the virtual engine
they wi
On Wed, Apr 17, 2019 at 03:24:00PM +0200, Daniel Vetter wrote:
> On Tue, Apr 16, 2019 at 08:46:24PM +0200, Noralf Trønnes wrote:
> >
> >
> > Den 16.04.2019 09.59, skrev Daniel Vetter:
> > > On Sun, Apr 07, 2019 at 06:52:33PM +0200, Noralf Trønnes wrote:
> > >> drm_fb_helper_is_bound() is used to
We have to avoid chasing after a userspace race!
<3>[ 473.114328] BUG: KASAN: use-after-free in i915_gem_create+0x1d2/0x1f0
[i915]
<3>[ 473.114389] Read of size 8 at addr 88815bf1d840 by task
gem_flink_race/1541
<4>[ 473.114464] CPU: 1 PID: 1541 Comm: gem_flink_race Tainted: G U
On Tue, Apr 16, 2019 at 08:46:24PM +0200, Noralf Trønnes wrote:
>
>
> Den 16.04.2019 09.59, skrev Daniel Vetter:
> > On Sun, Apr 07, 2019 at 06:52:33PM +0200, Noralf Trønnes wrote:
> >> drm_fb_helper_is_bound() is used to check if DRM userspace is in control.
> >> This is done by looking at the f
== Series Details ==
Series: GuC 32.0.3 (rev4)
URL : https://patchwork.freedesktop.org/series/58760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5942_full -> Patchwork_12818_full
Summary
---
**SUCCESS**
No regre
On Thu, Apr 11, 2019 at 04:36:00PM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A ext
On Wed, Apr 17, 2019 at 01:25:24PM +0200, Christian König wrote:
> This is to work around problems with libva and vainfo.
>
> Signed-off-by: Christian König
I don't think this is a good idea since it leaves the core ioctl out, and
it leaves all other drivers out (and inconsistency in these winsy
Quoting Tvrtko Ursulin (2019-04-17 13:35:29)
>
> On 17/04/2019 12:57, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-04-17 12:43:49)
> >>
> >> On 17/04/2019 08:56, Chris Wilson wrote:
> >>> Allow the user to direct which physical engines of the virtual engine
> >>> they wish to execute one,
On 17/04/2019 12:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-17 12:43:49)
On 17/04/2019 08:56, Chris Wilson wrote:
Allow the user to direct which physical engines of the virtual engine
they wish to execute one, as sometimes it is necessary to override the
load balancing algorithm.
== Series Details ==
Series: series starting with [1/2] drm/i915: remove DRM_AUTH from IOCTLs which
also have DRM_RENDER_ALLOW
URL : https://patchwork.freedesktop.org/series/59641/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5946 -> Patchwork_12820
=
Quoting Tvrtko Ursulin (2019-04-17 12:43:49)
>
> On 17/04/2019 08:56, Chris Wilson wrote:
> > Allow the user to direct which physical engines of the virtual engine
> > they wish to execute one, as sometimes it is necessary to override the
> > load balancing algorithm.
> >
> > Signed-off-by: Chris
On Wed, Apr 17, 2019 at 09:28:19AM +0200, Daniel Vetter wrote:
> On Fri, Apr 12, 2019 at 03:50:56PM +0530, Uma Shankar wrote:
> > This series adds support for programmable gamma modes and
> > exposes a property interface for the same. Also added,
> > support for multi segment gamma mode introduced
On 17/04/2019 08:56, Chris Wilson wrote:
Allow the user to direct which physical engines of the virtual engine
they wish to execute one, as sometimes it is necessary to override the
load balancing algorithm.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 58 +++
Quoting Christian König (2019-04-17 12:25:24)
> This is to work around problems with libva and vainfo.
>
> Signed-off-by: Christian König
Mediated HW access should not require additional DRM_AUTH, if you can
already create buffers, execbuf itself should not be any more dangerous.
Reviewed-by: C
== Series Details ==
Series: series starting with [1/2] drm/i915: remove DRM_AUTH from IOCTLs which
also have DRM_RENDER_ALLOW
URL : https://patchwork.freedesktop.org/series/59641/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9091009a4b9e drm/i915: remove DRM_AUTH from IOCTLs
== Series Details ==
Series: series starting with [01/32] drm/i915: Seal races between async GPU
cancellation, retirement and signaling
URL : https://patchwork.freedesktop.org/series/59636/
State : failure
== Summary ==
Applying: drm/i915: Seal races between async GPU cancellation, retirement
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-04-16 16:01:58)
>> Add subtests to resend the same spinner to same context
>> and to other context.
>>
>> v2: other engines (Chris)
>>
>> Cc: Chris Wilson
>> Signed-off-by: Mika Kuoppala
> Reviewed-by: Chris Wilson
>
>> + igt_s
On 17/04/2019 08:56, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the
This reverts commit 8059add0478e29cb641936011a8fcc9ce9fd80be.
It's breaking radv and most likely old libdrm_amdgpu versions.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_ioctl.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/d
This is to work around problems with libva and vainfo.
Signed-off-by: Christian König
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bbe1a5d56480..12615641a
On Thu, 04 Apr 2019, Vandita Kulkarni wrote:
> Read back the pixel fomrat register and get the bpp.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/d
Quoting Matthew Auld (2019-04-17 12:11:21)
> On Fri, 12 Apr 2019 at 09:54, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h
> > b/drivers/gpu/drm/i915/i915_scatterlist.h
> > new file mode 100644
> > index ..ca9ddee41e88
> > --- /dev/null
> > +++ b/drivers/g
On Fri, 05 Apr 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Ville Syrjälä
>> Sent: Friday, April 5, 2019 2:00 AM
>> To: Kulkarni, Vandita
>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
>> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix pipe config timing
>>
On Fri, 12 Apr 2019 at 09:54, Chris Wilson wrote:
>
> Out scatterlist utility routines can be pulled out of i915_gem.h for a
> bit more decluttering.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c|
On Fri, 05 Apr 2019, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work correctly using xrandr
On 17/04/2019 08:56, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance)
On 17/04/2019 08:56, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy
On 17/04/2019 08:56, Chris Wilson wrote:
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c |
On 17/04/2019 08:56, Chris Wilson wrote:
For controlling runtime pm of the GT and engines, we would like to have
a callback to do extra work the first time we wake up and the last time
we drop the wakeref. This first/last access needs serialisation and so
we encompass a mutex with the regular in
On 17/04/2019 08:56, Chris Wilson wrote:
Start partitioning off the code that talks to the hardware (GT) from the
uapi layers and move the device facing code under gt/
One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to
subdivide that header and body further (and split out the
On 17/04/2019 08:56, Chris Wilson wrote:
As we push for better compartmentalisation, it is more convenient to
copy the default sseu configuration from the engine into the derived
logical context, than it is to dig it out from i915->runtime_info.
Signed-off-by: Chris Wilson
---
drivers/gpu/dr
On 17/04/2019 08:56, Chris Wilson wrote:
Sometimes the HW doesn't even play fair, and completely forgets about
register writes. Skip verifying known troublemakers.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/
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