== Series Details ==
Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data
type to u32
URL : https://patchwork.freedesktop.org/series/60007/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6007_full -> Patchwork_12886_full
== Series Details ==
Series: drm/i915: add in-kernel blitter client
URL : https://patchwork.freedesktop.org/series/60017/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12889
Summary
---
**FAILURE**
Quoting Matthew Auld (2019-04-26 23:17:05)
> The plan is to use the blitter engine for async object clearing when
> using local memory, but before we can move the worker to get_pages() we
> have to first tame some more of our struct_mutex usage. With this in
> mind we should be able to upstream
== Series Details ==
Series: drm/i915: add in-kernel blitter client
URL : https://patchwork.freedesktop.org/series/60017/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: add in-kernel blitter client
== Series Details ==
Series: drm/i915: add in-kernel blitter client
URL : https://patchwork.freedesktop.org/series/60017/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
658ea31e573a drm/i915: add in-kernel blitter client
-:43: CHECK:SPACING: spaces preferred around that '<<'
The plan is to use the blitter engine for async object clearing when
using local memory, but before we can move the worker to get_pages() we
have to first tame some more of our struct_mutex usage. With this in
mind we should be able to upstream the object clearing as some
selftests, which should
== Series Details ==
Series: Refactor to expand subslice mask (rev3)
URL : https://patchwork.freedesktop.org/series/59742/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
slice * subslice stride +
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
drivers/gpu/drm/i915/i915_query.c| 17
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on
parking
URL : https://patchwork.freedesktop.org/series/60008/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12887
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on
parking
URL : https://patchwork.freedesktop.org/series/60008/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/execlists: Flush the tasklet on
On Fri, Apr 26, 2019 at 11:53:54AM -0700, Aditya Swarup wrote:
> On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote:
> > On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> > > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 25, 2019 at
== Series Details ==
Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data
type to u32
URL : https://patchwork.freedesktop.org/series/60007/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12886
On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > > > From: Clinton Taylor
> >
On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > > From: Clinton Taylor
> > >
> > > v2: Fix commit msg to reflect why issue occurs(Jani)
> > > Set
On Fri, Apr 26, 2019 at 01:12:58PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote:
> > On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote:
> > > On Fri, 05 Apr 2019, Aditya Swarup wrote:
> > > > From: Clinton Taylor
> > > >
> > > > v2: Fix
On Fri, Apr 26, 2019 at 11:31:51PM +0530, Shashank Sharma wrote:
> ICL introduces a new gamma correction mode in display engine, called
> multi-segmented-gamma mode. This mode allows users to program the
> darker region of the gamma curve with sueprfine precision. An
> example use case for this is
On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > From: Clinton Taylor
> >
> > v2: Fix commit msg to reflect why issue occurs(Jani)
> > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
> >
> >
Remove the modification of the "constant" device info by promoting the
inconsistent intel_engine static table into an initialisation error.
Now, if we add a new engine into the device_info, we must first add that
engine information into the intel_engines.
Signed-off-by: Chris Wilson
---
Make the engine responsible for cleaning itself up!
This removes the i915->gt.cleanup vfunc that has been annoying the
casual reader and myself for the last several years, and helps keep a
future patch to add more cleanup tidy.
v2: Assert that engine->destroy is set after the backend starts
Tidy up the cleanup sequence by always ensure that the tasklet is
flushed on parking (before we cleanup). The parking provides a
convenient point to ensure that the backend is truly idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++--
On Fri, Apr 26, 2019 at 11:31:50PM +0530, Shashank Sharma wrote:
> From: Uma Shankar
>
> Add macros to define multi segmented gamma registers
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 17 +
> 1 file
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT
shadow contexts
URL : https://patchwork.freedesktop.org/series/60004/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6006 -> Patchwork_12885
On Thu, Apr 18, 2019 at 3:06 AM Tvrtko Ursulin
wrote:
>
> From: Tvrtko Ursulin
>
> WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> to benefit 3d workloads but media has different requirements.
>
> Remove the workaround and whitelist the register to allow any userspace
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT
shadow contexts
URL : https://patchwork.freedesktop.org/series/60004/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gvt: Pin the per-engine GVT
Joonas,
Mesa now applies this WA on ICL and we're not seeing any regressions in CI.
I tested Mesa with and without this patch applied to kernel. I don't see any
performance impact to Manhattan from GfxBench5. I'm little surprised to
see it's not really helping benchmark performance in Mesa.
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT
shadow contexts
URL : https://patchwork.freedesktop.org/series/60004/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
df18fb0cb42a drm/i915/gvt: Pin the per-engine GVT shadow
Combine the (i915_gem_context, intel_engine) into a single parameter,
the intel_context for convenience and later simplification.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 74 +++
1 file changed, 44
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical
Move the intel_context_instance() to the caller so that we can decouple
ourselves from one context instance per engine.
v2: Rename pin_lock() to lock_pinned(), hopefully that is clearer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c
Simply the setup slightly for the sseu selftests to use the actual
kernel_context.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git
Having transitioned GEM over to using intel_context as its primary means
of tracking the GEM context and engine combined and using
i915_request_create(), we can move the older i915_request_alloc()
helper function into selftests/ where the remaining users are confined.
Signed-off-by: Chris Wilson
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 11 +--
In the next patch, we require the engine vfuncs setup prior to
initialising the pinned kernel contexts, so split the vfunc setup from
the engine initialisation and call it earlier.
v2: s/setup_xcs/setup_common/ for intel_ring_submission_setup()
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko
We want to pass in a intel_context into intel_context_pin() and that
requires us to first be able to lookup the intel_context!
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c| 37 +++---
Our eventual goal is to rid request construction of struct_mutex, with
the short term step of lifting the struct_mutex requirements into the
higher levels (i.e. the caller must ensure that the context is already
pinned into the GTT). In this patch, we pin GVT's shadow context upon
allocation and
From: Ville Syrjälä
Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
the running with > 8bpc.
v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc
Cc: Mario Kleiner
Signed-off-by: Ville Syrjälä
---
src/sna/sna_display.c | 245
From: Ville Syrjälä
Generalize the code that parses the plane properties to be useable
for crtc (or any kms object) properties as well.
v2: plane 'type' prop is enum not range!
Cc: Mario Kleiner
Signed-off-by: Ville Syrjälä
---
src/sna/sna_display.c | 69
On Fri, Apr 26, 2019 at 04:01:02PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-04-26 15:54:54)
> > On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote:
> > > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote:
> > > > Quoting Ville Syrjala (2019-04-15 15:16:41)
> >
On Fri, Apr 26, 2019 at 12:56:48PM +1000, Dave Airlie wrote:
> Daniel, drm-misc-next-fixes?
Makes sense. Pushed.
Cheers, Daniel
>
> Dave.
>
> On Fri, 26 Apr 2019 at 12:25, wrote:
> >
> > Hi Dave,
> >
> > > -Original Message-
> > > From: Dave Airlie [mailto:airl...@gmail.com]
> > >
Quoting Ville Syrjälä (2019-04-26 15:54:54)
> On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2019-04-15 15:16:41)
> > > > From: Ville Syrjälä
> > > >
> > > > Since SKL the eLLC has been
On Fri, Apr 26, 2019 at 08:56:45AM +0100, Chris Wilson wrote:
> If we can't match the devid to a chipset, we do not have a reference for
> the tiling strides. Instead of randomly failing, skip with a
> semi-informative message.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523
>
On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-04-15 15:16:41)
> > > From: Ville Syrjälä
> > >
> > > Since SKL the eLLC has been sitting on the far side of the system
> > > agent,
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12884_full
On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
>
> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The pipe has a special HDR mode with higher precision when only
> > HDR planes are active. Let's use it.
> >
> > Curiously this fixes the kms_color
Reviewed-by: Swati Sharma
Thanks and Regards,
Swati
-Original Message-
From: Intel-gfx On Behalf Of Ville
Syrjala
Sent: Monday, April 8, 2019 5:48 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Clean up cherryview_load_luts()
From: Ville Syrjälä
I
Reviewed-by: Swati Sharma
Thanks and Regards,
Swati
-Original Message-
From: Intel-gfx On Behalf Of Ville
Syrjala
Sent: Friday, April 26, 2019 12:54 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming
From: Ville Syrjälä
When
== Series Details ==
Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow
contexts
URL : https://patchwork.freedesktop.org/series/59970/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12883_full
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously this fixes the kms_color gamma/degamma tests when
using a HDR plane, which is always the case unless one hacks
the
== Series Details ==
Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
(rev7)
URL : https://patchwork.freedesktop.org/series/58912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6001_full -> Patchwork_12881_full
On Thu, 25 Apr 2019, Chris Wilson wrote:
> For convenience in avoiding inline spaghetti, keep the type definition
> as a separate header.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
>
On 25/04/2019 11:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-25 11:35:01)
On 25/04/2019 10:19, Chris Wilson wrote:
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In
Quoting Ville Syrjälä (2019-04-23 16:36:47)
> On Fri, Apr 19, 2019 at 12:17:47PM +0100, Chris Wilson wrote:
> > Despite what I think the prm recommends, commit f2253bd9859b
> > ("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
> > to be a huge mistake when enabling Ironlake
On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work
On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote:
> On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote:
> > On Fri, 05 Apr 2019, Aditya Swarup wrote:
> > > From: Clinton Taylor
> > >
> > > v2: Fix commit msg to reflect why issue occurs(Jani)
> > > Set GCP_COLOR_INDICATION
== Series Details ==
Series: series starting with [1/7] drm/i915: Introduce intel_irq
URL : https://patchwork.freedesktop.org/series/59958/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12880_full
== Series Details ==
Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks
URL : https://patchwork.freedesktop.org/series/59956/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12879_full
== Series Details ==
Series: drm/i915: Fix ICL output CSC programming
URL : https://patchwork.freedesktop.org/series/59955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12878_full
Summary
---
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12884
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59980/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59980/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ab284a305f9c drm/i915: Disable preemption
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Factor out combo PHY lane
power setup helper
URL : https://patchwork.freedesktop.org/series/59954/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12877_full
+ Anuj
Quoting Lionel Landwerlin (2019-04-26 11:13:58)
> On 18/04/2019 18:06, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> > to benefit 3d workloads but media has different requirements.
> >
> > Remove the
FYI,
MDAPI got tired of waiting for this to land upstream :
https://github.com/intel/metrics-discovery/commit/7b6399d5d5e5ef5fcc018a48853b46d0803da441
Apart from squashing the last commit, any other change needed?
Thanks,
-Lionel
On 03/04/2019 00:36, Lionel Landwerlin wrote:
On 02/04/2019
Split the sideback declarations out of the ginormous i915_drv.h
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile.header-test | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 120
sandybride_pcode is another sideband, so move it to their new home.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 195 -
Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.
v2: Restore vlv_flisdsi_read() lost during rebasing.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pcu_lock is now redudant
and can be separated
These routines are identical except in the nature of the value parameter.
For writes it is a pure in-param, but for a read, we need an out-param.
Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
---
Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
into their callers, so that we can lock the sideband once for a sequence
of operations, rather than perform the heavyweight acquisition on each
request.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idle) doesn't provide a sufficient barrier to ensure that all core
are indeed awake (out of
On 18/04/2019 18:06, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Remove the workaround and whitelist the register to allow any userspace
configure the
If we can't match the devid to a chipset, we do not have a reference for
the tiling strides. Instead of randomly failing, skip with a
semi-informative message.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523
Signed-off-by: Chris Wilson
---
tests/i915/gem_tiling_max_stride.c | 16
On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> When I refactored the code into its own function I accidentally
> misplaced the <<16 shifts for some of the registers causing us
> to lose the blue channel entirely.
>
> We should really find a way to test this...
== Series Details ==
Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow
contexts
URL : https://patchwork.freedesktop.org/series/59970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12883
== Series Details ==
Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow
contexts
URL : https://patchwork.freedesktop.org/series/59970/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gvt: Pin the per-engine GVT
== Series Details ==
Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow
contexts
URL : https://patchwork.freedesktop.org/series/59970/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
800faa589858 drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix fastset vs. pfit on/off on HSW
EDP transcoder
URL : https://patchwork.freedesktop.org/series/59950/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12876_full
Our eventual goal is to rid request construction of struct_mutex, with
the short term step of lifting the struct_mutex requirements into the
higher levels (i.e. the caller must ensure that the context is already
pinned into the GTT). In this patch, we pin GVT's shadow context upon
allocation and
Having transitioned GEM over to using intel_context as its primary means
of tracking the GEM context and engine combined and using
i915_request_create(), we can move the older i915_request_alloc()
helper function into selftests/ where the remaining users are confined.
Signed-off-by: Chris Wilson
Move the intel_context_instance() to the caller so that we can decouple
ourselves from one context instance per engine.
v2: Rename pin_lock() to lock_pinned(), hopefully that is clearer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c
Simply the setup slightly for the sseu selftests to use the actual
kernel_context.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical
Combine the (i915_gem_context, intel_engine) into a single parameter,
the intel_context for convenience and later simplification.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 74 +++
1 file changed, 44
We want to pass in a intel_context into intel_context_pin() and that
requires us to first be able to lookup the intel_context!
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c| 37 +++---
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 11 +--
In the next patch, we require the engine vfuncs setup prior to
initialising the pinned kernel contexts, so split the vfunc setup from
the engine initialisation and call it earlier.
v2: s/setup_xcs/setup_common/ for intel_ring_submission_setup()
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko
Quoting Zhenyu Wang (2019-04-26 07:04:45)
> On 2019.04.25 17:23:44 +0100, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-04-25 06:42:02)
> > > Our eventual goal is to rid request construction of struct_mutex, with
> > > the short term step of lifting the struct_mutex requirements into the
> >
== Series Details ==
Series: series starting with [01/10] drm/i915: Seal races between async GPU
cancellation, retirement and signaling (rev2)
URL : https://patchwork.freedesktop.org/series/59912/
State : failure
== Summary ==
Applying: drm/i915: Seal races between async GPU cancellation,
On 2019.04.25 17:23:44 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2019-04-25 06:42:02)
> > Our eventual goal is to rid request construction of struct_mutex, with
> > the short term step of lifting the struct_mutex requirements into the
> > higher levels (i.e. the caller must ensure that
98 matches
Mail list logo
