On 25/06/2019 22:48, Daniele Ceraolo Spurio wrote:
On 6/25/19 8:26 AM, Matt Roper wrote:
On Fri, Jun 14, 2019 at 03:17:39PM -0700, Matt Roper wrote:
On Fri, Jun 14, 2019 at 02:37:49PM -0700, José Roberto de Souza wrote:
EHL can have up to one VECS(video enhancement) engine, so add it to
the
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/icl: Add new supported CD clocks
URL : https://patchwork.freedesktop.org/series/62748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13433
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351_full -> Patchwork_13424_full
Summary
---
== Series Details ==
Series: EHL port programming (rev3)
URL : https://patchwork.freedesktop.org/series/62492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13432
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/connector: Allow max possible encoders to attach to a connector
URL : https://patchwork.freedesktop.org/series/62743/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13431
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/icl: Add new supported CD clocks
URL : https://patchwork.freedesktop.org/series/62748/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Add new supported CD clocks
Okay!
== Series Details ==
Series: EHL port programming (rev3)
URL : https://patchwork.freedesktop.org/series/62492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1ef07c06355c drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Drop stale commentary for
timeline density
URL : https://patchwork.freedesktop.org/series/62742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13430
== Series Details ==
Series: drm/i915: Eliminate platform specific drm_driver vfuncs (rev3)
URL : https://patchwork.freedesktop.org/series/62397/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6350_full -> Patchwork_13422_full
== Series Details ==
Series: drm/i915/gt: Always call kref_init for the timeline
URL : https://patchwork.freedesktop.org/series/62741/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13429
Summary
---
== Series Details ==
Series: drm/i915: Fail harder if GPU reset fails outright
URL : https://patchwork.freedesktop.org/series/62740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13428
Summary
---
== Series Details ==
Series: drm/i915/guc: Compact init params debug to a single line (rev2)
URL : https://patchwork.freedesktop.org/series/62725/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13427
On 06/19, Daniel Vetter wrote:
> On Wed, Jun 19, 2019 at 09:48:56AM +0200, Daniel Vetter wrote:
> > On Tue, Jun 18, 2019 at 11:07:50PM -0300, Rodrigo Siqueira wrote:
> > > For historical reason, the function drm_wait_vblank_ioctl always return
> > > -EINVAL if something gets wrong. This scenario
== Series Details ==
Series: drm/i915/gt: Add some debug tracing for context pinning
URL : https://patchwork.freedesktop.org/series/62731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13426
Summary
== Series Details ==
Series: drm/i915: CTS fixes (rev5)
URL : https://patchwork.freedesktop.org/series/62437/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13425
Summary
---
**FAILURE**
Serious
s/Initial support for Tiger Lake/Warning: tigers inside
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> Basic pumbling to add Tiger Lake platform to i915, support for the
> 4th
> pipe, additional combo phy, power well definitions, clock changes,
> DDI
> changes and registers moving
Now 180, 172.8 and 192 MHz are supported.
180 and 172.8 MHz CD clocks will only be used when audio is not
enabled as state by BSpec and implemented in
intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
but we are
EHL has it own voltage level requirement depending on cd clock.
BSpec: 21809
Cc: Clint Taylor
Cc: Matt Roper
Cc: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++
1 file changed, 23
EHL do not support 648 and 652.8 MHz.
v2:
- Limiting maximum CD clock by max_cdclk_freq instead of remove it
from icl_calc_cdclk()(Ville and Jani)
BSpec: 20598
Cc: Clint Taylor
Cc: Matt Roper
Cc: Ville Syrjälä
Cc: Jani Nikula
Reviewed-by: Matt Roper
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13424
Summary
---
**SUCCESS**
No
On Wed, Jun 19, 2019 at 09:24:56PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 19, 2019 at 06:49:11PM +0100, Emil Velikov wrote:
> > On Wed, 19 Jun 2019 at 17:33, Ville Syrjälä
> > wrote:
> > >
> > > On Wed, Jun 19, 2019 at 05:03:53PM +0100, Emil Velikov wrote:
> > > > Hi all,
> > > >
> > > >
== Series Details ==
Series: drm/i915: CTS fixes (rev5)
URL : https://patchwork.freedesktop.org/series/62437/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
920a6126f035 drm/i915: fix whitelist selftests with readonly registers
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible
EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.
Although EHL added a third combo PHY, no PHY_MISC register was added for
PHY C. The bspec indicates that there's no need to program the "DE to
IO Comp Pwr Down" setting for this PHY that we usually need to set in
PHY_MISC.
v2:
- Add IS_ELKHARTLAKE() guards since future platforms that have a PHY
The port parameter hasn't been used since the last bspec phy programming
update. Drop it to make some upcoming changes simpler.
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes
per BSPEC")
Cc: Clint Taylor
Signed-off-by: Matt Roper
Reviewed-by: Clint Taylor
---
Previous series revision here:
https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html
This revision incorporates Jose's feedback on patches #2, #3, and #4.
Matt Roper (5):
drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
drm/i915/ehl: Add third combo PHY
v2: Rename register to _EHL_COMBOPHY_C. (Jose)
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
11acbbf944b4 drm/i915: Add modular FIA
68a37855e4a8 drm/i915: rework reading pipe disable fuses
8deb258dbdfa
== Series Details ==
Series: drm/i915/guc: Compact init params debug to a single line
URL : https://patchwork.freedesktop.org/series/62725/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6350 -> Patchwork_13423
Summary
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized - 32. The current limitation looks artificial.
Increasing the limit to 32 does however increases the size of the static
u32 array keeping
Always initialise the refcount, even for the embedded timelines inside
mock devices.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
We no longer allocate a contiguous set of timeline ids for all engines
upon creation, so we no longer should assume that the timelines are
densely allocated within a context. Hopefully, the set of fences used
within a workload are still dense enough for us to take advantage of
the compressed radix
On 6/25/19 6:01 AM, Chris Wilson wrote:
We no longer allocate a continguous set of timeline ids for all engines
upon creation, so we no longer should assume that the timelines are
density allocated within a context. Hopefully, still dense enough for us
to take advantage of the compressed radix
Always initialise the refcount, even for the embedded timelines inside
mock devices.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Quoting Chris Wilson (2019-06-26 00:08:06)
> Use hex_dump_to_buffer() to compress the parameter debug into a single
> line for less verbose debug logs.
Please excuse the noise, git send-email typo.
-Chris
___
Intel-gfx mailing list
Use hex_dump_to_buffer() to compress the parameter debug into a single
line for less verbose debug logs.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
If we request a reset and the GPU fails to respond, abandon all hope. If
the request is still stuck when we attempt to do another, fail early and
avoid requesting multiple possibly conflicting domains be reset
simultaneously.
We should never see this in practice, and if we do, it is already too
Hi Alastair,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.2-rc6 next-20190625]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
== Series Details ==
Series: drm/i915: Eliminate platform specific drm_driver vfuncs (rev3)
URL : https://patchwork.freedesktop.org/series/62397/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6350 -> Patchwork_13422
== Series Details ==
Series: drm/i915: Eliminate platform specific drm_driver vfuncs (rev3)
URL : https://patchwork.freedesktop.org/series/62397/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix various tracepoints for gen2
Okay!
Commit:
== Series Details ==
Series: drm/i915: Eliminate platform specific drm_driver vfuncs (rev3)
URL : https://patchwork.freedesktop.org/series/62397/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
676d3dde843d drm/i915: Fix various tracepoints for gen2
-:76: WARNING:TABSTOP:
== Series Details ==
Series: drm/i915/guc: Add debug capture of GuC exception (rev2)
URL : https://patchwork.freedesktop.org/series/62554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6346_full -> Patchwork_13421_full
On Fri, Jun 21, 2019 at 01:52:16PM -0700, Souza, Jose wrote:
> On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> > EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
> >
> > Cc: José Roberto de Souza
> > Signed-off-by: Matt Roper
> > ---
> >
On Mon, Jun 24, 2019 at 1:36 PM Sam Ravnborg wrote:
>
> Hi Derek.
>
> On Fri, Jun 21, 2019 at 08:41:02PM -0700, Derek Basehore wrote:
> > This adds a helper function for reading the rotation (panel
> > orientation) from the device tree.
> >
> > Signed-off-by: Derek Basehore
> > ---
> >
== Series Details ==
Series: series starting with [01/20] drm/i915/execlists: Convert recursive
defer_request() into iterative (rev3)
URL : https://patchwork.freedesktop.org/series/62706/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6346_full -> Patchwork_13420_full
On 6/25/19 8:26 AM, Matt Roper wrote:
On Fri, Jun 14, 2019 at 03:17:39PM -0700, Matt Roper wrote:
On Fri, Jun 14, 2019 at 02:37:49PM -0700, José Roberto de Souza wrote:
EHL can have up to one VECS(video enhancement) engine, so add it to
the device_info.
Bspec 29150 has a footnote on VEbox
On Fri, Jun 21, 2019 at 05:24:10PM -0700, Souza, Jose wrote:
> On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> > Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> > mapping.
> > Because of this, both the bspec documentation and our i915 code has
> > used
> > the term "port"
On 6/25/19 1:11 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-06-25 21:06:10)
On 6/25/19 11:47 AM, Chris Wilson wrote:
Do we even need to dump them? They are almost all static, with the
exception of debug level and ads address? Is it useful?
In my experience it can be
Quoting Daniele Ceraolo Spurio (2019-06-25 21:06:10)
>
>
> On 6/25/19 11:47 AM, Chris Wilson wrote:
> > Do we even need to dump them? They are almost all static, with the
> > exception of debug level and ads address? Is it useful?
>
> In my experience it can be useful when we get a bug report
On 6/25/19 11:47 AM, Chris Wilson wrote:
Quoting Michal Wajdeczko (2019-06-25 19:30:18)
On Tue, 25 Jun 2019 19:45:47 +0200, Chris Wilson
wrote:
Use hex_dump_to_buffer() to compress the parameter debug into a single
line for less verbose debug logs.
Signed-off-by: Chris Wilson
Cc: Michal
On Tue, Jun 25, 2019 at 09:57:38PM +0300, Imre Deak wrote:
> On Tue, Jun 25, 2019 at 04:53:01PM +0300, Ville Syrjälä wrote:
> > On Thu, Jun 20, 2019 at 05:05:53PM +0300, Imre Deak wrote:
> > > For consistency s/intel_get_shared_dpll()/intel_reserve_shared_dplls()/
> > > to better match
Add the context pin/unpin events to the trace for post-mortem debugging.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_context.c| 10 ++
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 3 +++
2 files changed, 13 insertions(+)
diff --git
Quoting Michal Wajdeczko (2019-06-25 18:47:55)
> On Tue, 25 Jun 2019 18:41:07 +0200, Robert M. Fosha
> wrote:
>
> > Detect GuC firmware load failure due to an exception during execution
> > in GuC firmware. Output the GuC EIP where exception occurred to dmesg
> > for GuC debug information.
> >
== Series Details ==
Series: drm/i915/guc: Add debug capture of GuC exception (rev2)
URL : https://patchwork.freedesktop.org/series/62554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6346 -> Patchwork_13421
Summary
== Series Details ==
Series: series starting with [01/20] drm/i915/execlists: Convert recursive
defer_request() into iterative (rev3)
URL : https://patchwork.freedesktop.org/series/62706/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6346 -> Patchwork_13420
On Tue, Jun 25, 2019 at 05:12:52PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 20, 2019 at 05:05:58PM +0300, Imre Deak wrote:
> > Add state verification for the TypeC port mode wrt. the port's AUX power
> > well enabling/disabling. Also check the correctness of changing the port
> > mode:
> > - When
On Mon, Jun 10, 2019 at 11:19:14AM +0300, Lionel Landwerlin wrote:
We got the wrong offsets (could they have changed?). New values were
computed off an error state by looking up the register offset in the
context image as written by the HW.
Signed-off-by: Lionel Landwerlin
Fixes:
Hi Alastair,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.2-rc6 next-20190625]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
On Mon, Jun 24, 2019 at 11:34:42PM -0700, Lucas De Marchi wrote:
> On Mon, Jun 24, 2019 at 2:07 PM Manasi Navare
> wrote:
> >
> > In the transcoder port sync mode, the slave transcoders mask their vblanks
> > until master transcoder's vblank so while disabling them, make
> > sure slaves are
On Tue, Jun 25, 2019 at 04:53:01PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 20, 2019 at 05:05:53PM +0300, Imre Deak wrote:
> > For consistency s/intel_get_shared_dpll()/intel_reserve_shared_dplls()/
> > to better match intel_release_shared_dplls(). Also, pass to the
> > reserve/release and
On Mon, 2019-06-17 at 10:19 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Add missing VECS engine
> URL : https://patchwork.freedesktop.org/series/62143/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6277_full -> Patchwork_13297_full
>
On Tue, 25 Jun 2019 at 14:02, Chris Wilson wrote:
>
> Add the context pin/unpin events to the trace for post-mortem debugging.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Michal Wajdeczko (2019-06-25 19:30:18)
> On Tue, 25 Jun 2019 19:45:47 +0200, Chris Wilson
> wrote:
>
> > Use hex_dump_to_buffer() to compress the parameter debug into a single
> > line for less verbose debug logs.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Michal Wajdeczko
> > ---
>
On Tue, 25 Jun 2019 at 14:03, Chris Wilson wrote:
>
> Always initialise the refcount, even for the embedded timelines inside
> mock devices.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
On Tue, 25 Jun 2019 at 14:02, Chris Wilson wrote:
>
> As we wait upon the request, we should be sure to hold our own reference
> for our checks.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
On Mon, 24 Jun 2019 at 06:45, Chris Wilson wrote:
>
> Our general rule is to use is/has as the verb for boolean functions,
> rename intel_wakeref_active to intel_wakeref_is_active so the question
> being asked is clear.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
On Tue, Jun 25, 2019 at 04:42:01PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 20, 2019 at 05:05:49PM +0300, Imre Deak wrote:
> > Make the order during detection more consistent: first reset the TypeC
> > port mode if needed (adding new helpers for this), then detect any
> > connected sink.
> >
> >
On Tue, 25 Jun 2019 19:45:47 +0200, Chris Wilson
wrote:
Use hex_dump_to_buffer() to compress the parameter debug into a single
line for less verbose debug logs.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc.c | 6 --
1 file changed, 4
== Series Details ==
Series: series starting with [01/20] drm/i915/execlists: Convert recursive
defer_request() into iterative (rev3)
URL : https://patchwork.freedesktop.org/series/62706/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit:
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.
For PS_INVOCATION_COUNT we've got the following piglit tests :
Hi,
Compile tested /o\
Lionel Landwerlin (3):
drm/i915: fix whitelist selftests with readonly registers
drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
drivers/gpu/drm/i915/gt/intel_workarounds.c| 16 +++-
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6
CFL:C0+ changed the status of those registers which are now
blacklisted by default.
This is breaking a number of CTS tests on GL & Vulkan :
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
(GL)
== Series Details ==
Series: series starting with [01/20] drm/i915/execlists: Convert recursive
defer_request() into iterative (rev3)
URL : https://patchwork.freedesktop.org/series/62706/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d5806bbd1145 drm/i915/execlists: Convert
On Tue, 25 Jun 2019 at 14:02, Chris Wilson wrote:
>
> Switch from passing the i915 container to newly named struct intel_gt.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
On Tue, 25 Jun 2019 at 14:03, Chris Wilson wrote:
>
> As this engine owns the lock around rq->sched.link (for those waiters
> submitted to this engine), we can use that link as an element in a local
> list. We can thus replace the recursive algorithm with an iterative walk
> over the ordered list
Hi Alastair,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.2-rc6 next-20190625]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 33 ---
.../drm/i915/display/intel_display_power.h|
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
From: Mahesh Kumar
Create a helper function to get ddc pin according to port number.
Cc: Anusha Srivatsa
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
From: Mahesh Kumar
TGL has 3 combo-phy ports. This patch adds offset of third port to
combo-phy port register macros.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++-
drivers/gpu/drm/i915/i915_reg.h
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
distinction clear and update vdsc code path.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file changed, 9 insertions(+), 3
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 9
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
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