On 27/06/2019 21:56, Matthew Auld wrote:
From: Abdiel Janulgue
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 57 +++
include/uapi/drm/i915_drm.h
On 27/06/2019 21:56, Matthew Auld wrote:
From: Abdiel Janulgue
This call will specify which memory region an object should be placed.
Note that changing the object's backing storage should be immediately
done after an object is created or if it's not yet in use, otherwise
this will fail on a
On 27/06/2019 21:15, Andi Shyti wrote:
Hi Tvrtko,
+const struct intel_execution_engine2 *
+gem_eb_flags_to_engine(unsigned int flags)
+{
+ const struct intel_execution_engine2 *e2;
+
+ __for_each_static_engine(e2) {
+ if (e2->flags == flags)
+
Quoting Lionel Landwerlin (2019-06-28 00:53:09)
> On 27/06/2019 14:53, Chris Wilson wrote:
> > Magic! As we can't rely on our selftests to verify that this allows
> > access from user batches, could you poke Anuj for another tested by?
> > -Chris
> >
> I'll let Anuj answer.
>
> Do I need Cc:
Quoting Matthew Auld (2019-06-27 21:56:30)
> +int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
> +{
> + struct drm_i915_gem_context_param *args = data;
The plan was to use the upper_32_bits() or whatever as the class. To
Quoting Matthew Auld (2019-06-27 21:56:25)
> From: Abdiel Janulgue
>
> Add a new CPU mmap implementation that allows multiple fault handlers
> that depends on the object's backing pages.
>
> Note that we multiplex mmap_gtt and mmap_offset through the same ioctl,
> and use the zero extending
Quoting Matthew Auld (2019-06-27 21:56:24)
> + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
Strictly speaking, it's not actually VM_IO as we do not wrap and expose
mmio registers to userspace.
-Chris
___
Intel-gfx mailing list
Quoting Matthew Auld (2019-06-27 21:56:24)
> + if (node->readonly) {
Note that we can now drop the readonly field from the node as we only
added it for out benefit. Now we've extended the vma impl, we can use
our obj readonly flag directly.
-Chris
Quoting Matthew Auld (2019-06-27 21:56:24)
> +int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> +{
> + struct drm_vma_offset_node *node;
> + struct drm_file *priv = filp->private_data;
> + struct drm_device *dev = priv->minor->dev;
> + struct
Quoting Matthew Auld (2019-06-27 21:56:24)
> +static void i915_gem_vm_open(struct vm_area_struct *vma)
> +{
> + struct i915_mmap_offset *priv = vma->vm_private_data;
> + struct drm_i915_gem_object *obj = priv->obj;
> +
> + drm_gem_object_get(>base);
Pleae use the right getters,
This patch adds support for DPLL4 on EHL that include the
following restrictions:
- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
DPLL4 can be used with other DDIs, including DDID
(combo port A external usage).
- DPLL4 cannot be enabled when DC5 or DC6 are enabled.
- The
Quoting Matthew Auld (2019-06-27 21:56:20)
> From: Daniele Ceraolo Spurio
>
> We can't fence anything without aperture.
s/aperture/fence registers/
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Matthew Auld (2019-06-27 21:56:19)
> From: Daniele Ceraolo Spurio
>
> Done by returning -ENODEV from the map_gtt version ioctl.
>
> Cc: Antonio Argenziano
> Cc: Matthew Auld
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 1 file changed, 2
Quoting Matthew Auld (2019-06-27 21:56:15)
> int i915_gem_freeze(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e4f811fdaedc..958c61e88200 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++
On 27/06/2019 14:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 10:01:15)
CFL:C0+ changed the status of those registers which are now
blacklisted by default.
This is breaking a number of CTS tests on GL & Vulkan :
Quoting Matthew Auld (2019-06-27 21:56:12)
> We need to add support for pread'ing an LMEM object.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
> drivers/gpu/drm/i915/i915_gem.c | 6 ++
>
Quoting Matthew Auld (2019-06-27 21:56:11)
> @@ -1020,16 +1022,23 @@ static void reloc_cache_reset(struct reloc_cache
> *cache)
> i915_gem_object_finish_access((struct drm_i915_gem_object
> *)cache->node.mm);
> } else {
> wmb();
> -
Quoting Matthew Auld (2019-06-27 21:56:10)
> Signed-off-by: Matthew Auld
> ---
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 122 +-
> 1 file changed, 121 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>
Quoting Matthew Auld (2019-06-27 21:56:09)
> We also want to test LLC.
Then add a test for llc/snoop. It should be fine if it is physically
tagged...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
== Series Details ==
Series: Enable Transcoder Port Sync feature for Tiled displays (rev4)
URL : https://patchwork.freedesktop.org/series/59837/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1ed185770840 drm/i915/display: Rename update_crtcs() to commit_modeset_enables()
Quoting Matthew Auld (2019-06-27 21:56:06)
> We can already clear an object with the blt, so try to do the same to
> support copying from one object backing store to another. Really this is
> just object -> object, which is not that useful yet, what we really want
> is two backing stores, but that
Quoting Matthew Auld (2019-06-27 21:56:05)
> From: Abdiel Janulgue
>
> We can create LMEM objects, but we also need to support mapping them
> into kernel space for internal use.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> ---
>
Quoting Matthew Auld (2019-06-27 21:56:03)
> We currently define LMEM, or local memory, as just another memory
> region, like system memory or stolen, which we can expose to userspace
> and can be mapped to the CPU via some BAR.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel
Quoting Matthew Auld (2019-06-27 21:56:03)
> We currently define LMEM, or local memory, as just another memory
> region, like system memory or stolen, which we can expose to userspace
> and can be mapped to the CPU via some BAR.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel
Quoting Matthew Auld (2019-06-27 21:56:02)
> From: Abdiel Janulgue
>
> Exposes available regions for the platform. Shared memory will
> always be available.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>
Quoting Matthew Auld (2019-06-27 21:56:02)
> From: Abdiel Janulgue
>
> Exposes available regions for the platform. Shared memory will
> always be available.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>
Quoting Matthew Auld (2019-06-27 21:56:01)
> Volatile objects are marked as DONTNEED while pinned, therefore once
> unpinned the backing store can be discarded.
Apply to existing code...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Matthew Auld (2019-06-27 21:56:00)
> Some objects may need to be allocated as a continuous block, thinking
> ahead the various kernel io_mapping interfaces seem to expect it.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
>
Quoting Matthew Auld (2019-06-27 21:55:59)
> +int i915_memory_region_evict(struct intel_memory_region *mem,
What type is this again?
> +resource_size_t target)
> +{
> + struct drm_i915_gem_object *obj, *on;
> + resource_size_t found;
> +
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt
Create a new hook commit_modeset_disables() consistent with the naming
in drm atomic helpers and similar to the commit_modeset_enables() hook.
This helps better organize the disable sequence in atomic_commit_tail()
and move that to this disable hook.
No functional change
v2:
* Create a helper
Quoting Matthew Auld (2019-06-27 21:55:58)
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> b/drivers/gpu/drm/i915/intel_memory_region.c
> new file mode 100644
> index ..4c89853a7769
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -0,0 +1,215 @@
>
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use port clock to set correct N
value
URL : https://patchwork.freedesktop.org/series/62895/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use port clock to set correct N
Quoting Matthew Auld (2019-06-27 21:55:57)
> Simple buddy allocator. We want to allocate properly aligned
> power-of-two blocks to promote usage of huge-pages for the GTT, so 64K,
> 2M and possibly even 1G. While we do support allocating stuff at a
> specific offset, it is more intended for
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by hardware for deep color modes.
v2: Remove unnecessary initialization of size
Signed-off-by: Aditya Swarup
Cc: Clint Taylor
Cc: Jani Nikula
Cc: Ville
Use port_clock to check the clock values in n/cts lookup table instead
of crtc_clock. As port_clock is already adjusted based on color mode set
(8 bit or deep color), this will help in checking clock values for deep
color modes from n/cts lookup table.
Signed-off-by: Aditya Swarup
Cc: Clint
== Series Details ==
Series: Set correct values for N in deep color mode
URL : https://patchwork.freedesktop.org/series/62894/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use port clock to set correct N value
Okay!
Commit: drm/i915: Add
== Series Details ==
Series: Introduce memory region concept (including device local memory) (rev2)
URL : https://patchwork.freedesktop.org/series/56683/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: buddy allocator
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by hardware for deep color modes.
Signed-off-by: Aditya Swarup
Cc: Clint Taylor
Cc: Jani Nikula
Cc: Ville Syrjälä
---
Use port_clock to check the clock values in n/cts lookup table instead
of crtc_clock. As port_clock is already adjusted based on color mode set
(8 bit or deep color), this will help in checking clock values for deep
color modes from n/cts lookup table.
Signed-off-by: Aditya Swarup
Cc: Clint
Patch series to set correct values for N based on port clock in deep
color mode. Currently, the hardware doesn't set the correct N in deep
color mode.
Aditya Swarup (2):
drm/i915: Use port clock to set correct N value
drm/i915: Add N & CTS values for 10/12 bit deep color
== Series Details ==
Series: Introduce memory region concept (including device local memory) (rev2)
URL : https://patchwork.freedesktop.org/series/56683/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6f6eb8a214a1 drm/i915: buddy allocator
-:29: WARNING:FILE_PATH_CHANGES:
Quoting Daniele Ceraolo Spurio (2019-06-27 21:32:25)
> The CSB format has been reworked for Gen12 to include information on
> both the context we're switching away from and the context we're
> switching to. After the change, some of the events don't have their
> own bit anymore and need to be
On Thu, 2019-06-27 at 12:48 +0300, Imre Deak wrote:
> On Thu, Jun 27, 2019 at 02:55:21AM +0300, Souza, Jose wrote:
> > On Thu, 2019-06-20 at 17:05 +0300, Imre Deak wrote:
> > > Make the order during detection more consistent: first reset the
> > > TypeC
> > > port mode if needed (adding new
From: Abdiel Janulgue
Add a new CPU mmap implementation that allows multiple fault handlers
that depends on the object's backing pages.
Note that we multiplex mmap_gtt and mmap_offset through the same ioctl,
and use the zero extending behaviour of drm to differentiate between
them, when we
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the
From: Abdiel Janulgue
If there is no aperture we can't use map_gtt to map dumb buffers, so we
need a cpu-map based path to do it. We prefer map_gtt on platforms that
do have aperture.
Signed-off-by: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
From: Abdiel Janulgue
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 57 +++
include/uapi/drm/i915_drm.h | 39 +
2 files changed,
We are going want to able to move objects between different regions
like system memory and local memory. In the future everything should
be just another region.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
Hack patch to default all userspace allocations to LMEM. Useful for
testing purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem.c | 37 +
1 file changed, 37 insertions(+)
diff --git
We need to add support for pwrite'ing an LMEM object.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/intel_region_lmem.c | 75
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
From: Abdiel Janulgue
LMEM can be accessed by the CPU through a BAR. The mapping itself should
be 1:1.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_region_lmem.c | 16
drivers/gpu/drm/i915/intel_region_lmem.h
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Abdiel Janulgue
This call will specify which memory region an object should be placed.
Note that changing the object's backing storage should be immediately
done after an object is created or if it's not yet in use, otherwise
this will fail on a busy object.
Signed-off-by: Abdiel
From: Abdiel Janulgue
Fault handler to handle missing pages to be filled depending on an
object's backing storage. Handle also changes needed to refault pages
depending on fault handler usage.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
We need to add support for pread'ing an LMEM object.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 6 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 76
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
1 file changed, 22 insertions(+), 14
Add LMEM support for the CPU reloc path. When doing relocations we have
both a GPU and CPU reloc path, as well as some debugging options to force a
particular path. The GPU reloc path is preferred when the object
is not currently idle, otherwise we use the CPU reloc path. Since we
can't kmap the
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ---
From: Abdiel Janulgue
This enables us to store extra data within vma->vm_private_data and assign
the pagefault ops for each mmap instance.
We replace the core drm_gem_mmap implementation to overcome the limitation
in having only a single offset node per gem object, allowing us to have
multiple
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 161 ++
1 file changed, 161 insertions(+)
diff --git
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 66 +++---
From: Daniele Ceraolo Spurio
Done by returning -ENODEV from the map_gtt version ioctl.
Cc: Antonio Argenziano
Cc: Matthew Auld
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 67 ++-
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 73 +--
Simple buddy allocator. We want to allocate properly aligned
power-of-two blocks to promote usage of huge-pages for the GTT, so 64K,
2M and possibly even 1G. While we do support allocating stuff at a
specific offset, it is more intended for preallocating portions of the
address space, say for an
Some objects may need to be allocated as a continuous block, thinking
ahead the various kernel io_mapping interfaces seem to expect it.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
Support basic eviction for regions.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 7 ++
drivers/gpu/drm/i915/i915_gem.c | 16
drivers/gpu/drm/i915/intel_memory_region.c| 89 ++-
We also want to test LLC.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 122 +-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 29
In preparation for upcoming devices with device local memory, introduce the
concept of different memory regions, and a simple buddy allocator to manage
them.
One of the concerns raised from v1 was around not using enough of TTM, which is
a fair criticism, so trying to get better alignment here is
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Signed-off-by: CQ Tang
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 18 -
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and
We can already clear an object with the blt, so try to do the same to
support copying from one object backing store to another. Really this is
just object -> object, which is not that useful yet, what we really want
is two backing stores, but that will require some vma rework first,
otherwise we
Using the gpu to write to some dword over a number of pages is rather
useful, and we already have two copies of such a thing, and we don't
want a third so move it to utils. There is probably some other stuff
also...
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c |
== Series Details ==
Series: drm/i915/tgl: Gen12 csb support
URL : https://patchwork.freedesktop.org/series/62890/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72f2fb88c700 drm/i915/tgl: Gen12 csb support
-:41: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'csb_dw' may be better
On Wed, 2019-06-26 at 23:50 +0300, Imre Deak wrote:
> For using the correct AUX power domains we have to sanitize the TypeC
> port mode early, so move that before encoder sanitization. To do this
> properly read out the actual port mode instead of just relying on the
> VBT legacy port flag (which
The CSB format has been reworked for Gen12 to include information on
both the context we're switching away from and the context we're
switching to. After the change, some of the events don't have their
own bit anymore and need to be inferred from other values in the csb.
One of the context IDs
Quoting Andi Shyti (2019-06-27 21:15:30)
> > +bool gem_context_has_engine_map(int fd, uint32_t ctx)
> > +{
> > + struct drm_i915_gem_context_param param = {
> > + .param = I915_CONTEXT_PARAM_ENGINES,
> > + .ctx_id = ctx
> > + };
> > + int ret;
> > +
> > +
On Thu, Jun 27, 2019 at 12:15:26PM -0700, Manasi Navare wrote:
On Tue, Jun 25, 2019 at 10:54:19AM -0700, Lucas De Marchi wrote:
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are
On Thu, Jun 27, 2019 at 12:31:30PM -0700, Jose Souza wrote:
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the
Hi Tvrtko,
> +const struct intel_execution_engine2 *
> +gem_eb_flags_to_engine(unsigned int flags)
> +{
> + const struct intel_execution_engine2 *e2;
> +
> + __for_each_static_engine(e2) {
> + if (e2->flags == flags)
> + return e2;
> + }
> +
> +
On Mon, Jun 24, 2019 at 11:34:42PM -0700, Lucas De Marchi wrote:
> On Mon, Jun 24, 2019 at 2:07 PM Manasi Navare
> wrote:
> >
> > In the transcoder port sync mode, the slave transcoders mask their vblanks
> > until master transcoder's vblank so while disabling them, make
> > sure slaves are
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> From: Imre Deak
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power well#1
On Thu, Jun 27, 2019 at 07:28:15PM +, Souza, Jose wrote:
> On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > On TGL the special EDP transcoder is gone and it should be handled by
> > transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
On Thu, 2019-06-27 at 12:28 -0700, José Roberto de Souza wrote:
> On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > On TGL the special EDP transcoder is gone and it should be handled
> > by
> > transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre Deak
>
On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre
On Tue, Jun 25, 2019 at 10:54:19AM -0700, Lucas De Marchi wrote:
> From: Imre Deak
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power
== Series Details ==
Series: drm/i915: Add icl mipi dsi properties (rev2)
URL : https://patchwork.freedesktop.org/series/62770/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c146c1078623 drm/i915: Add icl mipi dsi properties
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should
== Series Details ==
Series: series starting with [1/8] drm/i915/selftests: Lock the drm_mm while
modifying
URL : https://patchwork.freedesktop.org/series/62851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6375 -> Patchwork_13455
== Series Details ==
Series: drm/i915/execlists: Hesitate before slicing
URL : https://patchwork.freedesktop.org/series/62867/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/execlists: Hesitate before slicing
== Series Details ==
Series: drm/panel: make drm_panel.h self-contained
URL : https://patchwork.freedesktop.org/series/62850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6375 -> Patchwork_13454
Summary
---
1 - 100 of 242 matches
Mail list logo
