From: Lionel Landwerlin
We want to set this flag in the next commit on requests containing
perf queries so that the result of the perf query can just be a delta
of global counters, rather than doing post processing of the OA
buffer.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
[i
On Tue, Jul 09, 2019 at 05:11:08AM -0700, Rodrigo Vivi wrote:
On Mon, Jul 08, 2019 at 04:16:20PM -0700, Lucas De Marchi wrote:
From: Mahesh Kumar
Create a helper function to get ddc pin according to port number.
Could you please explain why we can't simply reuse the icl one?
I couldn't find
On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Mar
On Mon, Jul 08, 2019 at 06:07:17PM -0700, Jose Souza wrote:
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggest
On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo
On Mon, Jul 08, 2019 at 04:16:26PM -0700, Lucas De Marchi wrote:
> From: Rodrigo Vivi
>
> Previously, the recommended B credit for all platforms was 24 / number
> of pipes, which would give 6 for newer platforms with 4 pipes. However 6
> is not enough and we need 12 on these cases.
>
> We also n
On Tue, Jul 09, 2019 at 12:50:10AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915: Clear the shared PLL from the
> put_dplls() hook
> URL : https://patchwork.freedesktop.org/series/63384/
> State : failure
Thanks for the review pushed to -dinq
Separate local includes with a blank line and sort the groups
alphabetically.
v2: don't make intel_tc.h be the first include
v3: don't make local includes be included first
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.h
On Mon, Jul 08, 2019 at 04:16:13PM -0700, Lucas De Marchi wrote:
> From: Imre Deak
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power w
== Series Details ==
Series: drm/i915: Lock the engine while dumping the active request (rev2)
URL : https://patchwork.freedesktop.org/series/63442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6441 -> Patchwork_13583
Summ
== Series Details ==
Series: drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset
URL : https://patchwork.freedesktop.org/series/63443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6440 -> Patchwork_13582
=
Quoting Chris Wilson (2019-07-07 22:00:18)
> The radix levels of each page directory are easily determined so replace
> the numerous hardcoded constants with precomputed derived constants.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++
Right idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed
_ight idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed
On Tue, Jul 9, 2019 at 11:42 AM Ser, Simon wrote:
>
> On Tue, 2019-07-09 at 11:32 -0300, Rodrigo Siqueira wrote:
> > On Wed, Jul 3, 2019 at 9:15 AM Ser, Simon wrote:
> > > On Tue, 2019-06-18 at 18:56 -0300, Rodrigo Siqueira wrote:
> > > > On Thu, Jun 13, 2019 at 11:54 AM Liviu Dudau
> > > > wro
Chris Wilson writes:
> In preparation for refactoring the free/clear/alloc, first move the code
> around so that we can avoid forward declarations in the next set of
> patches.
>
> Signed-off-by: Chris Wilson
Diff got funky at some point but after applying
end result looked good.
Reviewed-by:
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, July 9, 2019 8:06 PM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [V3] drm/i915: Add icl mipi dsi properties
>
> On Thu, Jun 27, 2019 at 08:54:57PM +0530, Vandita Kulkarni wrote:
>
On Mon, 2019-07-08 at 22:16 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-07-08 22:11:15)
> > On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> > > We now track features correctly instead of probing i915-
> > > >engine[RCS0]
> > > which is much more flexible and avoids any nasty
Quoting Mika Kuoppala (2019-07-09 15:43:15)
> Chris Wilson writes:
> > static struct i915_page_directory *__alloc_pd(void)
> > {
> > struct i915_page_directory *pd;
> >
> > pd = kmalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
> > -
> > if (unlikely(!pd))
> > return N
Chris Wilson writes:
> The page directory extends the page table with the shadow entries. Make
> the page directory struct embed the page table for easier code reuse.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt
On Tue, 2019-07-09 at 11:32 -0300, Rodrigo Siqueira wrote:
> On Wed, Jul 3, 2019 at 9:15 AM Ser, Simon wrote:
> > On Tue, 2019-06-18 at 18:56 -0300, Rodrigo Siqueira wrote:
> > > On Thu, Jun 13, 2019 at 11:54 AM Liviu Dudau wrote:
> > > > On Wed, Jun 12, 2019 at 11:16:02PM -0300, Brian Starkey wr
On Mon, 8 Jul 2019 16:51:14 +0530
Ramalingam C wrote:
> drm function is defined and exported to update a connector's
> content protection property state and to generate a uevent along
> with it.
>
> Need ACK for the uevent from userspace consumer.
>
> v2:
> Update only when state is differen
== Series Details ==
Series: drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset
URL : https://patchwork.freedesktop.org/series/63443/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Hold the vma manager lock w
On Thu, Jun 27, 2019 at 08:54:57PM +0530, Vandita Kulkarni wrote:
> Add scaling and panel orientation properties for
> icl mipi dsi.
>
> v2: Add platform specific function (Ville)
> v3: Remove redundant check and update scaler call (Jani, Ville)
>
> Signed-off-by: Vandita Kulkarni
Pushed to din
On Wed, Jul 3, 2019 at 9:15 AM Ser, Simon wrote:
>
> On Tue, 2019-06-18 at 18:56 -0300, Rodrigo Siqueira wrote:
> > On Thu, Jun 13, 2019 at 11:54 AM Liviu Dudau wrote:
> > > On Wed, Jun 12, 2019 at 11:16:02PM -0300, Brian Starkey wrote:
> > > > Add support in igt_kms for writeback connectors, wit
On Mon, 8 Jul 2019 16:51:11 +0530
Ramalingam C wrote:
> This patch adds a DRM ENUM property to the selected connectors.
> This property is used for mentioning the protected content's type
> from userspace to kernel HDCP authentication.
>
> Type of the stream is decided by the protected content
Quoting Lionel Landwerlin (2019-07-09 13:33:48)
> We want to set this flag in the next commit on requests containing
> perf queries so that the result of the perf query can just be a delta
> of global counters, rather than doing post processing of the OA
> buffer.
>
> Signed-off-by: Lionel Landwer
Better subject would be: "Enable HuC (through GuC) on supported platforms"
Quoting Michal Wajdeczko (2019-07-03 14:36:40)
> GuC firmware is now mature, so let it run by default.
That's bit of a misleading statement (in more than one way).
"Enable loading HuC firmware (through GuC) to unlock
adva
We cannot let the request be retired and freed while we are trying to
dump it during error capture. It is not sufficient just to grab a
reference to the request, as during retirement we may free the ring
which we are also dumping. So take the engine lock to prevent retiring
and freeing of the reque
Quoting Chris Wilson (2019-07-09 14:03:03)
> We cannot let the request be retired and freed while we are trying to
> dump it during error capture. It is not sufficient just to grab a
> reference to the request, as during retirement we may free the ring
> which we are also dumping. So take the engin
_ight idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed
Hi James,
James Bottomley schreef op za 29-06-2019 om 11:56 [-0700]:
> The symptoms are really weird: the screen image is locked in place.
> The machine is still functional and if I log in over the network I can
> do anything I like, including killing the X server and the display will
> never alt
== Series Details ==
Series: drm/i915: Lock the engine while dumping the active request
URL : https://patchwork.freedesktop.org/series/63442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6440 -> Patchwork_13581
Summary
---
Hi Oleg,
First of all, thank you for your patch and for working in this issue.
A few comments inline.
On Thu, Jul 4, 2019 at 5:54 AM Oleg Vasilev wrote:
>
> Bring dmabuf sharing through implementing prime_import_sg_table callback.
> This will help to validate userspace conformance in prime conf
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev8)
URL : https://patchwork.freedesktop.org/series/60916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6440 -> Patchwork_13580
Summary
---
*
On Mon, 8 Jul 2019 14:42:29 +0530
Ramalingam C wrote:
> On 2019-07-08 at 12:59:59 +0300, Pekka Paalanen wrote:
> > On Mon, 8 Jul 2019 12:52:17 +0300
> > Pekka Paalanen wrote:
> >
> > > On Fri, 5 Jul 2019 06:16:37 +0530
> > > Ramalingam C wrote:
> > >
> > > > This patch adds a DRM ENUM pr
== Series Details ==
Series: Initial support for Tiger Lake (rev2)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6433_full -> Patchwork_13574_full
Summary
---
**S
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev8)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/perf: ensure we keep a reference on the driver
Okay!
Commit: d
Quoting Chris Wilson (2019-07-09 14:10:52)
> Quoting Lionel Landwerlin (2019-07-09 13:53:38)
> > On 09/07/2019 15:33, Lionel Landwerlin wrote:
> > >
> > > +static int eb_oa_config(struct i915_execbuffer *eb)
> > > +{
> > > + int ret;
> > > +
> > > + if (!eb->oa_config)
> > > +
Quoting Lionel Landwerlin (2019-07-09 13:53:38)
> On 09/07/2019 15:33, Lionel Landwerlin wrote:
> >
> > +static int eb_oa_config(struct i915_execbuffer *eb)
> > +{
> > + int ret;
> > +
> > + if (!eb->oa_config)
> > + return 0;
> > +
> > + ret = i915_mutex_lock_interruptib
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev8)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
77863bf0383c drm/i915/perf: ensure we keep a reference on the driver
8f7a0808f250 drm/i915/perf: ad
We cannot let the request be retired and freed while we are trying to
dump it during error capture. It is not sufficient just to grab a
reference to the request, as during retirement we may free the ring
which we are also dumping. So take the engine lock to prevent retiring
and freeing of the reque
On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> On TGL the port programming for combophy is very similar to ICL, so
> adapt the callers to possibly use the different register values.
>
> Cc: Vandita Kulkarni
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> ---
> drivers
On 09/07/2019 15:33, Lionel Landwerlin wrote:
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int ret;
+
+ if (!eb->oa_config)
+ return 0;
+
+ ret = i915_mutex_lock_interruptible(&eb->i915->drm);
+ if (ret)
+ return ret;
This is a
On Mon, Jul 08, 2019 at 04:16:29PM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> This register definition changed from ICL and has now another meaning.
> Use the right bits on TGL.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/
== Series Details ==
Series: drm/i915: Remove unused i915_gem_context_lookup_engine
URL : https://patchwork.freedesktop.org/series/63437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6440 -> Patchwork_13579
Summary
---
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-07-09 13:24:27)
>> Chris Wilson writes:
>>
>> > We only use the dma pages for scratch, and so do not need to allocate
>> > the extra storage for the shadow page directory.
>> >
>> > Signed-off-by: Chris Wilson
>> > Cc: Mika Kuoppala
>> > ---
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On Tiger Lake there is one more pipe - check if it's fused.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/i915_reg.h
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This als
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process m
We want to set this flag in the next commit on requests containing
perf queries so that the result of the perf query can just be a delta
of global counters, rather than doing post processing of the OA
buffer.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_drm.h
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particu
The i915 perf stream has its own file descriptor and is tied to
reference of the driver. We haven't taken care of keep the driver
alive.
Signed-off-by: Lionel Landwerlin
Suggested-by: Chris Wilson
Fixes: eec688e1420da5 ("drm/i915: Add i915 perf infrastructure")
Reviewed-by: Chris Wilson
---
dr
This was dropped from the original patch series, we weren't sure
whether it was needed at the time. More recent tests show it's
definitely needed to have acurate performance data.
Signed-off-by: Lionel Landwerlin
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
Acked-by: Ch
We have a bunch of offsets in the scratch buffer. As we're about to
add some more, let's group all of the offsets in a common location.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++--
drivers/gpu/drm/i915/gt/intel_gt_types.h
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h |
Hi again,
This break one of the commit in 2 so that hold preemption
infrastructure is separate from perf using the feature.
Hopefully it addresses the last bits of locking issues around OA
configurations.
Finally added the Rbs from Chris.
Thanks a lot,
Lionel Landwerlin (13):
drm/i915/perf:
Quoting Mika Kuoppala (2019-07-09 13:24:27)
> Chris Wilson writes:
>
> > We only use the dma pages for scratch, and so do not need to allocate
> > the extra storage for the shadow page directory.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/i915_ge
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
As per BSPec #44455 the IDs seems correct.
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pc
Chris Wilson writes:
> We only use the dma pages for scratch, and so do not need to allocate
> the extra storage for the shadow page directory.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 192
> drivers/gpu/drm/
== Series Details ==
Series: drm/i915/selftests: Set igt_spinner.gt for early exit
URL : https://patchwork.freedesktop.org/series/63414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6433_full -> Patchwork_13573_full
Summar
On Mon, Jul 08, 2019 at 04:16:16PM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni
>
> Add a new pll array for Tiger Lake. The TC pll functions for type C will
> be covered in later patches after its phy is implemented.
>
> Cc: Madhav Chauhan
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Viv
On Mon, Jul 08, 2019 at 04:16:25PM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
>
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
> drivers/gpu/drm/i915
On Mon, Jul 08, 2019 at 04:16:20PM -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Create a helper function to get ddc pin according to port number.
Could you please explain why we can't simply reuse the icl one?
I couldn't find a new table for tgl on bspec...
>
> Cc: Anusha Srivatsa
On Mon, Jul 08, 2019 at 04:16:07PM -0700, Lucas De Marchi wrote:
> From: Radhakrishna Sripada
>
> Add the enum additions to TGP.
>
> Cc: Rodrigo Vivi
> Cc: Joonas Lahtinen
> Cc: David Weinehall
> Cc: James Ausmus
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Lucas De Marchi
Revie
On Tue, Jun 25, 2019 at 10:54:17AM -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
> register (and format).
>
> Cc: Ingo Molnar
> Cc: H. Peter Anvin
> Cc: x...@kernel.org
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Viv
On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> From: Mika Kahola
>
> Add power well 5 to support 4th pipe and transcoder on TGL.
>
> Cc: James Ausmus
> Cc: Imre Deak
> Signed-off-by: Mika Kahola
> Signed-off-by: Lucas De Marchi
> ---
> .../drm/i915/display/intel_display_
On Mon, Jul 08, 2019 at 04:16:09PM -0700, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 10 ++
> 2 fi
== Series Details ==
Series: drm/i915/guc: Define GuC firmware version for Comet Lake (rev2)
URL : https://patchwork.freedesktop.org/series/62969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6433_full -> Patchwork_13572_full
==
On 09/07/2019 13:07, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:08)
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct
== Series Details ==
Series: drm/i915/execlists: Disable preemption under GVT (rev6)
URL : https://patchwork.freedesktop.org/series/62533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6438 -> Patchwork_13578
Summary
--
On 09/07/2019 14:04, Lionel Landwerlin wrote:
On 09/07/2019 13:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_oa_c
On 09/07/2019 14:06, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 11:59:31)
On 09/07/2019 12:58, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_config)
+
Quoting Lionel Landwerlin (2019-07-09 11:59:31)
> On 09/07/2019 12:58, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-09 10:32:05)
> >> +static int eb_oa_config(struct i915_execbuffer *eb)
> >> +{
> >> + int err;
> >> +
> >> + if (!eb->oa_config)
> >> + return
On 09/07/2019 13:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_oa_config *oa_config = stream->oa_config;
+ s
On 09/07/2019 12:58, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ err = i915_active_request_set(&eb->engine->last_oa_config,
+
On Mon, Jul 08, 2019 at 10:28:13AM -0700, Lucas De Marchi wrote:
> Make intel_tc.h the first include so we guarantee it's self-contained.
> Sort the rest. Same principle applies for includes in the header.
>
> v2: don't make intel_tc.h be the first include
>
> Signed-off-by: Lucas De Marchi
> --
>-Original Message-
>From: C, Ramalingam
>Sent: Monday, July 8, 2019 5:03 PM
>To: intel-gfx ; Daniel Vetter
>
>Cc: Shankar, Uma ; C, Ramalingam
>
>Subject: [PATCH v2] drm/i915/hdcp: debug logs for sink related failures
>
>Adding few more debug logs to identify the sink specific HDCP fail
On 09/07/2019 13:00, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:06)
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers)
On 09/07/2019 12:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:02)
+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
+ i915_reg_t reg, u32 offset, u32 dword_count)
+{
+ uint32_t d;
+
+ for (d = 0; d < dword_count; d++) {
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev2)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6438 -> Patchwork_13577
Summary
---
On Mon, Jul 08, 2019 at 10:28:12AM -0700, Lucas De Marchi wrote:
> Let's make the just created intel_tc.c already follow the trend of using
> i915 instead of dev_priv and calling the intel_uncore_*() functions.
>
> Signed-off-by: Lucas De Marchi
No changes since v1, so still r-b.
> ---
> drive
== Series Details ==
Series: drm/i915/userptr: Don't mark readonly objects as dirty
URL : https://patchwork.freedesktop.org/series/63434/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6437 -> Patchwork_13576
Summary
---
Regards
Shashank
On 7/9/2019 7:39 AM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check i
Quoting Lionel Landwerlin (2019-07-09 10:32:08)
> +static int query_perf_config_data(struct drm_i915_private *i915,
> + struct drm_i915_query_item *query_item,
> + bool use_uuid)
> +{
> + struct drm_i915_query_perf_config __user
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
> +static int emit_oa_config(struct drm_i915_private *i915,
> + struct i915_perf_stream *stream)
> {
> - u32 i;
> + struct i915_oa_config *oa_config = stream->oa_config;
> + struct i915_request *rq = stream->
Quoting Lionel Landwerlin (2019-07-09 10:32:06)
> We would like to make use of perf in Vulkan. The Vulkan API is much
> lower level than OpenGL, with applications directly exposed to the
> concept of command buffers (pretty much equivalent to our batch
> buffers). In Vulkan, queries are always limi
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
> +static int eb_oa_config(struct i915_execbuffer *eb)
> +{
> + int err;
> +
> + if (!eb->oa_config)
> + return 0;
> +
> + err = i915_active_request_set(&eb->engine->last_oa_config,
> +
Quoting Lionel Landwerlin (2019-07-09 10:32:02)
> +static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
> + i915_reg_t reg, u32 offset, u32 dword_count)
> +{
> + uint32_t d;
> +
> + for (d = 0; d < dword_count; d++) {
> + *cs++ = INTEL_
Quoting Lionel Landwerlin (2019-07-09 10:31:59)
> Reporting this version will help application figure out what level of
> the support the running kernel provides.
>
> v2: Add i915_perf_ioctl_version() (Chris)
>
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
-Chris
Quoting Lionel Landwerlin (2019-07-09 10:31:58)
> Signed-off-by: Lionel Landwerlin
> Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
Acked-by: Chris Wilson
(Acked-by-but-not-condoned-by? :)
-Chris
___
Intel-gfx mailing list
Intel
Quoting Lionel Landwerlin (2019-07-09 10:31:57)
> The i915 perf stream has its own file descriptor and is tied to
> reference of the driver. We haven't taken care of keep the driver
> alive.
>
> Signed-off-by: Lionel Landwerlin
> Suggested-by: Chris Wilson
> Fixes: eec688e1420da5 ("drm/i915: Add
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v
Quoting Tvrtko Ursulin (2019-07-09 10:31:05)
> From: Tvrtko Ursulin
>
> There are no known plans to start using it either.
>
> Signed-off-by: Tvrtko Ursulin
I think I used it in the patch/series and you talked me out of it.
Reviewed-by: Chris Wilson
-Chris
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_drm.h
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