[Intel-gfx] [CI] drm/i915/selftests: Check the context size

Add a redzone to our context image and check the HW does not write into after a context save, to verify that we have the correct context size. (This does vary with feature bits, so test with a live setup that should match how we run userspace.) v2: Check the redzone on every context unpin v3: Use

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Check the context size (rev4)

== Series Details == Series: drm/i915/selftests: Check the context size (rev4) URL : https://patchwork.freedesktop.org/series/65323/ State : success == Summary == CI Bug Log - changes from CI_DRM_6724 -> Patchwork_14068 Summary --- *

[Intel-gfx] ✓ Fi.CI.IGT: success for More WOPCM fixes (rev3)

== Series Details == Series: More WOPCM fixes (rev3) URL : https://patchwork.freedesktop.org/series/65263/ State : success == Summary == CI Bug Log - changes from CI_DRM_6718_full -> Patchwork_14054_full Summary --- **SUCCESS** No

[Intel-gfx] [PATCH v2 03/40] drm/i915/tgl: Move transcoders to pipes' powerwells

From: José Roberto de Souza When trying to read registers from transcoder C and D while PG3 is ON it causes unclaimed access warnings. Adding the powerwells for the pipes fixes the issue, but doesn't match the spec. Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drive

[Intel-gfx] [PATCH v2 06/40] drm/i915: Add transcoder restriction to PSR2

From: José Roberto de Souza According to PSR2_CTL definition in BSpec there is only one instance of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on TRANSCODER_EDP while on TGL PSR2 is only supported by TRANSCODER_A. Since BDW PSR is allowed on any port, but we need to restr

[Intel-gfx] [PATCH v2 02/40] drm/i915/tgl: add support for reading the timestamp frequency

From: Michel Thierry There are no changes with respect to GEN11, which Paulo wrote. This gets rid of the "Missing switch case in read_timestamp_frequency" message at boot for Tiger Lake. [ Lucas: BSpec: 10742 and 9024, but there's a mismatch on the values. Let's say a glitch in the spec. Test

[Intel-gfx] [PATCH v2 00/40] Tiger Lake batch 3

v2 of https://patchwork.freedesktop.org/series/65290/ Differences from previous version: - Update patches that were already made available to their latest versions - Remove non-working W/A - Clean a little bit the PSR commits - Run checkpatch and fix warning - Add patch to update DMC

[Intel-gfx] [PATCH v2 16/40] drm/i915: Add for_each_new_intel_connector_in_state()

From: José Roberto de Souza The same macro as for_each_new_connector_in_state() but it uses intel/i915 types instead of the drm ones. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.h | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/dr

[Intel-gfx] [PATCH v2 11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2

From: José Roberto de Souza This fix unclaimed access warnings: [ 245.525788] [ cut here ] [ 245.525884] Unclaimed read from register 0x62900 [ 245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915] [

[Intel-gfx] [PATCH v2 24/40] drm/i915/tgl: move DP_TP_* to transcoder

Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather than port-based. This add the new register address and changes the functions that are used with DDI on gen 12 to use the new registers. On MST the master transcoder is the one to be used. Cc: Rodrigo Vivi Cc: Ville Syrjälä

[Intel-gfx] [PATCH v2 10/40] drm/i915: Guard and warn if more than one eDP panel is present

From: José Roberto de Souza Now that is allowed to have PSR enabled in any port from BDW+, lets guard intel_psr_init_dpcd() against multiple eDP panels and warn about it. For now we will keep just one instance of PSR. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Sou

[Intel-gfx] [PATCH v2 22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards

From: Michel Thierry Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist). Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) d

[Intel-gfx] [PATCH v2 13/40] drm/i915/tgl: Access the right register when handling PSR interruptions

From: José Roberto de Souza For older gens PSR IIR and IMR had a fixed address that was not relative to anything, but from TGL those registers moved to each transcoder offset. So here adding a new macro and a new PSR irq handler with the transcoder parameter. Cc: Dhinakaran Pandiyan Cc: Rodrig

[Intel-gfx] [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()

From: José Roberto de Souza Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse order. v2: Fix additional blank line Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.h | 9

[Intel-gfx] [PATCH v2 08/40] drm/i915/psr: Only handle interruptions of the transcoder in use

From: José Roberto de Souza It was enabling and checking PSR interruptions in every transcoder while it should keep the interruptions on the non-used transcoders masked. This also already prepares for future when more than one PSR instance will be allowed. Cc: Dhinakaran Pandiyan Signed-off-by

[Intel-gfx] [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04

2 important fixes: - vblank counter is now working - PSR1 is working Cc: Jose Souza Cc: Anusha Srivatsa Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu

[Intel-gfx] [PATCH v2 05/40] drm/i915/psr: Make PSR registers relative to transcoders

From: José Roberto de Souza PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and using it makes more difficult for people with an PSR register address or

[Intel-gfx] [PATCH v2 14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

From: José Roberto de Souza TGL PSR2 HW supports a bigger resolution, so lets add it Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c | 5 - 1 file changed, 4 insertions(+), 1 deleti

[Intel-gfx] [PATCH v2 12/40] drm/i915/tgl: PSR link standby is not supported anymore

From: José Roberto de Souza According to BSpc if link standby is set on TGL+, PSR will not be enabled. Vendors should not use panels that requires link standby and even if they do, panel should assert a PSR error that will cause PSR to be disabled. BSpec: 50434 Signed-off-by: José Roberto de Sou

[Intel-gfx] [PATCH v2 19/40] drm/i915/tgl: Select master transcoder in DP MST

From: José Roberto de Souza On TGL the blending of all the streams have moved from DDI to transcoder, so now every transcoder working over the same MST port must send its stream to a master transcoder and master will send to DDI respecting the time slots. So here it is picking the lowest pipe/tr

[Intel-gfx] [PATCH v2 07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall

From: José Roberto de Souza No need to unmask PSR interrutpion if PSR is not enabled, better move the call to intel_psr_enable_source(). Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c

[Intel-gfx] [PATCH v2 01/40] drm/i915/tgl: disable DDIC

The current SKUs added for Tiger Lake don't have DDIC hooked up, even though it is supported by the SoC. The current state for these SKUs is problematic since while enabling the combo phy, PORT_COMP_DW* return 0x, which is invalid per register definition. During initialization we check wha

[Intel-gfx] [PATCH v2 15/40] drm/i915: Fix DP-MST crtc_mask

From: Ville Syrjälä Each fake MST encoder is tied to a specific pipe. Fix the encoder's crtc_mask to reflect that fact. Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[Intel-gfx] [PATCH v2 18/40] drm/i915: Disable pipes in reverse order

From: José Roberto de Souza Disable CRTC/pipes in reverse order because some features (MST in TGL+) requires master and slave relationship between pipes, so it should always pick the lowest pipe as master as it will be enabled first and disable in the reverse order so the master will be the last

[Intel-gfx] [PATCH v2 21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating

From: Michel Thierry HCP/MFX power gating is disabled by default, turn it on for the vd units available. User space will also issue a MI_FORCE_WAKEUP properly to wake up proper subwell. During driver load, init_clock_gating happens after device_info_init_mmio read the vdbox disable fuse register

[Intel-gfx] [PATCH v2 09/40] drm/i915/bdw+: Enable PSR in any eDP port

From: José Roberto de Souza From BDW+ the PSR registers moved from DDIA to transcoder, so any port with a eDP panel connected can have PSR, so lets remove this limitation. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- driver

[Intel-gfx] [PATCH v2 20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds

Add empty workaround hooks for Tiger Lake. The workarounds will be added on separate patches. We were already applying WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update the comment. Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi Reviewed-by: Radhakrishna Sripada

[Intel-gfx] [PATCH v2 27/40] drm/i915/tgl: add Gen12 default indirect ctx offset

From: Daniele Ceraolo Spurio Gen12 uses a new indirect ctx offset. Bspec: 11740 Cc: Joonas Lahtinen Cc: Radhakrishna Sripada Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 drivers/gpu/d

[Intel-gfx] [PATCH v2 35/40] drm/i915/tgl: Add perf support on TGL

From: Lionel Landwerlin The design of the OA unit has been split into several units. We now have a global unit (OAG) and a render specific unit (OAR). This leads to some changes on how we program things. Some details : OAR: - has its own set of counter registers, they are per-context saved

[Intel-gfx] [PATCH v2 28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID

From: Daniele Ceraolo Spurio Like Gen11, Gen12 has 11 available bits for the ctx id field. However, the last value (0x7FF) is reserved to indicate engine idle, so we need to reduce the maximum number of contexts by 1 compared to Gen11. Cc: Chris Wilson Signed-off-by: Daniele Ceraolo Spurio Sig

[Intel-gfx] [PATCH v2 25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence

From: José Roberto de Souza On TGL some registers moved from DDI to transcoder and the DisplayPort training sequence has a separate BSpec page. I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but it was becoming really hard to follow, so a new and cleaner function for TGL was ad

[Intel-gfx] [PATCH v2 40/40] drm/i915/tgl: Gen-12 media compression

From: Dhinakaran Pandiyan Gen-12 display can decompress surfaces compressed by the media engine. Detect the modifier corresponding to media compression to enable decompression for YUV and ARGB packed formats. A new modifier is added so that the driver can distinguish between media and render comp

[Intel-gfx] [PATCH v2 34/40] drm/i915/perf: add a parameter to control the size of OA buffer

From: Lionel Landwerlin The way our hardware is designed doesn't seem to let us use the MI_RECORD_PERF_COUNT command without setting up a circular buffer. In the case where the user didn't request OA reports to be available through the i915 perf stream, we can set the OA buffer to the minimum si

[Intel-gfx] [PATCH v2 30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability

From: Michel Thierry In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC (Scaler & Format Converter) unit. This is not the case in Tigerlake, where each VDBox can access a SFC. We will use this information to decide when the SFC units need to be reset and also pass it to the Gu

[Intel-gfx] [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12

From: Michel Thierry Gen12 has subtle changes in the reg state context offsets (some fields are gone, some are in a different location), compared to previous Gens. The simplest approach seems to be keeping Gen12 (and future platform) changes apart from the previous gens, while keeping the regist

[Intel-gfx] [PATCH v2 39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression

From: Dhinakaran Pandiyan Gen-12 display can decompress surfaces compressed by the media engine, add a new modifier as the driver needs to know the surface was compressed by the media or render engine. Cc: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Lucas De Marchi --- in

[Intel-gfx] [PATCH v2 26/40] HACK: drm/i915/tgl: Gen12 render context size

From: Daniele Ceraolo Spurio Re-use Gen11 context size for now. [ Lucas: add HACK since this is a temporary patch that needs to be confirmed: we need to check BSpec 46255 and recompute ] Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_

[Intel-gfx] [PATCH v2 36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support

From: Dhinakaran Pandiyan Yf tiling was removed in gen-12, make the necessary to changes to not expose the modifier to user space. Gen-12 display also is incompatible with pre-gen12 Y-tiled compression, so do not expose I915_FORMAT_MOD_Y_TILED_CCS. Bspec: 29650 Cc: Daniel Vetter Cc: Ville Syrj

[Intel-gfx] [PATCH v2 31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

From: Michel Thierry GAM registers located in the 0x4xxx range have been relocated to 0xCxxx; this is to make space for global MOCS registers. HSD: 399379 Cc: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |

[Intel-gfx] [PATCH v2 32/40] drm/i915/tgl: Updated Private PAT programming

From: Michel Thierry Gen12 removes the target-cache and age fields from the private PAT because MOCS now have the capability to set these itself. Only memory-type field should be programmed in the ppat, the reminded bits are reserved. Since now there are only 4 possible combinations, we could se

[Intel-gfx] [PATCH v2 33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl

From: Michel Thierry Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA will use the correct one. Cc: Lionel Landwerlin Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- drivers/gpu/

[Intel-gfx] [PATCH v2 38/40] drm/i915/tgl: Gen-12 render decompression

From: Dhinakaran Pandiyan Gen-12 decompression is supported with Y-tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Gen-12 display decompression is incompatible with buffers compressed by earlier GPUs, so make use of a new modif

[Intel-gfx] [PATCH v2 37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression

From: Dhinakaran Pandiyan Gen-12 has a new compression format, add a new modifier for userspace to indicate that. Cc: Ville Syrjälä Cc: Daniel Vetter Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Lucas De Marchi --- include/uapi/drm/drm_fourcc.h | 10 ++ 1 file changed, 10 inser

[Intel-gfx] [PATCH v2 29/40] drm/i915/tgl: Gen12 csb support

From: Daniele Ceraolo Spurio The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the c

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev2)

== Series Details == Series: Tiger Lake batch 3 (rev2) URL : https://patchwork.freedesktop.org/series/65290/ State : warning == Summary == $ dim checkpatch origin/drm-tip bfd5dba4649b drm/i915/tgl: disable DDIC 90d92ce242b9 drm/i915/tgl: add support for reading the timestamp frequency bc672332

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3 (rev2)

== Series Details == Series: Tiger Lake batch 3 (rev2) URL : https://patchwork.freedesktop.org/series/65290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: disable DDIC Okay! Commit: drm/i915/tgl: add support for reading the timestamp fr

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/gt: Mark context->active_count as protected by timeline->mutex

== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Mark context->active_count as protected by timeline->mutex URL : https://patchwork.freedesktop.org/series/65307/ State : success == Summary == CI Bug Log - changes from CI_DRM_6719_full -> Patchwork_14056_full ===

[Intel-gfx] ✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev2)

== Series Details == Series: Tiger Lake batch 3 (rev2) URL : https://patchwork.freedesktop.org/series/65290/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6725 -> Patchwork_14069 Summary --- **FAILURE** Serious un

[Intel-gfx] [PATCH] dma-buf: Shrink size of struct dma_fence

Rearrange the couple of 32-bit atomics hidden amongst the field of pointers that unnecessarily caused the compiler to insert some padding, shrinks the size of the base struct dma_fence from 80 to 72 bytes on x86-64. Signed-off-by: Chris Wilson Cc: Christian König --- include/linux/dma-fence.h |

Re: [Intel-gfx] [PATCH] dma-buf: Shrink size of struct dma_fence

Am 17.08.19 um 13:39 schrieb Chris Wilson: > Rearrange the couple of 32-bit atomics hidden amongst the field of > pointers that unnecessarily caused the compiler to insert some padding, > shrinks the size of the base struct dma_fence from 80 to 72 bytes on > x86-64. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] dma-buf: Shrink size of struct dma_fence

Quoting Koenig, Christian (2019-08-17 12:42:48) > Am 17.08.19 um 13:39 schrieb Chris Wilson: > > Rearrange the couple of 32-bit atomics hidden amongst the field of > > pointers that unnecessarily caused the compiler to insert some padding, > > shrinks the size of the base struct dma_fence from 80 t

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: Shrink size of struct dma_fence

== Series Details == Series: dma-buf: Shrink size of struct dma_fence URL : https://patchwork.freedesktop.org/series/65345/ State : warning == Summary == $ dim checkpatch origin/drm-tip 41eeb5f1a8bc dma-buf: Shrink size of struct dma_fence -:27: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definit

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Lift process_csb() out of the irq-off spinlock

== Series Details == Series: drm/i915/execlists: Lift process_csb() out of the irq-off spinlock URL : https://patchwork.freedesktop.org/series/65321/ State : success == Summary == CI Bug Log - changes from CI_DRM_6720_full -> Patchwork_14058_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: Shrink size of struct dma_fence

== Series Details == Series: dma-buf: Shrink size of struct dma_fence URL : https://patchwork.freedesktop.org/series/65345/ State : success == Summary == CI Bug Log - changes from CI_DRM_6725 -> Patchwork_14070 Summary --- **SUCCESS*

[Intel-gfx] [PATCH 0/3] Don't fail on uc init step

Michal Wajdeczko (3): drm/i915/uc: Cleanup fw fetch only if it was successful drm/i915/uc: Cleanup fw fetch on every GuC/HuC init failure drm/i915/uc: Never fail on uc preparation step drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 drivers/gpu/drm/i915/gt/uc/intel_huc.c | 9 +++

[Intel-gfx] [PATCH 2/3] drm/i915/uc: Cleanup fw fetch on every GuC/HuC init failure

Be consistent and always perform fw fetch cleanup in GuC/HuC specific init functions on every failure. Also while converting firmware status to error, stop treating SELECTED as non-error, as long term we should not see it. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wils

[Intel-gfx] [PATCH 3/3] drm/i915/uc: Never fail on uC preparation step

Let's wait with decision about importance of uC failure to hardware initialization step. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 +++ drivers/gpu/drm/i915/gt/uc/intel_huc.c | 3 +++ drivers/gpu/drm/i915/gt/uc/

[Intel-gfx] [PATCH 1/3] drm/i915/uc: Cleanup fw fetch only if it was successful

We can rely on firmware status AVAILABLE to determine if any firmware cleanup is required. Also don't unconditionally reset fw status to SELECTED as we will loose MISSING/ERROR codes. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson --- drivers/gpu/drm/i915/gt/uc/int

Re: [Intel-gfx] [PATCH 1/3] drm/i915/uc: Cleanup fw fetch only if it was successful

Quoting Michal Wajdeczko (2019-08-17 14:11:42) > We can rely on firmware status AVAILABLE to determine if any > firmware cleanup is required. Also don't unconditionally reset > fw status to SELECTED as we will loose MISSING/ERROR codes. > > Signed-off-by: Michal Wajdeczko > Cc: Daniele Ceraolo Sp

Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Cleanup fw fetch on every GuC/HuC init failure

Quoting Michal Wajdeczko (2019-08-17 14:11:43) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index 449c432dd768..d8e9be1d7b0e 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -305,16 +305,10 @

Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Never fail on uC preparation step

Quoting Michal Wajdeczko (2019-08-17 14:11:44) > Let's wait with decision about importance of uC failure to > hardware initialization step. i.e. wait until we are committed to using it before abandoning all hope. > Signed-off-by: Michal Wajdeczko > Cc: Daniele Ceraolo Spurio > Cc: Chris Wilson

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check the context size (rev3)

== Series Details == Series: drm/i915/selftests: Check the context size (rev3) URL : https://patchwork.freedesktop.org/series/65323/ State : success == Summary == CI Bug Log - changes from CI_DRM_6721_full -> Patchwork_14062_full Summary --

[Intel-gfx] ✓ Fi.CI.BAT: success for Don't fail on uc init step

== Series Details == Series: Don't fail on uc init step URL : https://patchwork.freedesktop.org/series/65351/ State : success == Summary == CI Bug Log - changes from CI_DRM_6725 -> Patchwork_14071 Summary --- **SUCCESS** No regres

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always wrap the ring offset before resetting

== Series Details == Series: drm/i915: Always wrap the ring offset before resetting URL : https://patchwork.freedesktop.org/series/65329/ State : success == Summary == CI Bug Log - changes from CI_DRM_6721_full -> Patchwork_14063_full Summa

[Intel-gfx] [PATCH 1/6] dma-buf: Introduce selftesting framework

In light of recent review slip ups, the absence of a suite of tests for dma-buf became apparent. Given the current plethora of testing frameworks, opt for one already in use by Intel's CI and so allow easy hook up into igt. We introduce a new module that when loaded will execute the list of selfte

[Intel-gfx] [PATCH 5/6] dma-fence: Simply wrap dma_fence_signal_locked with dma_fence_signal

Currently dma_fence_signal() tries to avoid the spinlock and only takes it if absolutely required to walk the callback list. However, to allow for some users to surreptitiously insert lazy signal callbacks that do not depend on enabling the signaling mechanism around every fence, we always need to

[Intel-gfx] [PATCH 3/6] dma-fence: Shrink size of struct dma_fence

Rearrange the couple of 32-bit atomics hidden amongst the field of pointers that unnecessarily caused the compiler to insert some padding, shrinks the size of the base struct dma_fence from 80 to 72 bytes on x86-64. Signed-off-by: Chris Wilson Cc: Christian König Reviewed-by: Christian König --

[Intel-gfx] [PATCH 2/6] dma-buf: Add selftests for dma-fence

Exercise the dma-fence API exported to drivers. Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/dma-buf/Makefile | 5 +- drivers/dma-buf/selftests.h| 1 + drivers/dma-buf/st-dma-fence.c | 571 + 3 files changed, 576 insertions(+), 1 deleti

[Intel-gfx] [PATCH 6/6] dma-fence: Store the timestamp in the same union as the cb_list

The timestamp and the cb_list are mutually exclusive, the cb_list can only be added to prior to being signaled (and once signaled we drain), while the timestamp is only valid upon being signaled. Both the timestamp and the cb_list are only valid while the fence is alive, and as soon as no reference

[Intel-gfx] [PATCH 4/6] dma-fence: Avoid list_del during fence->cb_list iteration

Before we notify the fence signal callback, we remove the cb from the list. However, since we are processing the entire list from underneath the spinlock, we do not need to individual delete each element, but can simply reset the link and the entire list. Signed-off-by: Chris Wilson Cc: Daniel Ve

Re: [Intel-gfx] [PATCH 5/6] dma-fence: Simply wrap dma_fence_signal_locked with dma_fence_signal

Am 17.08.19 um 16:47 schrieb Chris Wilson: > Currently dma_fence_signal() tries to avoid the spinlock and only takes > it if absolutely required to walk the callback list. However, to allow > for some users to surreptitiously insert lazy signal callbacks that > do not depend on enabling the signali

Re: [Intel-gfx] [PATCH 6/6] dma-fence: Store the timestamp in the same union as the cb_list

Am 17.08.19 um 16:47 schrieb Chris Wilson: > The timestamp and the cb_list are mutually exclusive, the cb_list can > only be added to prior to being signaled (and once signaled we drain), > while the timestamp is only valid upon being signaled. Both the > timestamp and the cb_list are only valid wh

[Intel-gfx] [PATCH v3] dma-fence: Simply wrap dma_fence_signal_locked with dma_fence_signal

Currently dma_fence_signal() tries to avoid the spinlock and only takes it if absolutely required to walk the callback list. However, to allow for some users to surreptitiously insert lazy signal callbacks that do not depend on enabling the signaling mechanism around every fence, we always need to

Re: [Intel-gfx] [PATCH 6/6] dma-fence: Store the timestamp in the same union as the cb_list

Quoting Koenig, Christian (2019-08-17 16:20:12) > Am 17.08.19 um 16:47 schrieb Chris Wilson: > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > > index 89d96e3e6df6..2c21115b1a37 100644 > > --- a/drivers/dma-buf/dma-fence.c > > +++ b/drivers/dma-buf/dma-fence.c > > @@ -129

Re: [Intel-gfx] [PATCH v3] dma-fence: Simply wrap dma_fence_signal_locked with dma_fence_signal

Am 17.08.19 um 17:23 schrieb Chris Wilson: > Currently dma_fence_signal() tries to avoid the spinlock and only takes > it if absolutely required to walk the callback list. However, to allow > for some users to surreptitiously insert lazy signal callbacks that > do not depend on enabling the signali

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] dma-buf: Introduce selftesting framework (rev2)

== Series Details == Series: series starting with [1/6] dma-buf: Introduce selftesting framework (rev2) URL : https://patchwork.freedesktop.org/series/65353/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68147e4f876c dma-buf: Introduce selftesting framework -:27: WARNING:CONFI

[Intel-gfx] [PATCH v2] dma-fence: Store the timestamp in the same union as the cb_list

The timestamp and the cb_list are mutually exclusive, the cb_list can only be added to prior to being signaled (and once signaled we drain), while the timestamp is only valid upon being signaled. Both the timestamp and the cb_list are only valid while the fence is alive, and as soon as no reference

Re: [Intel-gfx] [PATCH 6/6] dma-fence: Store the timestamp in the same union as the cb_list

Am 17.08.19 um 17:27 schrieb Chris Wilson: > Quoting Koenig, Christian (2019-08-17 16:20:12) >> Am 17.08.19 um 16:47 schrieb Chris Wilson: >>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>> index 89d96e3e6df6..2c21115b1a37 100644 >>> --- a/drivers/dma-buf/dma-fence.c >>>

Re: [Intel-gfx] [PATCH v2] dma-fence: Store the timestamp in the same union as the cb_list

Am 17.08.19 um 17:30 schrieb Chris Wilson: > The timestamp and the cb_list are mutually exclusive, the cb_list can > only be added to prior to being signaled (and once signaled we drain), > while the timestamp is only valid upon being signaled. Both the > timestamp and the cb_list are only valid wh

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] dma-buf: Introduce selftesting framework (rev2)

== Series Details == Series: series starting with [1/6] dma-buf: Introduce selftesting framework (rev2) URL : https://patchwork.freedesktop.org/series/65353/ State : success == Summary == CI Bug Log - changes from CI_DRM_6727 -> Patchwork_14072

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] dma-buf: Introduce selftesting framework (rev3)

== Series Details == Series: series starting with [1/6] dma-buf: Introduce selftesting framework (rev3) URL : https://patchwork.freedesktop.org/series/65353/ State : warning == Summary == $ dim checkpatch origin/drm-tip e16973981faa dma-buf: Introduce selftesting framework -:27: WARNING:CONFI

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/connector: Allow max possible encoders to attach to a connector (rev2)

== Series Details == Series: drm/connector: Allow max possible encoders to attach to a connector (rev2) URL : https://patchwork.freedesktop.org/series/62743/ State : success == Summary == CI Bug Log - changes from CI_DRM_6721_full -> Patchwork_14064_full ==

Re: [Intel-gfx] [PATCH 3/5] mm, notifier: Catch sleeping/blocking for !blockable

On Sat, Aug 17, 2019 at 5:26 PM Jason Gunthorpe wrote: > > On Thu, Aug 15, 2019 at 09:02:49AM +0200, Daniel Vetter wrote: > > On Wed, Aug 14, 2019 at 09:00:29PM -0300, Jason Gunthorpe wrote: > > > On Wed, Aug 14, 2019 at 10:20:25PM +0200, Daniel Vetter wrote: > > > > We need to make sure implement

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] dma-buf: Introduce selftesting framework (rev3)

== Series Details == Series: series starting with [1/6] dma-buf: Introduce selftesting framework (rev3) URL : https://patchwork.freedesktop.org/series/65353/ State : success == Summary == CI Bug Log - changes from CI_DRM_6727 -> Patchwork_14073

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/uc: Add explicit DISABLED state for firmware (rev4)

== Series Details == Series: drm/i915/uc: Add explicit DISABLED state for firmware (rev4) URL : https://patchwork.freedesktop.org/series/65278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6722_full -> Patchwork_14065_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen11: Allow usage of all GPIO pins (rev4)

== Series Details == Series: drm/i915/gen11: Allow usage of all GPIO pins (rev4) URL : https://patchwork.freedesktop.org/series/65261/ State : success == Summary == CI Bug Log - changes from CI_DRM_6723_full -> Patchwork_14067_full Summary

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check the context size (rev4)

== Series Details == Series: drm/i915/selftests: Check the context size (rev4) URL : https://patchwork.freedesktop.org/series/65323/ State : success == Summary == CI Bug Log - changes from CI_DRM_6724_full -> Patchwork_14068_full Summary --

[Intel-gfx] [CI] drm/i915: Propagate fence errors

Errors spread like wildfire, and must eventually be returned to the user. They need to be captured and passed along the flow of fences, infecting each in turn with the existing error, until finally they fall out of a user visible result. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Propagate fence errors

== Series Details == Series: drm/i915: Propagate fence errors URL : https://patchwork.freedesktop.org/series/65365/ State : success == Summary == CI Bug Log - changes from CI_DRM_6728 -> Patchwork_14074 Summary --- **SUCCESS** No

[Intel-gfx] ✓ Fi.CI.IGT: success for dma-buf: Shrink size of struct dma_fence

== Series Details == Series: dma-buf: Shrink size of struct dma_fence URL : https://patchwork.freedesktop.org/series/65345/ State : success == Summary == CI Bug Log - changes from CI_DRM_6725_full -> Patchwork_14070_full Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for Don't fail on uc init step

== Series Details == Series: Don't fail on uc init step URL : https://patchwork.freedesktop.org/series/65351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6725_full -> Patchwork_14071_full Summary --- **FAILURE**