> -Original Message-
> From: Karas, Anna
> Sent: Thursday, September 26, 2019 6:06 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kulkarni, Vandita
> Subject: [PATCH] drm/i915/tgl: Fix doc not corresponding to code
>
> Replace PLLs names used in documentation to that used in the code.
>
On Fri, Sep 20, 2019 at 01:42:26PM +0200, Maarten Lankhorst wrote:
> We want to program slave planes with the master plane_state for
> properties such as FB, rotation, coordinates, etc, but the
> slave plane_state for all programming parameters.
>
> Instead of special casing NV12 Y-planes, we
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev3)
URL : https://patchwork.freedesktop.org/series/67195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963_full -> Patchwork_14547_full
On Fri, Sep 20, 2019 at 01:42:25PM +0200, Maarten Lankhorst wrote:
> Unfortunately I have no way to test this, but it should be correct
> if the bios sets up bigjoiner in a sane way.
>
> Skip iterating over bigjoiner slaves, only the master has the state we
> care about.
>
> Add the width of the
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev3)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966 ->
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
On Wed, Sep 25, 2019 at 10:18:19PM -0700, Matt Roper wrote:
> On Fri, Sep 20, 2019 at 01:42:24PM +0200, Maarten Lankhorst wrote:
> > Make vdsc work when no output is enabled. The big joiner needs VDSC
> > on the slave, so enable it and set the appropriate bits.
> > Also update timestamping
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
URL : https://patchwork.freedesktop.org/series/67312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966 -> Patchwork_14561
Quoting Chris Wilson (2019-09-26 15:25:38)
> Moving our primary irq handler to a RT thread incurs an extra 1us delay
> in process interrupts. This is most notice in waking up client threads,
> where it adds about 20% of extra latency. It also imposes a delay in
> feeding the GPU, an extra 1us
== Series Details ==
Series: series starting with [v11,1/2] drm/i915: Introduce async plane update
to i915
URL : https://patchwork.freedesktop.org/series/67254/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6961_full -> Patchwork_14546_full
From: Clinton A Taylor
BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
now taking in consideration the pin assignment and allowing us to
optimize power by shutting down available but not needed lanes.
It was tested on ICL and TGL, with adaptors that used pin assignment
C and
Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.
Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or
From: Clinton A Taylor
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the
From: Lucas De Marchi
Now that TC support was added, initialize DDIs.
Reviewed-by: José Roberto de Souza
Acked-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
1 file changed, 6
On Thu, 2019-09-26 at 18:34 +0300, Imre Deak wrote:
> On Wed, Sep 25, 2019 at 04:45:07PM -0700, José Roberto de Souza
> wrote:
> > From: Clinton A Taylor
> >
> > Added DKL Phy sequences and helpers functions to program voltage
> > swing, clock gating and dp mode.
> >
> > It is not written in DP
On Thu, Sep 26, 2019 at 10:35:16PM +0300, Souza, Jose wrote:
> On Thu, 2019-09-26 at 15:02 +0300, Imre Deak wrote:
> > On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza
> > wrote:
> > > From: Clinton A Taylor
> > >
> > > BSpec was updated(r146548) with a new MG_DP_MODE Programming
On Thu, 2019-09-26 at 15:02 +0300, Imre Deak wrote:
> On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza
> wrote:
> > From: Clinton A Taylor
> >
> > BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> > now taking in consideration the pin assignment and allowing us
Quoting Brian Welty (2019-09-26 19:57:17)
>
> On 9/26/2019 7:25 AM, Chris Wilson wrote:
> > Moving our primary irq handler to a RT thread incurs an extra 1us delay
> > in process interrupts. This is most notice in waking up client threads,
> > where it adds about 20% of extra latency. It also
On Thu, Sep 26, 2019 at 07:09:22PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2019 at 05:50:05PM +0200, Maarten Lankhorst wrote:
> > Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
> > > On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
> > >> Now that we can program planes from
== Series Details ==
Series: GuC engine reset support
URL : https://patchwork.freedesktop.org/series/67251/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14543_full
Summary
---
**SUCCESS**
On 9/26/2019 7:25 AM, Chris Wilson wrote:
> Moving our primary irq handler to a RT thread incurs an extra 1us delay
> in process interrupts. This is most notice in waking up client threads,
> where it adds about 20% of extra latency. It also imposes a delay in
> feeding the GPU, an extra 1us
Quoting Chris Wilson (2019-09-26 11:24:35)
> Quoting Michał Winiarski (2019-09-26 11:06:34)
> > We're currently doing one workaround where we're using scratch as a
> > temporary storage place, while we're overwriting the value of one
> > register with some known constant value in order to perform
Verify that the values we store in our nonpriv context image registers
are restored after a switch.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
---
tests/i915/gem_ctx_isolation.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/tests/i915/gem_ctx_isolation.c
== Series Details ==
Series: drm/i915/huc: fix version parsing from CSS header
URL : https://patchwork.freedesktop.org/series/67248/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14541_full
Summary
On Thu, Sep 26, 2019 at 03:28:44PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 11:37:58AM -0700, Manasi Navare wrote:
> > On Wed, Sep 25, 2019 at 01:08:23PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 24, 2019 at 10:59:57AM -0700, Manasi Navare wrote:
> > > > On Tue, Sep 24, 2019 at
Quoting Sebastian Andrzej Siewior (2019-09-26 11:56:43)
> The function intel_engine_breadcrumbs_irq() is always invoked from an
> interrupt
> handler and for that reason it invokes (as an optimisation) only spin_lock()
> for locking assuming that the interrupts are already disabled. The
>
On Wed, Sep 25, 2019 at 08:40:19PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Small joiner RAM buffer size is platform-specific
> URL : https://patchwork.freedesktop.org/series/67195/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6952_full
== Series Details ==
Series: drm/i915: Add feature flag for platforms with DRAM
URL : https://patchwork.freedesktop.org/series/67244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14540_full
Summary
Quoting Sebastian Andrzej Siewior (2019-09-26 11:56:44)
> The lockdep_assert_irqs_disabled() check is needless. The previous
> lockdep_assert_held() check ensures that the lock is acquired and while
> the lock is acquired lockdep also prints a warning if the interrupts are
> not disabled if they
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Delegate our irq handler to a
thread
URL : https://patchwork.freedesktop.org/series/67299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14560
On Thu, Sep 26, 2019 at 10:26:08AM -0600, Alex Williamson wrote:
> On Thu, 26 Sep 2019 11:46:55 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Sep 25, 2019 at 10:30:28AM -0600, Alex Williamson wrote:
> > > On Wed, 25 Sep 2019 10:11:00 -0400
> > > Rob Miller wrote:
> > > > > > On Tue, 24
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Delegate our irq handler to a
thread
URL : https://patchwork.freedesktop.org/series/67299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
764ea7b0a0bd drm/i915: Delegate our irq handler to a thread
== Series Details ==
Series: DC3CO Support for TGL (rev12)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14559
Summary
---
**SUCCESS**
No
On Thu, Sep 26, 2019 at 06:13:53PM +0200, Maarten Lankhorst wrote:
> Op 26-09-2019 om 18:09 schreef Ville Syrjälä:
> > On Thu, Sep 26, 2019 at 05:50:05PM +0200, Maarten Lankhorst wrote:
> >> Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
> >>> On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten
On Thu, 26 Sep 2019 11:46:55 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Sep 25, 2019 at 10:30:28AM -0600, Alex Williamson wrote:
> > On Wed, 25 Sep 2019 10:11:00 -0400
> > Rob Miller wrote:
> > > > > On Tue, 24 Sep 2019 21:53:29 +0800
> > > > > Jason Wang wrote:
> > > > > > diff --git
On Thu, Sep 26, 2019 at 11:47:25AM +0200, Maarten Lankhorst wrote:
> This can all be done from the intel_update_crtc function. Split out the
> pipe update into a separate function, just like is done for the planes.
> Pull in all the changes done during fastset as well. It makes no sense
> for it
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL : https://patchwork.freedesktop.org/series/67240/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14539_full
Op 26-09-2019 om 18:09 schreef Ville Syrjälä:
> On Thu, Sep 26, 2019 at 05:50:05PM +0200, Maarten Lankhorst wrote:
>> Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
>>> On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
Now that we can program planes from the update_slave
On 2019-09-26 16:40:34 [+0100], Chris Wilson wrote:
>
> It's all edge interrupts -- although for gen2/3 my memory is hazy. But
> the GPU (circa gen6) can generate more than enough interrupts to saturate
> a CPU.
:)
> -Chris
Sebastian
___
Intel-gfx
On Thu, Sep 26, 2019 at 05:50:05PM +0200, Maarten Lankhorst wrote:
> Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
> > On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
> >> Now that we can program planes from the update_slave callback, and
> >> we have done all fb pinning
== Series Details ==
Series: DC3CO Support for TGL (rev12)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48714a15864a drm/i915/tgl: Add DC3CO required register and bits
305bf875caba drm/i915/tgl: Add DC3CO mask to
Op 26-09-2019 om 00:09 schreef Manasi Navare:
> On Tue, Sep 24, 2019 at 10:30:39PM -0700, Matt Roper wrote:
>> On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
>>> Small changes to intel_dp_mode_valid(), allow listing modes that
>>> can only be supported in the bigjoiner
== Series Details ==
Series: drm/i915: Update references to previously renamed files
URL : https://patchwork.freedesktop.org/series/67295/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14558
Summary
Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
> On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
>> Now that we can program planes from the update_slave callback, and
>> we have done all fb pinning correctly, it's time to program those
>> planes as well.
>>
>> We use the
On Wed, Sep 25, 2019 at 10:30:28AM -0600, Alex Williamson wrote:
> On Wed, 25 Sep 2019 10:11:00 -0400
> Rob Miller wrote:
> > > > On Tue, 24 Sep 2019 21:53:29 +0800
> > > > Jason Wang wrote:
> > > > > diff --git a/drivers/vfio/mdev/vfio_mdev.c
> > > > b/drivers/vfio/mdev/vfio_mdev.c
> > > >
Quoting Chris Wilson (2019-09-26 16:40:34)
> Quoting Sebastian Andrzej Siewior (2019-09-26 16:32:52)
> > On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > index
Quoting Sebastian Andrzej Siewior (2019-09-26 16:32:52)
> On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index bc83f094065a..f3df7714a3f3 100644
> > > > ---
From: Sebastian Andrzej Siewior
The function intel_engine_breadcrumbs_irq() is always invoked from an interrupt
handler and for that reason it invokes (as an optimisation) only spin_lock()
for locking assuming that the interrupts are already disabled. The
function
From: Sebastian Andrzej Siewior
The lockdep_assert_irqs_disabled() check is needless. The previous
lockdep_assert_held() check ensures that the lock is acquired and while
the lock is acquired lockdep also prints a warning if the interrupts are
not disabled if they have to be.
These IRQ-off
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before signaling secondary engines and
extra latency in
On Wed, Sep 25, 2019 at 04:45:07PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor
>
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
>
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that
On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index bc83f094065a..f3df7714a3f3 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -4491,8
== Series Details ==
Series: drm/i915: Delegate our irq handler to a thread
URL : https://patchwork.freedesktop.org/series/67294/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14557
Summary
---
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full
Quoting Sebastian Andrzej Siewior (2019-09-26 16:13:08)
> On 2019-09-26 15:25:38 [+0100], Chris Wilson wrote:
> > Moving our primary irq handler to a RT thread incurs an extra 1us delay
> > in process interrupts. This is most notice in waking up client threads,
> > where it adds about 20% of extra
On 2019-09-26 15:57:07 [+0100], Tvrtko Ursulin wrote:
> 2. What about our tasklets - with threaded irqs we don't need them any more,
> right? So in this case they just add additional latency.
If you enqueue / schedule tasklets from your threaded handler then this
will wake up ksoftirqd and
On 2019-09-26 15:25:38 [+0100], Chris Wilson wrote:
> Moving our primary irq handler to a RT thread incurs an extra 1us delay
> in process interrupts. This is most notice in waking up client threads,
> where it adds about 20% of extra latency. It also imposes a delay in
> feeding the GPU, an extra
Quoting Tvrtko Ursulin (2019-09-26 15:57:07)
>
> On 26/09/2019 15:25, Chris Wilson wrote:
> > Moving our primary irq handler to a RT thread incurs an extra 1us delay
> > in process interrupts. This is most notice in waking up client threads,
> > where it adds about 20% of extra latency. It also
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset
Resending V9 series after fixing CI warnings and CI IGT failures.
v9 revision is a rework of series, which has fixed the review comments
provided by Imre and added Animesh's RB on following two patches.
1.Add DC3CO required register and bits
2.Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of
Disallow DC3CO state before PSR2 exit.
Store dc3co_exitline from crtc state to psr dev_priv
structure to use it easily whenever it requires.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
v2: Moved tgl_psr2_deep_sleep_enable/disable function to
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc:
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Define explicit wedged on init
reset state
URL : https://patchwork.freedesktop.org/series/67289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14556
On Thu, 2019-09-26 at 15:36 +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 02:07:27PM -0700, Stuart Summers wrote:
>
> No commit message.
I'll add one here, should have caught this before posting, sorry.
>
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/i915_drv.c
On 26/09/2019 15:25, Chris Wilson wrote:
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before
== Series Details ==
Series: drm/i915/selftests: Exercise concurrent submission to all engines
URL : https://patchwork.freedesktop.org/series/67237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14537_full
Update references to reservation.c and reservation.h since these files
have been renamed to dma-resv.c and dma-resv.h respectively.
Cc: Christian König
Link: https://patchwork.freedesktop.org/patch/323401/?series=65037=1
Signed-off-by: Anna Karas
---
Documentation/driver-api/dma-buf.rst | 6
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before signaling secondary engines and
extra latency in
== Series Details ==
Series: drm/i915/tgl: Fix doc not corresponding to code (rev2)
URL : https://patchwork.freedesktop.org/series/67088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14555
Summary
On 25/09/2019 11:01, Chris Wilson wrote:
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 155
From: Michał Winiarski
Some of our commands (MI_FLUSH_DW / PIPE_CONTROL) require a post-sync write
operation to be performed. Currently we're using dedicated VMA for
PIPE_CONTROL and global HWSP for MI_FLUSH_DW.
On execlists platforms, each of our contexts has an area that can be
used as scratch
From: Michał Winiarski
Default length value of MI_LOAD_REGISTER_REG is 1.
Also move it out of cmd-parser-only registers since we're going to use
it in i915.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Jani Nikula
Reviewed-by: Chris Wilson
---
Quoting Michał Winiarski (2019-09-26 11:06:34)
> We're currently doing one workaround where we're using scratch as a
> temporary storage place, while we're overwriting the value of one
> register with some known constant value in order to perform a
> workaround.
> While we could just do similar
From: Michał Winiarski
We're currently using scratch presence as a way of identifying that we
entered wedged state at driver initialization time.
Let's use a separate flag rather than rely on scratch.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Chris
Quoting Michał Winiarski (2019-09-26 13:20:19)
> We're no longer using it on execlists platforms. There's no point in
> allocating it.
>
> v2: Move scratch init to legacy ring submission backend. (Chris)
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
-Chris
Quoting Michał Winiarski (2019-09-26 11:06:33)
> We can use it in i915 for updating parts of unmasked registers from
> within a batch. We're also adding Gen8+ versions of CS_GPR registers
> (aka MI_MATH_REG in the coprocessor).
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
Checked
On 26/09/2019 15:21, Anna Karas wrote:
Insert structure members names into their descriptions to follow
kernel-doc format.
Cc: Chris Wilson
Signed-off-by: Anna Karas
Still
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++---
1 file changed, 7
== Series Details ==
Series: drm/i915/perf: Fix use of kernel-doc format in structure members
URL : https://patchwork.freedesktop.org/series/67282/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14554
Hi Chris,
On Thu, Sep 26, 2019 at 02:10:06PM +0100, Chris Wilson wrote:
> Make it easier to discern in the noise of the module reload where each
> begins.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
thanks for this patch!
Acked-by: Andi Shyti
Andi
> ---
> tests/i915/i915_pm_rpm.c |
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state (rev2)
URL : https://patchwork.freedesktop.org/series/67276/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14553
Make it easier to discern in the noise of the module reload where each
begins.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
tests/i915/i915_pm_rpm.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index a2bdabee2..f5f813c3d 100644
On Wed, Sep 25, 2019 at 04:45:08PM -0700, José Roberto de Souza wrote:
> Link training is failling when running link at 2.7GHz and 1.62GHz and
> following BSpec pll algorithm.
>
> Comparing the values calculated and the ones from the reference table
> it looks like
On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
> Now that we can program planes from the update_slave callback, and
> we have done all fb pinning correctly, it's time to program those
> planes as well.
>
> We use the update_slave callback as it allows us to use the
> separate
On Wed, Sep 25, 2019 at 4:52 AM Tian, Kevin wrote:
> > From: Alex Williamson
> > Sent: Wednesday, September 25, 2019 7:07 AM
> >
> > On Tue, 24 Sep 2019 21:53:29 +0800
> > Jason Wang wrote:
> >
> > > Currently, except for the create and remove, the rest of
> > > mdev_parent_ops is designed for
On Wed, Sep 25, 2019 at 02:42:12PM -0700, Matt Roper wrote:
> On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
> > This can all be done from the intel_update_crtc function. Split out the
> > pipe update into a separate function, just like is done for the planes.
> > Pull in all
Replace PLLs names used in documentation to that used in the code.
Cc: Vandita Kulkarni
Fixes: commit d0570414f3d1 ("drm/i915/tgl: Add new pll ids")
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On Wed, Sep 25, 2019 at 02:07:27PM -0700, Stuart Summers wrote:
No commit message.
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>
On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> active. Update intel_can_enable_sagv to allow this, and loop through all
> active planes on all active crtcs to check against the interlaced and
> latency
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state (rev2)
URL : https://patchwork.freedesktop.org/series/67276/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5883d760ee3b drm/i915: Define explicit wedged on init reset
On Wed, Sep 25, 2019 at 11:37:58AM -0700, Manasi Navare wrote:
> On Wed, Sep 25, 2019 at 01:08:23PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 24, 2019 at 10:59:57AM -0700, Manasi Navare wrote:
> > > On Tue, Sep 24, 2019 at 05:38:00PM +0200, Maarten Lankhorst wrote:
> > > > Op 22-09-2019 om 19:08
Insert structure members names into their descriptions to follow
kernel-doc format.
Cc: Chris Wilson
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
We're no longer using it on execlists platforms. There's no point in
allocating it.
v2: Move scratch init to legacy ring submission backend. (Chris)
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 --
drivers/gpu/drm/i915/gt/intel_gt.c
On Thu, Sep 26, 2019 at 06:48:54PM +0800, Jason Wang wrote:
>
> On 2019/9/26 下午4:21, Michael S. Tsirkin wrote:
> > On Thu, Sep 26, 2019 at 12:04:46PM +0800, Jason Wang wrote:
> > > > > > I'm not sure how stable above ops are.
> > > > > It's the kernel internal API, so there's no strict
== Series Details ==
Series: drm/i915: Don't skip debug messages when dp link config fails
URL : https://patchwork.freedesktop.org/series/67232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14535_full
On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor
>
> BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> now taking in consideration the pin assignment and allowing us to
> optimize power by shutting down available but not needed
== Series Details ==
Series: drm/i915: Acquire locks with interrupts disabled
URL : https://patchwork.freedesktop.org/series/67280/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14552
Summary
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