== Series Details ==
Series: drm/i915/execlists: Fix annotation for decoupling virtual request
URL : https://patchwork.freedesktop.org/series/67621/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14677_full
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14674_full
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio()
static
URL : https://patchwork.freedesktop.org/series/67600/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14671_full
=
== Series Details ==
Series: drm/i915: customize DPCD brightness control for specific panel
URL : https://patchwork.freedesktop.org/series/67595/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14670_full
===
On Fri, Oct 04, 2019 at 05:17:07PM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > > linear and has 4
On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > linear and has 4 bits of data for each main surface cache line pair, a
> > ratio of 1:256. Add
On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> Gen12 display can decompress surfaces compressed by render engine with Clear
> Color, add
> a new modifier as the driver needs to know the surface was compressed by
> render engine.
>
> V2: Description changes as suggested by Rafae
On Fri, 2019-10-04 at 18:36 +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driv
On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-spa
On Fri, 2019-10-04 at 13:27 -0700, Matt Roper wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driver
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Rev
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified ge
Quoting Matthew Auld (2019-10-04 18:04:33)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
Ok, while dma_addr_t can technically exceed resourc
On Fri, Oct 04, 2019 at 01:53:57PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> >In prep for newer platforms having more complicated ways to determine
> >the SAGV block time, move the variable to dev_priv, and extract the
> >setting to an initial s
On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
> >Starting from TGL, we now need to read the SAGV block time via a PCODE
> >mailbox, rather than having a static value.
> >
> >BSpec: 49326
> >
> >v2: Fix up pcode val d
== Series Details ==
Series: drm/i915/selftests: Appease lockdep
URL : https://patchwork.freedesktop.org/series/67622/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7012 -> Patchwork_14678
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/vga: rename
intel_vga_msr_write() to intel_vga_reset_io_mem()
URL : https://patchwork.freedesktop.org/series/67592/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7007_full -> Patchwork_14668_full
On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav
== Series Details ==
Series: drm/i915/selftests: Appease lockdep
URL : https://patchwork.freedesktop.org/series/67622/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4c82f2976a87 drm/i915/selftests: Appease lockdep
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit de
On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new g
On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
I agree
Disable irqs around updating the context image to keep lockdep happy:
<4>[ 673.483340] WARNING: possible irq lock inversion dependency detected
<4>[ 673.483342] 5.4.0-rc1-CI-Trybot_5118+ #1 Tainted: G U
<4>[ 673.483342]
<4>[ 673.4833
On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers
== Series Details ==
Series: drm/i915/execlists: Fix annotation for decoupling virtual request
URL : https://patchwork.freedesktop.org/series/67621/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14677
Summ
On Fri, Oct 04, 2019 at 01:56:08PM +0530, Swati Sharma wrote:
> Moved common code to check gamma_enable to specific funcs per platform
> in bit_precision func. icl doesn't support that and chv has separate
> enable knob for CGM LUT.
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/di
On Fri, Oct 04, 2019 at 01:56:07PM +0530, Swati Sharma wrote:
> Premature gamma lut prepration and loading which was getting
> reflected in first modeset causing different colors on
> screen during boot.
>
> Issue: In BIOS, gamma is disabled by default. However, legacy read_luts()
> was setting cr
== Series Details ==
Series: drm/i915/execlists: Fix annotation for decoupling virtual request
URL : https://patchwork.freedesktop.org/series/67621/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a0822b4ea301 drm/i915/execlists: Fix annotation for decoupling virtual request
-:16
== Series Details ==
Series: drm/i915/stolen: make the object creation interface consistent
URL : https://patchwork.freedesktop.org/series/67615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14676
Summary
As we may signal a request and take the engine->active.lock within the
signaler, the engine submission paths have to use a nested annotation on
their requests -- but we guarantee that we can never submit on the same
engine as the signaling fence.
<4>[ 723.763281] WARNING: possible circular lockin
On Fri, 04 Oct 2019, Adam Jackson wrote:
> On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
>> This panel (manufacturer is SDC, product ID is 0x4141)
>> used manufacturer defined DPCD register to control brightness
>> that not defined in eDP spec so far. This change follow panel
>> vendor's i
From: CQ Tang
Our other backends return an actual error value upon failure. Do the
same for stolen objects, which currently just return NULL on failure.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://p
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14674
Summary
---
**SUCCESS**
No regressions fo
== Series Details ==
Series: gpu: Fix Kconfig indentation (rev2)
URL : https://patchwork.freedesktop.org/series/67121/
State : failure
== Summary ==
Applying: gpu: Fix Kconfig indentation
error: sha1 information is lacking or useless
(drivers/gpu/drm/amd/display/Kconfig).
error: could not bui
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/stolen: make the object creation interface consistent
Okay!
Commit: drm/i915: introduce intel
== Series Details ==
Series: series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio()
static
URL : https://patchwork.freedesktop.org/series/67600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14671
===
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^/\t/' -i */Kconfig
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Fix also DRM_AMD_DC_HDCP (new arrival since v1).
---
drivers/gpu/drm/Kconfig
On Thu, Oct 03, 2019 at 06:45:56PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add Sphinx-compatible references to struct fields
> URL : https://patchwork.freedesktop.org/series/67550/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915: Add Sphinx-compatible re
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
230ce2751c83 drm/i915/stolen: make the object creation interface consistent
-:89: CHECK:COMPARISON_TO_NULL: Comparison to NULL cou
== Series Details ==
Series: Enable bigjoiner support, second approach. (rev2)
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
Applying: HAX to make DSC work on the icelake test system
Applying: drm/i915: Fix for_each_intel_plane_mask definition
Applying: dr
== Series Details ==
Series: drm/i915: Use helpers for drm_mm_node booleans
URL : https://patchwork.freedesktop.org/series/67602/
State : failure
== Summary ==
Applying: drm/i915: Use helpers for drm_mm_node booleans
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/g
On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, move the variable to dev_priv, and extract the
> setting to an initial setup function. While we're at it, update the if
> ladder to follow the
== Series Details ==
Series: drm/i915: customize DPCD brightness control for specific panel
URL : https://patchwork.freedesktop.org/series/67595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14670
Summary
Quoting Matthew Auld (2019-10-04 18:04:49)
> From: Michal Wajdeczko
>
> HWS placement restrictions can't just rely on HAS_LLC flag.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Auld
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
> 1 fi
== Series Details ==
Series: drm/i915: customize DPCD brightness control for specific panel
URL : https://patchwork.freedesktop.org/series/67595/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84d67190854b drm/i915: customize DPCD brightness control for specific panel
-:88: CHEC
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
dr
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 65 +++---
drivers/gpu/drm/i915/gem/i
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/driver
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
1 file changed, 5 in
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 74 ++-
drivers/gpu/drm/i915/i915_drv.h
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the apertu
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_intern
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 ++---
1 file changed, 20 insertions(
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support
basic LMEM object creation within the kernel. From there we can start with the
dumb buffer support, and then the other display related bits.
Quick respin with a bunch of minor tweaks + rebasing on the now merged
struct_mutex
Since we have no way access it from the CPU. For such cases just
fallback to internal objects.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
b/drivers/g
From: CQ Tang
Our other backends return an actual error value upon failure. Do the
same for stolen objects, which currently just return NULL on failure.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_displ
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_g
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drive
Some kernel internal objects may need to be allocated as a contiguous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtine
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangc
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 167 ++
1 file changed, 167 insertions(+)
diff --git a/drivers
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f27772f6779a..d4892769b73
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 inserti
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Skip redundant
resubmission (rev2)
URL : https://patchwork.freedesktop.org/series/67566/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14665_full
===
On 2019-10-04 at 18:48:08 +0300, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote:
> > Adding following definition to i915_reg.h
> > 1. DC_STATE_EN register DC3CO bit fields and masks.
> >DC3CO enable bit will be used by driver to make DC3CO
> >ready for
== Series Details ==
Series: TGL HAX drm/i915/tgl: Interrupts are overrated (rev7)
URL : https://patchwork.freedesktop.org/series/67558/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14664_full
Summar
On Fri, Oct 04, 2019 at 05:51:16PM +0200, Maarten Lankhorst wrote:
> Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
> >> We are still looking at drm_crtc_state in a few places, convert those
> >> to use intel_crtc_state instead.
Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
>> We are still looking at drm_crtc_state in a few places, convert those
>> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
>>
>> Signed-off-by: Maarten Lankhorst
On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote:
> Adding following definition to i915_reg.h
> 1. DC_STATE_EN register DC3CO bit fields and masks.
>DC3CO enable bit will be used by driver to make DC3CO
>ready for DMC f/w and status bit will be used as DC3CO
>entry status.
On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers
Chris Wilson writes:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and
== Series Details ==
Series: fix broken state checker and enable state checker for icl+
URL : https://patchwork.freedesktop.org/series/67586/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14663_full
S
On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
> This panel (manufacturer is SDC, product ID is 0x4141)
> used manufacturer defined DPCD register to control brightness
> that not defined in eDP spec so far. This change follow panel
> vendor's instruction to support brightness adjustment.
I'
There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.
v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
variety of huc readonly status
On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
> ---
>
== Series Details ==
Series: series starting with [01/20] drm/i915: Only track bound elements of the
GTT
URL : https://patchwork.freedesktop.org/series/67594/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7008 -> Patchwork_14669
===
On 04/10/2019 15:22, Chris Wilson wrote:
A subset of 71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
in order to prepare drm-intel-next-queued for subsequent patches before
we can backmerge 71724f708997 itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm
And only verify cursor allocation when cursor plane is active.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/i
A subset of 71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
in order to prepare drm-intel-next-queued for subsequent patches before
we can backmerge 71724f708997 itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
dr
From: Ville Syrjälä
drm_get_cea_aspect_ratio() is not used outside drm_edid.c.
Make it static.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 10 +-
include/drm/drm_edid.h | 1 -
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/g
From: Ville Syrjälä
Extract drm_mode_hdmi_vic() to correctly calculate the final HDMI
VIC for us. Currently this is being done a bit differently between
the AVI and HDMI infoframes. Let's get both to agree on this.
We need to allow the case where a mode is both 3D and has a HDMI
VIC. Currently w
From: Ville Syrjälä
I think this should provide most of necessary logic for
adding aspecr ratios to the HDMI 4k modes.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 37 +++--
1 file changed, 31 insertions(+), 6 deletions(-)
diff -
From: Ville Syrjälä
Extract the logic to compute the final CEA VIC to a small helper.
We'll reorder it a bit to make future modifications more
straightforward. No function changes.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 53 +
== Series Details ==
Series: series starting with [01/20] drm/i915: Only track bound elements of the
GTT
URL : https://patchwork.freedesktop.org/series/67594/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d11fa436d327 drm/i915: Only track bound elements of the GTT
800905fc6a4b
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Swati
> Sharma
> Sent: perjantai 4. lokakuuta 2019 11.26
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Nautiyal, Ankit K
>
> Subject: [Intel-gfx] [PATCH 0/4] fix broken state checker and enable state
> checker
> for i
This panel (manufacturer is SDC, product ID is 0x4141)
used manufacturer defined DPCD register to control brightness
that not defined in eDP spec so far. This change follow panel
vendor's instruction to support brightness adjustment.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97883
Cc
As our global unpark/park keep track of the number of active users, we
can simply move the accounting from the GEM layer to the base GT layer.
It was placed originally inside GEM to benefit from the 100ms extra
delay on idleness, but that has been eliminated and now there is no
substantive differen
Having a struct_mutex around the read of a BIOS blob serves no purpose.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers
Forgo the struct_mutex serialisation for i915_active, and interpose its
own mutex handling for active/retire.
This is a multi-layered sleight-of-hand. First, we had to ensure that no
active/retire callbacks accidentally inverted the mutex ordering rules,
nor assumed that they were themselves seria
We no longer need struct_mutex to serialise request emission, so remove
it from the gt selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 15 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 4 -
.../drm/i915/gem/selftests
It protects nothing being accessed for the intel_framebuffer, so it's
own locking had better be sufficient.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.
Quoting Mika Kuoppala (2019-10-04 14:51:05)
> Chris Wilson writes:
>
> > There's very little variation in non-privileged registers for Tigerlake,
> > so we can mostly inherit the set from gen11. There is no whitelist at
> > present, so we do not need to add any special registers.
> >
> > Bugzilla
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/vga: rename
intel_vga_msr_write() to intel_vga_reset_io_mem()
URL : https://patchwork.freedesktop.org/series/67592/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7007 -> Patchwork_14668
==
Chris Wilson writes:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Si
On 04/10/2019 14:40, Chris Wilson wrote:
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
v3: Correct split with removal of logical HW ID
Reviewed-by:
We no longer need to placate lockdep by holding struct_mutex for our
initialisation, so don't.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 --
drivers/gpu/drm/i915/i915_gem.c | 9 -
drivers/gpu/drm/i91
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
v3: Correct split with removal of logical HW ID
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
dri
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