== Series Details ==
Series: series starting with [1/5] drm/i915/display: Handle fused off display
correctly
URL : https://patchwork.freedesktop.org/series/68247/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7133_full -> Patchwork_14891_full
== Series Details ==
Series: series starting with [1/5] drm/i915/display: Handle fused off display
correctly
URL : https://patchwork.freedesktop.org/series/68247/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7133 -> Patchwork_14891
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: simplify setting of
ddi_io_power_domain (rev4)
URL : https://patchwork.freedesktop.org/series/68069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7132_full -> Patchwork_14890_full
If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above but for GEN9+ spec says
that hardware will override the pipe output to a solid color, so
some display is there and maybe we would need to shutdown display
to save power, so setting
Check if DMC is fused off and handle it.
Cc: Ville Syrjälä
Cc: Martin Peres
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
HDCP could be fused off, so not all GEN9+ platforms will support it.
Cc: Ville Syrjälä
Cc: Martin Peres
Reviewed-by: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 ++
DSC could be fused off, so not all GEN10+ platforms will support it.
Cc: Manasi Navare
Cc: Martin Peres
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
Check if FBC is fused off and handle it.
Cc: Ville Syrjälä
Cc: Martin Peres
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
On Thu, 2019-10-03 at 17:50 +0300, Imre Deak wrote:
> On Mon, Sep 30, 2019 at 05:55:36PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> >
> > BSpec: 21750
> > BSpsc: 49294
> >
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: simplify setting of
ddi_io_power_domain (rev4)
URL : https://patchwork.freedesktop.org/series/68069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7132 -> Patchwork_14890
Quoting Umesh Nerlige Ramappa (2019-10-18 01:50:27)
> From: Lionel Landwerlin
>
> We want this so we can preempt performance queries and keep the system
> responsive even when long running queries are ongoing. We avoid doing
> it for all contexts.
>
> v2: use LRI to modify context control
Quoting Kumar Valsan, Prathap (2019-10-19 00:24:13)
> On Fri, Oct 18, 2019 at 11:14:39PM +0100, Chris Wilson wrote:
> > +static int check_l3cc_table(struct intel_engine_cs *engine,
> > + const struct drm_i915_mocs_table *table,
> > + const u32
Pushed to dinq thanks for the reviews
Manasi
On Fri, Oct 18, 2019 at 10:27:24AM -0700, Manasi Navare wrote:
> This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> register during crtc_disable().
>
> v3:
> * Rebase on maarten's patches
> v2:
> * Directly write the
Pushed to dinq, thanks for reviews
manasi
On Fri, Oct 18, 2019 at 10:27:25AM -0700, Manasi Navare wrote:
> In the transcoder port sync mode, the slave transcoders mask their vblanks
> until master transcoder's vblank so while disabling them, make
> sure slaves are disabled first and then the
Pushed to dinq, thanks for the reviews
manasi
On Fri, Oct 18, 2019 at 10:27:23AM -0700, Manasi Navare wrote:
> As per the display enable sequence, we need to follow the enable sequence
> for slaves first with DP_TP_CTL set to Idle and configure the transcoder
> port sync register to select the
Pushed to dinq, thanks for reviews
Manasi
On Fri, Oct 18, 2019 at 10:27:22AM -0700, Manasi Navare wrote:
> After the state is committed, we readout the HW registers and compare
> the HW state with the SW state that we just committed.
> For Transcdoer port sync, we add master_transcoder and the
>
Pushed to dinq, thanks for reviews
Manasi
On Fri, Oct 18, 2019 at 10:27:21AM -0700, Manasi Navare wrote:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync
Pushed to dinq, thank you all for reviews!
Manasi
On Fri, Oct 18, 2019 at 10:27:20AM -0700, Manasi Navare wrote:
> In case of tiled displays when the two tiles are sent across two CRTCs
> over two separate DP SST connectors, we need a mechanism to synchronize
> the two CRTCs and their
On Fri, Oct 18, 2019 at 11:14:39PM +0100, Chris Wilson wrote:
> Probe the mocs registers for new contexts and across GPU resets. Similar
> to intel_workarounds, we have tables of what register values we expect
> to see, so verify that user contexts are affected by them. In the
> future, we should
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: simplify setting of
ddi_io_power_domain (rev4)
URL : https://patchwork.freedesktop.org/series/68069/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f64128fd71f7 drm/i915: simplify setting of
== Series Details ==
Series: series starting with [01/13] drm/i915: Don't set queue_priority_hint if
we don't kick the submission
URL : https://patchwork.freedesktop.org/series/68243/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7132 -> Patchwork_14889
Quoting Matthew Auld (2019-10-18 17:55:54)
> From: Abdiel Janulgue
>
> Signed-off-by: Abdiel Janulgue
> Cc: Matthew Auld
Looks reasonable,
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Matthew Auld (2019-10-18 17:55:55)
> From: Abdiel Janulgue
>
> We can create LMEM objects, but we also need to support mapping them
> into kernel space for internal use.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> Signed-off-by: Steve Hampson
> Cc: Joonas
Quoting Matthew Auld (2019-10-18 17:55:56)
> Simple test writing to dwords across an object, using various engines in
> a randomized order, checking that our writes land from the cpu.
>
> Signed-off-by: Matthew Auld
Looks like a good base to build upon, and gives a useful sanity check.
Quoting Matthew Auld (2019-10-18 17:55:57)
> Add LMEM objects to list of backends we test for huge-GTT-pages.
>
> Signed-off-by: Matthew Auld
Looks consistent with our current test strategy and useful,
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx
Quoting Matthew Auld (2019-10-18 17:55:58)
> Ditch the dubious static list of sizes to enumerate, in favour of
> choosing a random size within the limits of each backing store. With
> repeated CI runs this should give us a wider range of object sizes, and
> in turn more page-size combinations,
== Series Details ==
Series: series starting with [01/13] drm/i915: Don't set queue_priority_hint if
we don't kick the submission
URL : https://patchwork.freedesktop.org/series/68243/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Don't set
== Series Details ==
Series: series starting with [01/13] drm/i915: Don't set queue_priority_hint if
we don't kick the submission
URL : https://patchwork.freedesktop.org/series/68243/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f1bf3e6b4d69 drm/i915: Don't set
Both routines operate local to the intel_gt, so pass it along as the
object to work on.
Signed-off-by: Chris Wilson
---
.../drm/i915/gem/selftests/i915_gem_context.c | 30 +++--
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 4 +-
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Separate each object class into a separate lock type to avoid lockdep
cross-contamination between paths (i.e. userptr!).
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 3 ++-
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 14 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) the opportunity to run
and prevents livelocks were contexts may have implicit ordering due to
userspace
Our existing behaviour is to allow contexts and their GPU requests to
persist past the point of closure until the requests are complete. This
allows clients to operate in a 'fire-and-forget' manner where they can
setup a rendering pipeline and hand it over to the display server and
immediately
If we change the priority of the active context, then it has no impact
on the decision of whether to preempt the active context -- we don't
preempt the context with itself. In this situation, we elide the tasklet
rescheduling and should *not* be marking up the queue_priority_hint as
that may mask
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure.
Quoting Matthew Auld (2019-10-18 17:55:53)
> diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
> b/drivers/gpu/drm/i915/intel_region_lmem.c
> new file mode 100644
> index ..7a3f96e1f766
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_region_lmem.c
> @@ -0,0 +1,43 @@
> +//
Quoting Michal Wajdeczko (2019-10-18 16:52:26)
> On Fri, 18 Oct 2019 12:07:10 +0200, Janusz Krzysztofik
> wrote:
>
> > Commit 2d6f6f359fd8 ("drm/i915: add i915_driver_modeset_remove()")
> > claimed removal of asymmetry in probe() and remove() calls, however, it
> > didn't take care of calling
== Series Details ==
Series: series starting with [CI,v12,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/68218/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130_full ->
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130_full -> Patchwork_14887_full
On Fri, Oct 18, 2019 at 9:46 AM Tomi Valkeinen wrote:
>
> Hi Sean,
>
> On 17/10/2019 22:26, Sean Paul wrote:
>
> > concern for those. The omap OMAP_BO_MEM_* changes though I don't think have
> > really reached non-TI eyes. There's no link in the commit message to a UAPI
> > implementation and the
== Series Details ==
Series: drm/i915: Don't set queue_priority_hint if we don't kick the submission
URL : https://patchwork.freedesktop.org/series/68215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130_full -> Patchwork_14886_full
On Fri, Oct 18, 2019 at 12:43:56PM -0700, Manasi Navare wrote:
> From: Ville Syrjala
>
> From: Ville Syrjälä
>
> On ILK+ the documented min hdisplay is 64, min hblank is 32, and min
> vblank is 5. On earlier platforms min hblank is also 32, and min
> vblank is 3. Make sure the mode satisfies
From: Ville Syrjala
From: Ville Syrjälä
On ILK+ the documented min hdisplay is 64, min hblank is 32, and min
vblank is 5. On earlier platforms min hblank is also 32, and min
vblank is 3. Make sure the mode satisfies those limits.
There are further limits for HDMI and pfit use cases, but we'll
== Series Details ==
Series: series starting with [CI,v12,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/68218/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130 ->
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130 -> Patchwork_14887
-Original Message-
From: Intel-gfx On Behalf Of
intel-gfx-requ...@lists.freedesktop.org
Sent: Friday, October 18, 2019 7:30 PM
To: intel-gfx@lists.freedesktop.org
Subject: Intel-gfx Digest, Vol 141, Issue 541
Send Intel-gfx mailing list submissions to
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: support creating LMEM objects
Okay!
Commit:
== Series Details ==
Series: series starting with [1/6] drm/i915: support creating LMEM objects
URL : https://patchwork.freedesktop.org/series/68216/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
69e50fdbd4bb drm/i915: support creating LMEM objects
-:35:
== Series Details ==
Series: drm/i915: Don't set queue_priority_hint if we don't kick the submission
URL : https://patchwork.freedesktop.org/series/68215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7130 -> Patchwork_14886
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v3:
* Rebase on maarten's patches
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v5:
* Dont pass dev priv to get_slave_crtc (Ville)
v4:
* Obtain slave state from master (Maarten)
v3:
*
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Signed-off-by: Matthew
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 167 ++
1 file changed, 167 insertions(+)
diff --git
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36
If we change the priority of the active context, then it has no impact
on the decision of whether to preempt the active context -- we don't
preempt the context with itself. In this situation, we elide the tasklet
rescheduling and should *not* be marking up the queue_priority_hint as
that may mask
== Series Details ==
Series: drm/i915: Split memory_region initialisation into its own file
URL : https://patchwork.freedesktop.org/series/68200/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7129 -> Patchwork_14884
On Fri, Oct 18, 2019 at 04:01:56AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct the PCH type in irq postinstall (rev2)
> URL : https://patchwork.freedesktop.org/series/68116/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7122_full ->
== Series Details ==
Series: drm/i915/selftests: Add the mock engine to the gt->engine[]
URL : https://patchwork.freedesktop.org/series/68201/
State : failure
== Summary ==
Applying: drm/i915/selftests: Add the mock engine to the gt->engine[]
Using index info to reconstruct a base tree...
M
On Fri, 18 Oct 2019 at 13:48, Chris Wilson wrote:
>
> Pull the memory region bookkeeping into its file. Let's start clean and
> see how long it lasts!
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Much better,
Reviewed-by: Matthew Auld
___
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Friday, October 4, 2019 7:49 PM
>To: dri-de...@lists.freedesktop.org
>Cc: intel-gfx@lists.freedesktop.org; Wayne Lin
>Subject: [Intel-gfx] [PATCH 3/4] drm/edid: Fix HDMI VIC handling
>
>From: Ville Syrjälä
>
On Fri, 18 Oct 2019 12:07:10 +0200, Janusz Krzysztofik
wrote:
Commit 2d6f6f359fd8 ("drm/i915: add i915_driver_modeset_remove()")
claimed removal of asymmetry in probe() and remove() calls, however, it
didn't take care of calling intel_irq_uninstall() on driver remove.
That doesn't hurt as
== Series Details ==
Series: drm/i915: Split memory_region initialisation into its own file
URL : https://patchwork.freedesktop.org/series/68200/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
36c94b0bae3b drm/i915: Split memory_region initialisation into its own file
-:202:
== Series Details ==
Series: drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA (rev2)
URL : https://patchwork.freedesktop.org/series/68162/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7129 -> Patchwork_14883
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: enumerate and init each
supported region
URL : https://patchwork.freedesktop.org/series/68187/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7127_full -> Patchwork_14877_full
Op 17-10-2019 om 15:21 schreef Maarten Lankhorst:
> Now that we split plane_state which I didn't want to do yet, we can
> program the slave plane without requiring the master plane.
>
> This is useful for programming bigjoiner slave planes as well. We
> will no longer need the master's
On Thu, 2019-10-17 at 14:42 -0700, Daniele Ceraolo Spurio wrote:
>
> On 10/17/19 12:37 PM, Stuart Summers wrote:
> > During engine initialization in i915 load, the batch buffers
> > being used to set up the initial context are being prematurely
> > ended. In most scenarios, this does not cause a
On Thu, 17 Oct 2019 18:48:35 +0800
Jason Wang wrote:
> This patch introduces a new mdev transport for virtio. This is used to
> use kernel virtio driver to drive the mediated device that is capable
> of populating virtqueue directly.
>
> A new virtio-mdev driver will be registered to the mdev
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev5)
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7128 -> Patchwork_14882
Summary
On Fri, Oct 18, 2019 at 01:39:37PM +0100, Tvrtko Ursulin wrote:
>
> On 18/10/2019 13:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-18 13:23:53)
> > >
> > > On 17/10/2019 15:30, Chris Wilson wrote:
> > > > Dynamic subtests!
> > >
> > > Ouch! :)
> > >
> > > > Signed-off-by: Chris
Op 18-10-2019 om 12:57 schreef Patchwork:
> == Series Details ==
>
> Series: series starting with [01/14] drm/i915: Rework watermark readout to
> use plane api (rev2)
> URL : https://patchwork.freedesktop.org/series/68154/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
== Series Details ==
Series: drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2)
URL : https://patchwork.freedesktop.org/series/68194/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7128 -> Patchwork_14881
Summary
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev6)
URL : https://patchwork.freedesktop.org/series/66811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7128 -> Patchwork_14880
Summary
---
On Fri, Oct 18, 2019 at 01:06:39PM +0100, Chris Wilson wrote:
> Probe the mocs registers for new contexts and across GPU resets. Similar
> to intel_workarounds, we have tables of what register values we expect
> to see, so verify that user contexts are affected by them. In the
> future, we should
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev5)
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
221d3a170a43 drm/i915/selftests: Add coverage of mocs registers
-:29:
Hi Sean,
On 17/10/2019 22:26, Sean Paul wrote:
concern for those. The omap OMAP_BO_MEM_* changes though I don't think have
really reached non-TI eyes. There's no link in the commit message to a UAPI
implementation and the only reference I could find is libkmsxx which can set
them through the
Signed-off-by: Chris Wilson
---
tests/Makefile.sources| 1 +
tests/i915/sysfs_heartbeat_interval.c | 430 ++
tests/meson.build | 1 +
3 files changed, 432 insertions(+)
create mode 100644 tests/i915/sysfs_heartbeat_interval.c
diff
Signed-off-by: Chris Wilson
---
tests/Makefile.sources| 1 +
tests/i915/sysfs_timeslice_duration.c | 304 ++
tests/meson.build | 1 +
3 files changed, 306 insertions(+)
create mode 100644 tests/i915/sysfs_timeslice_duration.c
diff
Just a status update on the igt having fleshed them out some more.
-Chris
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Dynamic subtests!
Signed-off-by: Chris Wilson
---
lib/i915/gem_context.c| 41
lib/i915/gem_context.h| 2 +
tests/Makefile.sources| 1 +
tests/i915/sysfs_preemption_timeout.c | 310 ++
tests/meson.build
On Fri, 18 Oct 2019 18:55:02 +0800
Jason Wang wrote:
> On 2019/10/18 下午5:46, Cornelia Huck wrote:
> > On Thu, 17 Oct 2019 18:48:34 +0800
> > Jason Wang wrote:
> >> + * @get_vendor_id:Get virtio vendor id
> >> + *@mdev: mediated device
> >> + *
Quoting Tvrtko Ursulin (2019-10-18 14:22:39)
>
> On 18/10/2019 14:07, Chris Wilson wrote:
> > Remember to include the newly created mock engine in the list of
> > available engines inside the gt.
> >
> > Fixes: a50134b1983b ("drm/i915: Make for_each_engine_masked work on
> > intel_gt")
> >
On 18/10/2019 14:07, Chris Wilson wrote:
Remember to include the newly created mock engine in the list of
available engines inside the gt.
Fixes: a50134b1983b ("drm/i915: Make for_each_engine_masked work on intel_gt")
Signed-off-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wi..oh
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev6)
URL : https://patchwork.freedesktop.org/series/66811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7128 -> Patchwork_14880
Summary
---
On Fri, Oct 18, 2019 at 02:09:17PM +0200, Maarten Lankhorst wrote:
> Op 18-10-2019 om 12:36 schreef Ville Syrjälä:
> > On Thu, Oct 17, 2019 at 03:20:55PM +0200, Maarten Lankhorst wrote:
> >> Prepare to split up hw and uapi machinally, by adding a uapi and
> >> hw alias. We will remove the base in
On Friday, October 18, 2019 2:13:18 PM CEST Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Restore full symmetry in i915_driver_modeset_probe/remove
> URL : https://patchwork.freedesktop.org/series/68188/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
Remember to include the newly created mock engine in the list of
available engines inside the gt.
Fixes: a50134b1983b ("drm/i915: Make for_each_engine_masked work on intel_gt")
Signed-off-by: Chris Wilson
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/mock_engine.c | 4
1 file changed, 4
On Thu, Oct 17, 2019 at 03:20:57PM +0200, Maarten Lankhorst wrote:
> Split up crtc_state->base to hw where appropriate. This is done using the
> following patch:
>
> @@
> struct intel_crtc_state *T;
> identifier x =~
> "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
> @@
>
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