== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14937
Summary
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad3f8ef792a4 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
== Series Details ==
Series: drm/i915/selftests: Release ctx->engine_mutex after iteration
URL : https://patchwork.freedesktop.org/series/68420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14936
Summary
== Series Details ==
Series: drm/i915: Fix PCH reference clock for FDI on HSW/BDW
URL : https://patchwork.freedesktop.org/series/68411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14935
Summary
---
== Series Details ==
Series: doc: Update header files names
URL : https://patchwork.freedesktop.org/series/68381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7150_full -> Patchwork_14917_full
Summary
---
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14934
Summary
---
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14932
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse
Gen12 display can decompress surfaces compressed by render engine with Clear
Color, add
a new modifier as the driver needs to know the surface was compressed by render
engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev2)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
Applying: drm/i915: Refactor intel_can_enable_sagv
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_pm.c).
error: could
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
714257337388 drm/i915/guc: Enable guc logging on guc log
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev2)
URL : https://patchwork.freedesktop.org/series/68081/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14929
Summary
---
== Series Details ==
Series: drm/i915/gem: Distinguish each object type (rev2)
URL : https://patchwork.freedesktop.org/series/67948/
State : failure
== Summary ==
Applying: drm/i915/gem: Distinguish each object type
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: series starting with [v2] drm/i915: Teach record_defaults to operate on
the intel_gt (rev2)
URL : https://patchwork.freedesktop.org/series/68391/
State : failure
== Summary ==
Applying: drm/i915: Teach record_defaults to operate on the intel_gt
Using index info
== Series Details ==
Series: Add scaling filters in DRM layer
URL : https://patchwork.freedesktop.org/series/68378/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7149_full -> Patchwork_14916_full
Summary
---
== Series Details ==
Series: drm/i915/bios: add compression parameter block definition
URL : https://patchwork.freedesktop.org/series/68396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14928
Summary
== Series Details ==
Series: drm/i915: Use uabi engines for the default engine map
URL : https://patchwork.freedesktop.org/series/68395/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14927
Summary
---
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine
Allow ourselves to sleep before a GPU reset, for a few milliseconds.
This allows for userspace to gracefully quiesce before being shot down.
By stopping submission and then waiting for the current requests to
complete, we are less likely to disrupt innocent contexts by performing
the reset while
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen
Signed-off-by: Chris Wilson
Cc:
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure.
Our existing behaviour is to allow contexts and their GPU requests to
persist past the point of closure until the requests are complete. This
allows clients to operate in a 'fire-and-forget' manner where they can
setup a rendering pipeline and hand it over to the display server and
immediately
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 21 -
drivers/gpu/drm/i915/selftests/i915_active.c | 46
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual
A lock once taken must be released again.
Fixes: c31c9e82ee8a ("drm/i915/selftests: Teach switch_to_context() to use the
context")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/selftests/i915_gem.c | 10 +++---
1 file changed,
== Series Details ==
Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params
member to dsc
URL : https://patchwork.freedesktop.org/series/68394/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14926
== Series Details ==
Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params
member to dsc
URL : https://patchwork.freedesktop.org/series/68394/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
884c1ae47848 drm/i915/dsc: rename crtc state dsc_params member
== Series Details ==
Series: drm/i915/selftests: Move uncore fw selftests to operate on intel_gt
URL : https://patchwork.freedesktop.org/series/68392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7154 -> Patchwork_14925
On Mon, Oct 21, 2019 at 10:36:02PM -0400, Lyude Paul wrote:
> This probably hasn't caused any problems up until now since it's
> probably nearly impossible to encounter this in the wild, however if we
> were to receive a connection status notification from the MST hub after
> resume while we're in
== Series Details ==
Series: drm/i915/selftests: Set vm->gt backpointer for mock_ppgtt
URL : https://patchwork.freedesktop.org/series/68376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7147_full -> Patchwork_14915_full
On Mon, Oct 21, 2019 at 10:36:01PM -0400, Lyude Paul wrote:
> This is a complicated one. Essentially, there's currently a problem in the MST
> core that hasn't really caused any issues that we're aware of (emphasis on
> "that
> we're aware of"): locking.
>
> When we go through and probe the link
Hi Chris,
On Tue, Oct 22, 2019 at 12:21:11PM +0100, Chris Wilson wrote:
> If retirement is running on another thread, we may inspect the status of
> the i915_active before its retirement callback is complete. As we expect
> it to be running synchronously, we can wait for any callback to complete
== Series Details ==
Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow
PTE on tgl as on all others (rev2)
URL : https://patchwork.freedesktop.org/series/68388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7154 -> Patchwork_14923
== Series Details ==
Series: drm/i915: Drop assertion that ce->pin_mutex guards state updates (rev2)
URL : https://patchwork.freedesktop.org/series/68252/
State : failure
== Summary ==
Applying: drm/i915: Drop assertion that ce->pin_mutex guards state updates
Using index info to reconstruct a
== Series Details ==
Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow
PTE on tgl as on all others (rev2)
URL : https://patchwork.freedesktop.org/series/68388/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0331f204fce6 drm/i915/gt: Set unused
== Series Details ==
Series: drm/i915/selftests: Synchronize checking active status with retirement
URL : https://patchwork.freedesktop.org/series/68385/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7154 -> Patchwork_14922
From: "Paul E. McKenney"
This commit replaces the use of rcu_swap_protected() with the more
intuitively appealing rcu_replace() as a step towards removing
rcu_swap_protected().
Link:
https://lore.kernel.org/lkml/CAHk-=wiAsJLw1egFEE=z7-ggtm6wcvtyytxza1+bhqta4gg...@mail.gmail.com/
Reported-by:
== Series Details ==
Series: drm/i915: Add new CNL PCH ID seen on a CML platform
URL : https://patchwork.freedesktop.org/series/68375/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7147_full -> Patchwork_14914_full
Summary
From: Ville Syrjälä
The change to skip the PCH reference initialization during fastboot
did end up breaking FDI. To fix that let's try to do the PCH reference
init whenever we're disabling a DPLL that was using said reference
previously.
Cc: sta...@vger.kernel.org
Tested-by: Andrija
Bugzilla:
== Series Details ==
Series: series starting with [01/14] drm/i915: Rework watermark readout to use
plane api (rev3)
URL : https://patchwork.freedesktop.org/series/68154/
State : failure
== Summary ==
Applying: drm/i915: Rework watermark readout to use plane api
Applying: drm/i915: Introduce
== Series Details ==
Series: drm/i915/selftests: Make the mman object busy everywhere
URL : https://patchwork.freedesktop.org/series/68383/
State : failure
== Summary ==
Applying: drm/i915/selftests: Make the mman object busy everywhere
Using index info to reconstruct a base tree...
M
On 10/22/19 6:44 AM, Tvrtko Ursulin wrote:
On 22/10/2019 14:10, Chris Wilson wrote:
Forcewake is the speciality of the GT, so it is natural to run the
intel_uncore_forcewake tests over the GT. So pass intel_gt as the
parameter to our selftests.
I had the same urge yesterday but then ended
On Tue, Oct 22, 2019 at 08:37:58PM +0530, Animesh Manna wrote:
>
> On 10/22/2019 5:17 AM, Manasi Navare wrote:
> >On Thu, Oct 03, 2019 at 08:36:53PM +0530, Animesh Manna wrote:
> >>This patch process phy compliance request by programming requested
> >>vswing, pre-emphasis and test pattern.
> >So
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, October 22, 2019 11:15 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re:
On Thu, Oct 17, 2019 at 03:20:59PM +0200, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
>
== Series Details ==
Series: drm/i915/perf: Describe structure members in documentation
URL : https://patchwork.freedesktop.org/series/68382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7153 -> Patchwork_14919
Summary
On Fri, Oct 18, 2019 at 10:13:23AM +0200, Maarten Lankhorst wrote:
> intel_get_load_detect_pipe() needs to set uapi active,
> uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
> so we can remove it.
>
> intel_pipe_config_compare() needs to look at hw state, but I didn't
> change
On Tue, Oct 22, 2019 at 12:31:49PM +0200, Maarten Lankhorst wrote:
> From: Maarten Lankhorst
>
> Now that we split plane_state which I didn't want to do yet, we can
> program the slave plane without requiring the master plane.
>
> This is useful for programming bigjoiner slave planes as well.
On Mon, Oct 14, 2019 at 05:05:33PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
>
Hi!
On Tue, 2019-10-22 at 07:44:26 +1100, Stephen Rothwell wrote:
> Fixes tag
>
> Fixes: 7a074e96 ("aio: implement io_pgetevents")
>
> has these problem(s):
>
> - SHA1 should be at least 12 digits long
> Can be fixed by setting core.abbrev to 12 (or more) or (for git v2.11
> or
On 2019-10-22 8:20 a.m., Ville Syrjälä wrote:
> On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
>> This patch adds a scaling filter mode porperty
>> to allow:
>> - A driver/HW to showcase it's scaling filter capabilities.
>> - A userspace to pick a desired effect while scaling.
From: Ville Syrjälä
Most of the pfit functions are of the form:
func()
{
if (pfit_enabled) {
...
}
}
Flip the pfit_enabled check around to flatten the functions.
And while we're touching all this let's do the usual
s/pipe_config/crtc_state/ replacement.
From: Ville Syrjälä
Make the PFIT_PIPE stuff less ugly via parametrization.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Fix skl_update_scaler_crtc() to deal with different scaling
modes correctly. The current implementation assumes
DRM_MODE_SCALE_FULLSCREEN. Fortunately we don't expose any
border properties currently so the code does actually end
up doing the right thing (assigning a scaler
From: Ville Syrjälä
Pass the entire connector state to intel_{gmch,pch}_panel_fitting().
For now we just need to get at .scaling_mode but in the future we'll
want access to the margin properties as well.
v2: Deal with intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Follow the new naming convention and call the crtc state
"crtc_state", and while at it drop the redundant crtc argument.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c| 8 +-
From: Ville Syrjälä
Change intel_{gmch,pch}_panel_fitting() to return a normal
error vs. success int. We'll need this later to validate that
the margin properties aren't misconfigured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++---
From: Ville Syrjälä
I'm reworking a bunch of the scaler/pfit stuff to allow
us to expose the TV margin properties, properly check all
the hardware scaling limits, and just generally cleaning
up a bunch of bitrotted scaler code. Here are some easy
prep patches.
Ville Syrjälä (8):
drm/i915:
From: Ville Syrjälä
Make things a bit more abstract by replacing the pch_pfit.pos/size
raw register values with a drm_rect. Makes it slighly more convenient
to eg. compute the scaling factors.
v2: Use drm_rect_init()
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Some I915_READ_FW()s have snuck in where we don't hold the uncore lock.
Replace with the normal thing for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On Tue, 2019-10-22 at 12:51 +0300, Imre Deak wrote:
> Atm we don't detect a PCH with PCI ID 0xA3C1 which showed up now on a
> CML
> platform. We don't have the official assignment of the PCH PCI IDs,
> but
> this looks like a CNP which was already used on CML platforms. Let's
> add
> the new
On Tue, Oct 22, 2019 at 07:34:13PM +0530, Animesh Manna wrote:
>
> On 10/22/2019 4:27 AM, Manasi Navare wrote:
> >On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
> >>vswing/pre-emphasis adjustment calculation is needed in processing
> >>of auto phy compliance request other than
== Series Details ==
Series: drm/dsi: cleanups and compression helpers
URL : https://patchwork.freedesktop.org/series/68379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7153 -> Patchwork_14918
Summary
---
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Stanislav Lisovskiy (2):
On Tue, Oct 22, 2019 at 04:34:13PM +0300, Jani Nikula wrote:
> Reduce verbosity in code by renaming dsc_params member of crtc state to
> simply dsc. There is enough context for this to be clear. No functional
> changes.
Makes sense to just call it dsc
Reviewed-by: Manasi Navare
Manasi
>
>
== Series Details ==
Series: series starting with [01/10] i915: Exercise hostile context execution
URL : https://patchwork.freedesktop.org/series/68404/
State : warning
== Summary ==
Did not get list of undocumented tests for this run, something is wrong!
Other than that, pipeline status:
On Tue, Oct 22, 2019 at 04:34:14PM +0300, Jani Nikula wrote:
> DSC isn't DP specific, so remove the dp_ prefix from the crtc state
> member name. Also moving the member under the dsc sub-struct gives us
> enough context to allow shortening the name to just config. No
> functional changes.
>
> Cc:
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
Reviewed-by: Daniele Ceraolo Spurio
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
---
On Mon, Oct 21, 2019 at 10:36:00PM -0400, Lyude Paul wrote:
> Currently, MST lacks locking in a lot of places that really should have
> some sort of locking. Hotplugging and link address code paths are some
> of the offenders here, as there is actually nothing preventing us from
> running a link
On 22/10/2019 15:19, Chris Wilson wrote:
Again we wish to operate on the engines, which are owned by the
intel_gt. As such it is easier, and much more consistent, to pass the
intel_gt parameter.
v2: Unexport i915_gem_load_power_context()
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson
---
lib/i915/gem_engine_topology.c | 84 ++
Sanity test existing persistence and new exciting non-persistent context
behaviour.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
tests/Makefile.sources | 3 +
I915_CONTEXT_PARAM_RINGSIZE specifies how large to create the command
ringbuffer for logical ring contects. This directly affects the number
of batches userspace can submit before blocking waiting for space.
Signed-off-by: Chris Wilson
---
tests/Makefile.sources| 3 +
Expose a new context parameters to opting out of persistent behaviour.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
lib/i915/gem_context.c | 37 +
lib/i915/gem_context.h | 8
2 files changed, 45 insertions(+)
diff --git
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_isolation.c | 160 -
1
We [will] expose various per-engine scheduling controls. One of which,
'heartbeat_duration_ms', defines how often we send a heartbeat down the
engine to check upon the health of the engine. If a heartbeat does not
complete within the interval (or two), the engine is declared hung.
Signed-off-by:
Verify that contexts are automatically shotdown on close if hangchecking
is disabled.
Basic environmental robustness test stolen from gem_ctx_persistence.
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_exec.c | 41
We [will] expose various per-engine scheduling controls. One of which,
'timeslice_duration_ms', defines the scheduling quantum. If a context
exhausts its timeslice, it will be preempted in favour of running one of
its compatriots.
Signed-off-by: Chris Wilson
---
tests/Makefile.sources
Update to commit fef476f3ab47527a00818ddaf4b46b8c0936 (not upstream!)
Author: Chris Wilson
Date: Mon Aug 5 22:55:44 2019 +0100
drm/i915: Cancel non-persistent contexts on close
for I915_CONTEXT_PARAM_PERSISTENCE
---
include/drm-uapi/i915_drm.h | 22 --
1 file
We [will] expose various per-engine scheduling controls. One of which,
'preempt_timeout_ms', defines how we wait for a preemption request to be
honoured by the currently executing context. If it fails to relieve the
GPU within the required timeout, the engine is reset and the miscreant
forcibly
On Tue, Oct 22, 2019 at 03:03:18AM +0300, Souza, Jose wrote:
> [...]
> Makes sense, well the only doubt that I have is if getting
> POWER_DOMAIN_AUX__TBT will prevent TCCOLD for legacy and alt-
> mode,
Why do we need to care about POWER_DOMAIN_AUX__TBT? It doesn't
affect the TCCOLD state and we
Quoting Tvrtko Ursulin (2019-10-22 16:43:17)
>
> On 22/10/2019 14:56, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-22 14:40:42)
> >>
> >> On 22/10/2019 14:02, Chris Wilson wrote:
> >>> Again we wish to operate on the engines, which are owned by the
> >>> intel_gt. As such it is easier,
Verify that contexts are automatically shotdown on close if hangchecking
is disabled.
Basic environmental robustness test stolen from gem_ctx_persistence.
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_exec.c | 41
On 22/10/2019 14:56, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-22 14:40:42)
On 22/10/2019 14:02, Chris Wilson wrote:
Again we wish to operate on the engines, which are owned by the
intel_gt. As such it is easier, and much more consistent, to pass the
intel_gt parameter.
On Tue, Oct 22, 2019 at 02:06:22PM +, Harry Wentland wrote:
>
>
> On 2019-10-22 8:20 a.m., Ville Syrjälä wrote:
> > On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
> >> This patch adds a scaling filter mode porperty
> >> to allow:
> >> - A driver/HW to showcase it's scaling
On Tue, Oct 22, 2019 at 08:51:20PM +0530, Sharma, Shashank wrote:
>
> On 10/22/2019 5:56 PM, Ville Syrjälä wrote:
> > On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
> >> This patch adds a scaling filter mode porperty
> >> to allow:
> >> - A driver/HW to showcase it's scaling
Hello Harry,
Thanks for your comments, please find mine inline.
On 10/22/2019 7:36 PM, Harry Wentland wrote:
On 2019-10-22 8:20 a.m., Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW
Hello Mihail,
Thanks for your review, my comments inline.
On 10/22/2019 6:56 PM, Mihail Atanassov wrote:
Hi Shashank,
On Tuesday, 22 October 2019 10:59:44 BST Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter
Quoting Tvrtko Ursulin (2019-10-22 14:44:31)
>
> On 22/10/2019 14:10, Chris Wilson wrote:
> > Forcewake is the speciality of the GT, so it is natural to run the
> > intel_uncore_forcewake tests over the GT. So pass intel_gt as the
> > parameter to our selftests.
>
> I had the same urge yesterday
On 10/22/2019 5:56 PM, Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter capabilities.
- A userspace to pick a desired effect while scaling.
This option
Hello Ville,
Thanks for the comments, mine inline.
On 10/22/2019 5:50 PM, Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter capabilities.
- A userspace
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