[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gen9: Add missing 10bpc formats

== Series Details == Series: drm/i915/gen9: Add missing 10bpc formats URL : https://patchwork.freedesktop.org/series/69272/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7301 -> Patchwork_15209 Summary --- **FAILURE*

[Intel-gfx] [PATCH] drm/i915/gen9: Add missing 10bpc formats

Add 10bpc formats for gen9. This patch has dependency on below patch: https://patchwork.freedesktop.org/patch/335029/?series=67741&rev=2 Signed-off-by: Kishore Kadiyala --- drivers/gpu/drm/i915/display/intel_sprite.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/disp

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pmu: "Frequency" is reported as accumulated cycles

== Series Details == Series: drm/i915/pmu: "Frequency" is reported as accumulated cycles URL : https://patchwork.freedesktop.org/series/69233/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15203_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: do not warn late about hdmi on port A

== Series Details == Series: drm/i915: do not warn late about hdmi on port A URL : https://patchwork.freedesktop.org/series/69226/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15201_full Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/25] drm/i915: Protect context while grabbing its name for the request

== Series Details == Series: series starting with [01/25] drm/i915: Protect context while grabbing its name for the request URL : https://patchwork.freedesktop.org/series/69265/ State : success == Summary == CI Bug Log - changes from CI_DRM_7301 -> Patchwork_15208

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/25] drm/i915: Protect context while grabbing its name for the request

== Series Details == Series: series starting with [01/25] drm/i915: Protect context while grabbing its name for the request URL : https://patchwork.freedesktop.org/series/69265/ State : warning == Summary == $ dim checkpatch origin/drm-tip d402853e5a38 drm/i915: Protect context while grabbing

[Intel-gfx] [PATCH 10/25] drm/i915/execlists: Reduce barrier on context switch to a wmb()

Having been forced to reduce Braswell back to using the aliasing ppgtt, the coherency issue we previously observed cannot impact us. Reduce the performance penalty imposed on all platforms from using the mfence to a mere sfence. References: cf66b8a0ba14 ("drm/i915/execlists: Apply a full mb before

[Intel-gfx] [PATCH 08/25] drm/i915: Show guilty context name on GPU reset

We mention that we are resetting the GPU, and dump the device state for post mortem debugging. However, while that dump contains the active processes and the one flagged as causing the error, we do not always include that information in dmesg. Include the name of the guilty process in dmesg for ref

[Intel-gfx] [PATCH 04/25] drm/i915/execlists: Move reset_active() from schedule-out to schedule-in

The gem_ctx_persistence/smoketest was detecting an odd coherency issue inside the LRC context image; that the address of the ring buffer did not match our associated struct intel_ring. As we set the address into the context image when we pin the ring buffer into place before the context is active,

[Intel-gfx] [PATCH 12/25] drm/i915/userptr: Try to acquire the page lock around set_page_dirty()

set_page_dirty says: For pages with a mapping this should be done under the page lock for the benefit of asynchronous memory errors who prefer a consistent dirty state. This rule can be broken in some special cases, but should be better not to. Under those rules, i

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/bios: rename bios to oprom when mapping pci rom

== Series Details == Series: series starting with [1/3] drm/i915/bios: rename bios to oprom when mapping pci rom URL : https://patchwork.freedesktop.org/series/69220/ State : success == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15200_full =

[Intel-gfx] [PATCH 22/25] drm/i915: Remove i915->kernel_context

Allocate only an internal intel_context for the kernel_context, forgoing a global GEM context for internal use as we only require a separate address space (for our own protection). Now having weaned GT from requiring ce->gem_context, we can stop referencing it entirely. This also means we no longe

[Intel-gfx] [PATCH 20/25] drm/i915: Drop GEM context as a direct link from i915_request

Keep the intel_context as being the primary state for i915_request, with the GEM context a backpointer from the low level state for the rarer cases we need client information. Our goal is to remove such references to clients from the backend, and leave the HW submission agnostic to client interface

[Intel-gfx] [PATCH 11/25] drm/i915/gem: Silence sparse for RCU protection inside the constructor

Inside the constructor, while cloning, we need to replace the dst->engines. Having forgotten that dst->engines is marked as RCU protected, we need to add the appropriate annotations to make sparse happy. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gem/i915_gem_contex

[Intel-gfx] [PATCH 17/25] drm/i915/selftests: Fill all the drm_vma_manager holes

To test mmap_offset_exhaustion, we first have to fill the entire vma manager leaving a single page. Don't assume that the vma manager is not already fragment, and fill all the holes. Signed-off-by: Chris Wilson Cc: Matthew Auld --- .../drm/i915/gem/selftests/i915_gem_mman.c| 45

[Intel-gfx] [PATCH 16/25] drm/i915/selftests: Mock the engine sorting for easy validation

To make exploration of different sorting orders and presentation of the engines via the uabi easier, wrap the basic engine registration into a mock (aka standalone) selftest. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 + .../gpu/drm/i91

[Intel-gfx] [PATCH 24/25] drm/i915/uc: Use an internal buffer for firmware images

Since the lifetime of the uc_fw is virtually identical to the current pinned range, simplify the setup to avoid using a swappable shmem file, and just use an internal bo. The immediate advantage is in removing the extra pin/unpin stages during init that are very difficult to balance along error pat

[Intel-gfx] [PATCH 07/25] drm/i915: Cancel context if it hangs after it is closed

If we detect a hang in a closed context, just flush all of its requests and cancel any remaining execution along the context. Note that after closing the context, the last reference to the context may be dropped, leaving it only valid under RCU. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 09/25] drm/i915/icl: Refine PG_HYSTERESIS

After doing some measuring, Icelake behaves on a par with Broadwell, and without having to compromise for low power cores with long latencies, we can reduce the powergating hysteresis so that the powersaving is enabled faster. No impact observed on client side throughput measures (so negligible inc

[Intel-gfx] [PATCH 21/25] drm/i915: Push the use-semaphore marker onto the intel_context

Instead of rummaging through the intel_context to peek at the GEM context in the middle of request submission to decide whether to use semaphores, store that information on the intel_context itself. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 52 +-

[Intel-gfx] [PATCH 06/25] drm/i915/userptr: Handle unlocked gup retries

Enable gup to retry and fault the pages outside of the mmap_sem lock in our worker. As we are inside our worker, outside of any critical path, we can allow the mmap_sem lock to be dropped in order to service a page fault; this in turn allows the mm to populate the page using a slow fault handler.

[Intel-gfx] [PATCH 05/25] drm/i915/pmu: "Frequency" is reported as accumulated cycles

We report "frequencies" (actual-frequency, requested-frequency) as the number of accumulated cycles so that the average frequency over that period may be determined by the user. This means the units we report to the user are Mcycles (or just M), not MHz. Signed-off-by: Chris Wilson Cc: Tvrtko Urs

[Intel-gfx] [PATCH 15/25] drm/i915/selftests: Perform some basic cycle counting of MI ops

Some basic information that is useful to know, such as how many cycles is a MI_NOOP. Signed-off-by: Chris Wilson Cc: Anna Karas Cc: Tvrtko Ursulin --- .../i915/gem/selftests/i915_gem_object_blt.c | 15 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 339 +- drivers/gpu/drm

[Intel-gfx] [PATCH 03/25] drm/i915/gem: Update context name on closing

Update the context.name on closing so that the persistent requests are clear in debug prints. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers

[Intel-gfx] [PATCH 18/25] Revert "drm/i915: use a separate context for gpu relocs"

Since commit c45e788d95b4 ("drm/i915/tgl: Suspend pre-parser across GTT invalidations"), we now disable the advanced preparser on Tigerlake for the invalidation phase at the start of the batch, we no longer need to emit the GPU relocations from a second context as they are now flushed inlined. Ref

[Intel-gfx] [PATCH 25/25] drm/i915/gt: Pull GT initialisation under intel_gt_init()

Begin pulling the GT setup underneath a single GT umbrella; let intel_gt take ownership of its engines! As hinted, the complication is the lifetime of the probed engine versus the active lifetime of the GT backends. We need to detect the engine layout early and keep it until the end so that we can

[Intel-gfx] [PATCH 01/25] drm/i915: Protect context while grabbing its name for the request

Inside print_request(), we query the context/timeline name. Nothing immediately protects the context from being freed if the request is complete -- we rely on serialisation by the caller to keep the name valid until they finish using it. Inside intel_engine_dump(), we generally only print the requs

[Intel-gfx] [PATCH 14/25] drm/i915/selftests: Exercise parallel blit operations on a single ctx

Make sure that our code is robust enough to handle multiple threads trying to clear objects for a single client context. This brings the joy of a shared GGTT to all! References: https://bugs.freedesktop.org/show_bug.cgi?id=112176 Signed-off-by: Chris Wilson Cc: Matthew Auld --- .../i915/gem/sel

[Intel-gfx] [PATCH 13/25] drm/i915: Taint the kernel on dumping the GEM ftrace buffer

As the ftrace buffer is single shot, once dumped it will not update. As such, it only provides information for the first bug and all subsequent bugs are noise. The goal of CI is to have zero bugs, so taint the kernel causing CI to reboot the machine; fix the bug and move on. Signed-off-by: Chris W

[Intel-gfx] [PATCH 19/25] drm/i915: Use a ctor for TYPESAFE_BY_RCU i915_request

As we start peeking into requests for longer and longer, e.g. incorporating use of spinlocks when only protected by an rcu_read_lock(), we need to be careful in how we reset the request when recycling and need to preserve any barriers that may still be in use as the request is reset for reuse. Sig

[Intel-gfx] [PATCH 02/25] drm/i915/gem: Embed context/timeline name inside the GEM context

Use a small char buffer inside the i915_gem_context to store the user friendly name so that ctx->name has the same lifetime as the RCU protected GEM context. That is, e.g. when using print_request() that prints the timeline name (ctx->name), the name will not be prematurely freed upon the context b

[Intel-gfx] [PATCH 23/25] drm/i915: Move i915_gem_init_contexts() earlier

As the GEM global context setup is now independent of the GT state (although GT does currently still depending upon the global i915->kernel_context), we can move its init earlier, leaving the gt init ready to extracted. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c

Re: [Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

On Fri, Nov 08, 2019 at 09:22:00AM +0200, Lionel Landwerlin wrote: On 08/11/2019 01:34, Umesh Nerlige Ramappa wrote: It turns out that the OAR CONTROL register is not getting configured correctly in conjunction with the context save/restore bit. When measuring work for a single context, the OAR

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Track gup locked track

== Series Details == Series: drm/i915/userptr: Track gup locked track URL : https://patchwork.freedesktop.org/series/69218/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15199_full Summary ---

[Intel-gfx] [RFC PATCH] drm/i915/bios: find_vbt() can be static

Fixes: bee6eeb3ee67 ("drm/i915/bios: do not discard address space") Signed-off-by: kbuild test robot --- intel_bios.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 8dae8eb90d0da.

Re: [Intel-gfx] [PATCH 4/4] drm/i915/bios: do not discard address space

use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/drm-i915-opregion-fix-leaking-fw-on-error-path/20191110-000822 base: git://anongit.freedesktop.org/drm-intel

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Show guilty context name on GPU reset

== Series Details == Series: drm/i915: Show guilty context name on GPU reset URL : https://patchwork.freedesktop.org/series/69217/ State : success == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15198_full Summary

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsi: enable DSC

== Series Details == Series: drm/i915/dsi: enable DSC URL : https://patchwork.freedesktop.org/series/69202/ State : success == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15197_full Summary --- **SUCCESS** N

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Gamma cleanups (rev2)

== Series Details == Series: drm/i915: Gamma cleanups (rev2) URL : https://patchwork.freedesktop.org/series/69136/ State : success == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15196_full Summary --- **WARNING

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable second dbuf slice for ICL and TGL (rev3)

== Series Details == Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev3) URL : https://patchwork.freedesktop.org/series/69124/ State : success == Summary == CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15195_full Su

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC method to determine if submission is active.

On Wed, Nov 06, 2019 at 09:40:02AM -0800, don.hi...@intel.com wrote: > Add intel_guc_submission_is_enabled() function to determine if > GuC submission is active. Based on code by Michal Wajdeczko. Don't forget to update USES_GUC_SUBMISSION (and/or intel_uc_uses_guc_submission) to use this new func

[Intel-gfx] ✗ Fi.CI.IGT: failure for tools: Add a simple rapl wrapper

== Series Details == Series: tools: Add a simple rapl wrapper URL : https://patchwork.freedesktop.org/series/69213/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7299_full -> IGTPW_3673_full Summary --- **FAILURE**