On Mon, Nov 11, 2019 at 2:11 PM Steven Price wrote:
>
> On 04/11/2019 17:37, Daniel Vetter wrote:
> > Full audit of everyone:
> >
> > - i915, radeon, amdgpu should be clean per their maintainers.
> >
> > - vram helpers should be fine, they don't do command submission, so
> > really no business h
On 11/11/2019 14:32, Chris Wilson wrote:
Quoting Chris Wilson (2019-11-11 14:27:16)
Quoting Tvrtko Ursulin (2019-11-11 14:19:31)
On 11/11/2019 13:32, Chris Wilson wrote:
Enable gup to retry and fault the pages outside of the mmap_sem lock in
our worker. As we are inside our worker, outside o
On 11/11/2019 11:40, Chris Wilson wrote:
We cannot control how long RCU takes to find a quiescent point as that
depends upon the background load and so may take an arbitrary time.
Instead, let's try to avoid that impacting our measurements by inserting
an rcu_barrier() before our critical timing
== Series Details ==
Series: drm/i915/tgl: Do not read the transcoder register for mipi dsi
URL : https://patchwork.freedesktop.org/series/69288/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c8589c17d46 drm/i915/tgl: Do not read the transcoder register for mipi dsi
-:23: CHEC
On 11/11/2019 13:32, Chris Wilson wrote:
The gem_ctx_persistence/smoketest was detecting an odd coherency issue
inside the LRC context image; that the address of the ring buffer did
not match our associated struct intel_ring. As we set the address into
the context image when we pin the ring buff
Quoting Tvrtko Ursulin (2019-11-11 16:31:09)
>
> On 11/11/2019 13:32, Chris Wilson wrote:
> > The gem_ctx_persistence/smoketest was detecting an odd coherency issue
> > inside the LRC context image; that the address of the ring buffer did
> > not match our associated struct intel_ring. As we set t
On 08/11/2019 20:49, Chris Wilson wrote:
Register a userspace fault handler for a memory region that we also pass
to the GPU via userptr, and make sure the pagefault is properly serviced
before we execute.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_userptr_blits.c | 1
== Series Details ==
Series: drm/i915/tgl: Do not read the transcoder register for mipi dsi
URL : https://patchwork.freedesktop.org/series/69288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7309 -> Patchwork_15212
Summary
Quoting Tvrtko Ursulin (2019-11-11 16:48:14)
>
> On 08/11/2019 20:49, Chris Wilson wrote:
> > Register a userspace fault handler for a memory region that we also pass
> > to the GPU via userptr, and make sure the pagefault is properly serviced
> > before we execute.
> >
> > Signed-off-by: Chris W
On Sun, 10 Nov 2019 at 18:58, Chris Wilson wrote:
>
> Some basic information that is useful to know, such as how many cycles
> is a MI_NOOP.
>
> Signed-off-by: Chris Wilson
> Cc: Anna Karas
> Cc: Tvrtko Ursulin
> ---
> .../i915/gem/selftests/i915_gem_object_blt.c | 15 +-
> drivers/gpu/drm/i
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Protect context while grabbing
its name for the request
URL : https://patchwork.freedesktop.org/series/69289/
State : failure
== Summary ==
Applying: drm/i915: Protect context while grabbing its name for the request
Using in
Quoting Matthew Auld (2019-11-11 17:10:37)
> On Sun, 10 Nov 2019 at 18:58, Chris Wilson wrote:
> > +static struct i915_vma *create_empty_batch(struct intel_context *ce)
> > +{
> > + struct drm_i915_gem_object *obj;
> > + struct i915_vma *vma;
> > + u32 *cs;
> > + int err;
>
== Series Details ==
Series: Add support for mipi dsi cmd mode
URL : https://patchwork.freedesktop.org/series/69290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8ed082b3989c drm/i915/dsi: Define command mode registers
0b38d9ee6cc7 drm/i915/dsi: Configure transcoder operation
On Mon, 11 Nov 2019 at 17:16, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-11-11 17:10:37)
> > On Sun, 10 Nov 2019 at 18:58, Chris Wilson wrote:
> > > +static struct i915_vma *create_empty_batch(struct intel_context *ce)
> > > +{
> > > + struct drm_i915_gem_object *obj;
> > > +
== Series Details ==
Series: Add support for mipi dsi cmd mode
URL : https://patchwork.freedesktop.org/series/69290/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsi: Define command mode registers
Okay!
Commit: drm/i915/dsi: Configure trans
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
v2: Keep volatile pages pinned at all times! (Matthew)
Signed-off-by: Chris Wilson
Cc: Anna Karas
Cc: Tvrtko Ursulin
Reviewed-by: Matthew Auld
---
.../i915/gem/selftests/i915_gem_object_blt.c | 15 +-
driv
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Protect context while grabbing
its name for the request
URL : https://patchwork.freedesktop.org/series/69292/
State : failure
== Summary ==
Applying: drm/i915: Protect context while grabbing its name for the request
Using in
== Series Details ==
Series: Add support for mipi dsi cmd mode
URL : https://patchwork.freedesktop.org/series/69290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15214
Summary
---
**SUCCESS**
No
On 11/11/2019 16:58, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-11-11 16:48:14)
On 08/11/2019 20:49, Chris Wilson wrote:
Register a userspace fault handler for a memory region that we also pass
to the GPU via userptr, and make sure the pagefault is properly serviced
before we execute.
As the memory regions are setup early, we can rely on its existence as
we takeover the HW settings from BIOS.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/
> From: Tomas Janousek
> Sent: Sunday, November 10, 2019 3:11 AM
> To: Hiatt, Don
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/guc: Add GuC method to determine if
> submission is active.
>
> On Wed, Nov 06, 2019 at 09:40:02AM -0800, don.hi...@intel.com wrote:
> > A
On Mon, 11 Nov 2019 at 17:58, Chris Wilson wrote:
>
> As the memory regions are setup early, we can rely on its existence as
> we takeover the HW settings from BIOS.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
Inte
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise parallel
blit operations on a single ctx
URL : https://patchwork.freedesktop.org/series/69295/
State : failure
== Summary ==
Applying: drm/i915/selftests: Exercise parallel blit operations on a single ctx
Quoting Tvrtko Ursulin (2019-11-11 17:54:27)
>
> On 11/11/2019 16:58, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-11-11 16:48:14)
> >>
> >> On 08/11/2019 20:49, Chris Wilson wrote:
> >>> Register a userspace fault handler for a memory region that we also pass
> >>> to the GPU via userptr,
== Series Details ==
Series: series starting with [1/3] dma_resv: prime lockdep annotations (rev2)
URL : https://patchwork.freedesktop.org/series/68958/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
87afb1ee808f dma_resv: prime lockdep annotations
-:106: WARNING:COMMIT_LOG_LONG
Pass around the intended intel_uncore for mmio access during stolen
setup, and avoid relying on the implicit magic I915_READ() macros.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 207 +++--
1 file changed, 109 insertions(+), 98 d
As the memory regions are setup early, we can rely on its existence as
we takeover the HW settings from BIOS.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 22 ++
1 file changed, 10 insertions(+), 12
== Series Details ==
Series: series starting with [FIXES,1/3] drm/i915/userptr: Try to acquire the
page lock around set_page_dirty()
URL : https://patchwork.freedesktop.org/series/69296/
State : failure
== Summary ==
Applying: drm/i915/userptr: Try to acquire the page lock around set_page_dir
On Mon, 11 Nov 2019 at 18:22, Chris Wilson wrote:
>
> Pass around the intended intel_uncore for mmio access during stolen
> setup, and avoid relying on the implicit magic I915_READ() macros.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev3)
URL : https://patchwork.freedesktop.org/series/68824/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
126d741bd371 drm/i915/selftests: Perform some basic cycle counting of MI ops
-
== Series Details ==
Series: drm/i915/gt: Try an extra flush on the Haswell blitter
URL : https://patchwork.freedesktop.org/series/69293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15216
Summary
---
== Series Details ==
Series: series starting with [1/3] dma_resv: prime lockdep annotations (rev2)
URL : https://patchwork.freedesktop.org/series/68958/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15218
== Series Details ==
Series: drm/i915/gem: Pass mem region to preallocated stolen
URL : https://patchwork.freedesktop.org/series/69308/
State : failure
== Summary ==
Applying: drm/i915/gem: Pass mem region to preallocated stolen
error: sha1 information is lacking or useless
(drivers/gpu/drm/i
The bspec was just updated with a couple corrections to the TGL MOCS
table. Entries 16 and 17 are marked as reserved (overriding the value
we inherit from GEN11_MOCS_ENTRIES) and entry 61 shouldn't have the
LE_SCF bit applied.
Note that since we're intentionally/explicitly overriding table entrie
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev3)
URL : https://patchwork.freedesktop.org/series/68824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15220
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Replace implicit
dev_priv->uncore for stolen init
URL : https://patchwork.freedesktop.org/series/69310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15222
== Series Details ==
Series: drm/i915: do not warn late about hdmi on port A (rev2)
URL : https://patchwork.freedesktop.org/series/69226/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15223
Summary
---
On Mon, Nov 11, 2019 at 11:07:21AM -0800, Matt Roper wrote:
The bspec was just updated with a couple corrections to the TGL MOCS
table. Entries 16 and 17 are marked as reserved (overriding the value
we inherit from GEN11_MOCS_ENTRIES) and entry 61 shouldn't have the
LE_SCF bit applied.
Note tha
== Series Details ==
Series: drm/i915/tgl: MOCS table fixes
URL : https://patchwork.freedesktop.org/series/69312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7311 -> Patchwork_15224
Summary
---
**SUCCESS**
No re
When we call intel_dsb_get(), the dsb initialization may fail for
various reasons. We already log the error message in that path, making
it unnecessary to trigger a warning that refcount == 0 when calling
intel_dsb_put().
So here we simplify the logic and do lazy shutdown: leaving the extra
refcou
The current dsb API is not really prepared to handle multithread access.
I was debugging an issue that ended up fixed by commit a096883dda2c
("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA") and was
puzzled how these atomic operations were guaranteeing atomicity.
if (atomic_add
I was debugging a problem that got fixed by a096883dda2c ("drm/i915/dsb:
Remove PIN_MAPPABLE from the DSB object VMA"). While that specific
problem is already fixed, others may pop up in future. This series
is tested by temporarily reverting that commit and ensuring we have
only a error message in
On Mon, Nov 11, 2019 at 12:37:30PM -0800, Lucas De Marchi wrote:
> On Mon, Nov 11, 2019 at 11:07:21AM -0800, Matt Roper wrote:
> > The bspec was just updated with a couple corrections to the TGL MOCS
> > table. Entries 16 and 17 are marked as reserved (overriding the value
> > we inherit from GEN1
The bspec was just updated with a couple corrections to the TGL MOCS
table. Entries 16 and 17 are marked as reserved (overriding the value
we inherit from GEN11_MOCS_ENTRIES) and entry 61 shouldn't have the
LE_SCF bit applied.
Note that since we're intentionally/explicitly overriding table entrie
SAMPLE_OA_REPORT enables sampling of OA reports from the OA buffer.
Since reports from OA buffer had system wide visibility, collecting
samples from the OA buffer was a privileged operation on previous
platforms. Prior to TGL, it was also necessary to sample the OA buffer
to normalize reports from
Gen12 supports saving/restoring render counters per context. Apply OAR
configuration only for the context that is passed in to perf.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 203 ++-
1 file changed, 118 insertions(+), 85 deletions(-)
== Series Details ==
Series: Improve error handling on DSB
URL : https://patchwork.freedesktop.org/series/69319/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7311 -> Patchwork_15225
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915/tgl: MOCS table fixes (rev2)
URL : https://patchwork.freedesktop.org/series/69312/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c5d7cbe58b9 drm/i915/tgl: MOCS table fixes
-:72: CHECK:LINE_SPACING: Please use a blank line after
function/s
== Series Details ==
Series: drm/i915/tgl: MOCS table fixes (rev2)
URL : https://patchwork.freedesktop.org/series/69312/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: MOCS table fixes
-
+drivers/gpu/drm/i915/gt/intel_mocs.c:255:9: warnin
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Allow non-privileged access
when OA buffer is not sampled
URL : https://patchwork.freedesktop.org/series/69321/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3b64a508eefb drm/i915/perf: Allow non-privileged
== Series Details ==
Series: drm/i915/tgl: MOCS table fixes (rev2)
URL : https://patchwork.freedesktop.org/series/69312/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7311 -> Patchwork_15226
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Allow non-privileged access
when OA buffer is not sampled
URL : https://patchwork.freedesktop.org/series/69321/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7311 -> Patchwork_15227
===
On Thu, Nov 07, 2019 at 05:30:36PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark
On Thu, Nov 07, 2019 at 05:30:37PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case)
== Series Details ==
Series: drm/i915/tgl: Do not read the transcoder register for mipi dsi
URL : https://patchwork.freedesktop.org/series/69288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7309_full -> Patchwork_15212_full
===
== Series Details ==
Series: Add support for mipi dsi cmd mode
URL : https://patchwork.freedesktop.org/series/69290/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15214_full
Summary
---
**FAILU
Hi,
Here's one GVT dmabuf reference drop fix from Pan Bian.
Thanks
--
The following changes since commit ee2c5ef8a9d640ee1617ec97b84fe2f634284e51:
drm/i915/dp: Do not switch aux to TBT mode for non-TC ports (2019-11-04
13:24:14 -0800)
are available in the Git repository at:
https://githu
Hi,
Here's one fix to remove PVINFO read in initial state for extra
warning messages in debug.
Thanks
--
The following changes since commit d9dace9438945e7c13d91e62927c5c6c88a37ee5:
drm/i915/selftests: Add intel_gt_suspend_prepare (2019-11-05 16:06:25 +0200)
are available in the Git reposito
== Series Details ==
Series: drm/i915/gt: Try an extra flush on the Haswell blitter
URL : https://patchwork.freedesktop.org/series/69293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15216_full
Summa
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev3)
URL : https://patchwork.freedesktop.org/series/68824/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15220_full
===
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Replace implicit
dev_priv->uncore for stolen init
URL : https://patchwork.freedesktop.org/series/69310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15222_full
==
== Series Details ==
Series: drm/i915/execlists: Move reset_active() from schedule-out to schedule-in
URL : https://patchwork.freedesktop.org/series/69247/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15204_full
=
On 09/11/2019 10:53, Chris Wilson wrote:
We report "frequencies" (actual-frequency, requested-frequency) as the
number of accumulated cycles so that the average frequency over that
period may be determined by the user. This means the units we report to
the user are Mcycles (or just M), not MHz.
On 10/11/2019 19:14, Umesh Nerlige Ramappa wrote:
On Fri, Nov 08, 2019 at 09:22:00AM +0200, Lionel Landwerlin wrote:
On 08/11/2019 01:34, Umesh Nerlige Ramappa wrote:
It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit.
Quoting Tvrtko Ursulin (2019-11-11 09:11:03)
>
> On 09/11/2019 10:53, Chris Wilson wrote:
> > We report "frequencies" (actual-frequency, requested-frequency) as the
> > number of accumulated cycles so that the average frequency over that
> > period may be determined by the user. This means the uni
The ordering of the checks in the existing code can lead to holding
preemption not being considered as privileged op.
Signed-off-by: Lionel Landwerlin
Fixes: 9cd20ef7803c ("drm/i915/perf: allow holding preemption on filtered ctx")
---
drivers/gpu/drm/i915/i915_perf.c | 20 ++--
1
Quoting Lionel Landwerlin (2019-11-11 09:53:08)
> The ordering of the checks in the existing code can lead to holding
> preemption not being considered as privileged op.
>
> Signed-off-by: Lionel Landwerlin
> Fixes: 9cd20ef7803c ("drm/i915/perf: allow holding preemption on filtered
> ctx")
Oops
On 11/11/2019 12:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-11-11 09:53:08)
The ordering of the checks in the existing code can lead to holding
preemption not being considered as privileged op.
Signed-off-by: Lionel Landwerlin
Fixes: 9cd20ef7803c ("drm/i915/perf: allow holding pre
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 15f8297dc34e..9a1c64d8b778 100644
--- a/drivers/gpu/d
Chris Wilson writes:
> Inside print_request(), we query the context/timeline name. Nothing
> immediately protects the context from being freed if the request is
> complete -- we rely on serialisation by the caller to keep the name
> valid until they finish using it. Inside intel_engine_dump(), we
Chris Wilson writes:
> We mention that we are resetting the GPU, and dump the device state for
> post mortem debugging. However, while that dump contains the active
> processes and the one flagged as causing the error, we do not always
> include that information in dmesg. Include the name of the
On 11/11/2019 09:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-11-11 09:11:03)
On 09/11/2019 10:53, Chris Wilson wrote:
We report "frequencies" (actual-frequency, requested-frequency) as the
number of accumulated cycles so that the average frequency over that
period may be determined b
Chris Wilson writes:
> Update the context.name on closing so that the persistent requests are
> clear in debug prints.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm
On Sat, Nov 09, 2019 at 03:10:02PM +, Chris Wilson wrote:
> igt_aux.h already provides the optimal igt_fls(), so use that in
> preference to open coding the brute force version.
>
> Reported-by: Stuart Summers
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
Reviewed-by: Arkadiusz Hiler
Quoting Mika Kuoppala (2019-11-11 10:25:00)
> Chris Wilson writes:
>
> > Inside print_request(), we query the context/timeline name. Nothing
> > immediately protects the context from being freed if the request is
> > complete -- we rely on serialisation by the caller to keep the name
> > valid un
Quoting Mika Kuoppala (2019-11-11 10:25:00)
> Chris Wilson writes:
>
> > Inside print_request(), we query the context/timeline name. Nothing
> > immediately protects the context from being freed if the request is
> > complete -- we rely on serialisation by the caller to keep the name
> > valid un
Chris Wilson writes:
> If we detect a hang in a closed context, just flush all of its requests
> and cancel any remaining execution along the context. Note that after
> closing the context, the last reference to the context may be dropped,
> leaving it only valid under RCU.
Sound good. But is th
Quoting Mika Kuoppala (2019-11-11 10:47:00)
> Chris Wilson writes:
>
> > Update the context.name on closing so that the persistent requests are
> > clear in debug prints.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 18 ++
> > 1 f
Chris Wilson writes:
> After doing some measuring, Icelake behaves on a par with Broadwell, and
> without having to compromise for low power cores with long latencies, we
> can reduce the powergating hysteresis so that the powersaving is enabled
> faster. No impact observed on client side through
Quoting Mika Kuoppala (2019-11-11 10:54:14)
> Chris Wilson writes:
>
> > If we detect a hang in a closed context, just flush all of its requests
> > and cancel any remaining execution along the context. Note that after
> > closing the context, the last reference to the context may be dropped,
> >
On Fri, 08 Nov 2019, Lucas De Marchi wrote:
> On Fri, Nov 08, 2019 at 01:14:03PM +0200, Jani Nikula wrote:
>>Follow-up: store pointer to the oprom vbt somewhere under i915->vbt, and
>>have debugfs i915_vbt() handle that properly.
>
> I don't think this is needed. The thing I'm doing here is the sa
Chris Wilson writes:
> Use a small char buffer inside the i915_gem_context to store the user
> friendly name so that ctx->name has the same lifetime as the RCU
> protected GEM context. That is, e.g. when using print_request() that
> prints the timeline name (ctx->name), the name will not be prema
As per the Bspec the port mapping is fixed for mipi dsi
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/intel_display.c | 27
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-11-11 10:54:14)
>> Chris Wilson writes:
>>
>> > If we detect a hang in a closed context, just flush all of its requests
>> > and cancel any remaining execution along the context. Note that after
>> > closing the context, the last reference to t
Chris Wilson writes:
> We mention that we are resetting the GPU, and dump the device state for
> post mortem debugging. However, while that dump contains the active
> processes and the one flagged as causing the error, we do not always
> include that information in dmesg. Include the name of the
Inside print_request(), we query the context/timeline name. Nothing
immediately protects the context from being freed if the request is
complete -- we rely on serialisation by the caller to keep the name
valid until they finish using it. Inside intel_engine_dump(), we
generally only print the reque
Use a small char buffer inside the i915_gem_context to store the user
friendly name so that ctx->name has the same lifetime as the RCU
protected GEM context. That is, e.g. when using print_request() that
prints the timeline name (ctx->name), the name will not be prematurely
freed upon the context b
Update the context.name on closing so that the persistent requests are
clear in debug prints.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i
We mention that we are resetting the GPU, and dump the device state for
post mortem debugging. However, while that dump contains the active
processes and the one flagged as causing the error, we do not always
include that information in dmesg. Include the name of the guilty
process in dmesg for ref
== Series Details ==
Series: drm/i915: Protect context while grabbing its name for the request
URL : https://patchwork.freedesktop.org/series/69249/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15205_full
Fixed the comments on version1 RFC, basically fixing the
challenge on getting access to mipi dsi attributes like
is command mode enabled, and what should be the port for
reading TE and doing a frame update.
Thanks to Jani and Ville for their inputs on this.
Vandita Kulkarni (9):
drm/i915/dsi: De
In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_irq.c | 62 +
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_i
Adding all the register definitions needed
for mipi dsi command mode.
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_reg.h | 78 +
1 file changed, 70 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i91
If the GOP has programmed periodic command mode,
we need to disable that which would need a
deconfigure and configure sequence.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i
Transcoder timing calculation differ for command mode.
v2: Use is_vid_mode, and use same I915_WRITE (Jani)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 39 +-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/
We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_irq.c | 58 +++--
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_i
We cannot control how long RCU takes to find a quiescent point as that
depends upon the background load and so may take an arbitrary time.
Instead, let's try to avoid that impacting our measurements by inserting
an rcu_barrier() before our critical timing sections and hope that hides
the issue, let
Adding TE flags and periodic command mode flags
as part of private flags to indicate what TE interrupts
we would be getting instead of vblanks in case of mipi dsi
command mode.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
1 file changed, 6 in
On dsi cmd mode we do not receive vblanks instead
we would get TE and these flags indicate TE is expected on
which port.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/ic
In TE Gate mode, on every flip we need to set the
frame update request bit. After this bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 22
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