== Series Details ==
Series: series starting with [v2,1/2] drm/i915/tgl: Wa_1606679103 (rev3)
URL : https://patchwork.freedesktop.org/series/69420/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7346_full -> Patchwork_15269_full
=
== Series Details ==
Series: Improve error handling on DSB (rev3)
URL : https://patchwork.freedesktop.org/series/69319/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15303
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [1/3] drm/i915/bios: do not discard address space
URL : https://patchwork.freedesktop.org/series/69567/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15302
== Series Details ==
Series: drm/amdgpu/dm: Do not throw an error for a display with no audio
URL : https://patchwork.freedesktop.org/series/69492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7346_full -> Patchwork_15268_full
=
== Series Details ==
Series: series starting with [1/3] drm/i915/bios: do not discard address space
URL : https://patchwork.freedesktop.org/series/69567/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/bios: do not discard address space
Okay!
The current dsb API is not really prepared to handle multithread access.
I was debugging an issue that ended up fixed by commit a096883dda2c
("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA") and was
puzzled how these atomic operations were guaranteeing atomicity.
if (atomic_add
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission (rev5)
URL : https://patchwork.freedesktop.org/series/68685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15301
===
== Series Details ==
Series: VBT "generic DTD" block (rev3)
URL : https://patchwork.freedesktop.org/series/69481/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15300
Summary
---
**SUCCESS**
No re
== Series Details ==
Series: drm/i915/mst: Check uapi enable not intel one during mst atomic check
URL : https://patchwork.freedesktop.org/series/69557/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15299
The unaligned ioread32() will make us read byte by byte looking for the
vbt. We could just as well have done a ioread8() + a shift and avoid the
extra confusion on how we are looking for "$VBT".
However when using ACPI it's guaranteed the VBT is 4-byte aligned
per spec, so we can probably assume i
When we map the VBT through pci_map_rom() we may not be allowed
to simply discard the address space and go on reading the memory.
That doesn't work on my test system, but by dumping the rom via
sysfs I can can get the correct vbt. So change our find_vbt() to do
the same as done by pci_read_rom(), i
We don't need to keep the pci rom mapped during the entire
intel_bios_init() anymore. Move it to the previous copy_vbt() function
and rename it to oprom_get_vbt() since now it's responsible to to all
operations related to get the vbt from the oprom.
Signed-off-by: Lucas De Marchi
---
drivers/gpu
== Series Details ==
Series: drm/i915/irq: Disable display interrupt control during handler on gen11+
URL : https://patchwork.freedesktop.org/series/69556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15298
===
On Fri, Nov 15, 2019 at 10:31:06PM +, Patchwork wrote:
> == Series Details ==
>
> Series: VBT "generic DTD" block
> URL : https://patchwork.freedesktop.org/series/69481/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7345_full -> Patchwork_15264_full
> ===
== Series Details ==
Series: drm: Random pile of core stuff
URL : https://patchwork.freedesktop.org/series/69554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7357 -> Patchwork_15297
Summary
---
**SUCCESS**
No re
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the GuC suspend/resume entirely as we do
not need to
> From: Ceraolo Spurio, Daniele
> Sent: Friday, November 15, 2019 3:10 PM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Cc: Ewins, Jon ; KiteStramuort
> ; S . Zharkoff ;
> Wajdeczko, Michal ; Summers, Stuart
> ; Chris Wilson ; Tomas
> Janousek
> Subject: Re: [PATCH] drm/i915/guc: Skip susp
On 11/15/2019 2:22 PM, Hiatt, Don wrote:
From: Ceraolo Spurio, Daniele
Sent: Friday, November 15, 2019 2:02 PM
To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
Cc: Ewins, Jon ; KiteStramuort
; S . Zharkoff ;
Wajdeczko, Michal ; Summers, Stuart
; Chris Wilson ; Tomas
Janousek
Subject: Re: [P
On Fri, Nov 15, 2019 at 12:52:49PM -0800, Matt Roper wrote:
On Mon, Nov 11, 2019 at 12:50:25PM -0800, Lucas De Marchi wrote:
When we call intel_dsb_get(), the dsb initialization may fail for
various reasons. We already log the error message in that path, making
it unnecessary to trigger a warnin
On Fri, Nov 15, 2019 at 11:09:43PM +0200, Ville Syrjälä wrote:
On Fri, Nov 15, 2019 at 12:29:38PM -0800, Matt Roper wrote:
On Mon, Nov 11, 2019 at 12:50:24PM -0800, Lucas De Marchi wrote:
> The current dsb API is not really prepared to handle multithread access.
> I was debugging an issue that e
== Series Details ==
Series: drm: Random pile of core stuff
URL : https://patchwork.freedesktop.org/series/69554/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef6f78a9b185 drm: Move page_flip fb lookup earlier
053159ad20d8 drm: Allocate the page flip event earlier
a3d996b446f7
== Series Details ==
Series: drm/i915/selftests: Autotune timeouts
URL : https://patchwork.freedesktop.org/series/69553/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR d
== Series Details ==
Series: VBT "generic DTD" block
URL : https://patchwork.freedesktop.org/series/69481/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7345_full -> Patchwork_15264_full
Summary
---
**FAILURE**
Se
> From: Ceraolo Spurio, Daniele
> Sent: Friday, November 15, 2019 2:02 PM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Cc: Ewins, Jon ; KiteStramuort
> ; S . Zharkoff ;
> Wajdeczko, Michal ; Summers, Stuart
> ; Chris Wilson ; Tomas
> Janousek
> Subject: Re: [PATCH] drm/i915/guc: Skip su
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission (rev4)
URL : https://patchwork.freedesktop.org/series/68685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15295
===
On 11/15/19 10:20 AM, don.hi...@intel.com wrote:
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove
== Series Details ==
Series: drm/i915/gem: Purge the sudden reappearance of i915_gem_object_pin()
(rev4)
URL : https://patchwork.freedesktop.org/series/69524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15293
===
On Fri, Nov 15, 2019 at 09:12:57PM +, Patchwork wrote:
> == Series Details ==
>
> Series: VBT "generic DTD" block (rev2)
> URL : https://patchwork.freedesktop.org/series/69481/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15292
> ==
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev2)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
Applying: drm/i915: Change intel_encoders_() calling convention
Applying: drm/i915: Add intel_crtc_vblank_off()
Applying: drm
On Fri, 2019-11-15 at 23:11 +0200, Ville Syrjälä wrote:
> On Fri, Nov 15, 2019 at 03:54:17PM -0500, Lyude Paul wrote:
> > On Fri, 2019-11-15 at 22:25 +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 15, 2019 at 12:04:30PM -0800, José Roberto de Souza wrote:
> > > > When the connector has VCPI allocate
== Series Details ==
Series: VBT "generic DTD" block (rev2)
URL : https://patchwork.freedesktop.org/series/69481/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15292
Summary
---
**FAILURE**
Serio
On Fri, Nov 15, 2019 at 03:54:17PM -0500, Lyude Paul wrote:
> On Fri, 2019-11-15 at 22:25 +0200, Ville Syrjälä wrote:
> > On Fri, Nov 15, 2019 at 12:04:30PM -0800, José Roberto de Souza wrote:
> > > When the connector has VCPI allocated and is being moved to another
> > > pipe it causes drm_dp_atom
On Fri, Nov 15, 2019 at 12:29:38PM -0800, Matt Roper wrote:
> On Mon, Nov 11, 2019 at 12:50:24PM -0800, Lucas De Marchi wrote:
> > The current dsb API is not really prepared to handle multithread access.
> > I was debugging an issue that ended up fixed by commit a096883dda2c
> > ("drm/i915/dsb: Rem
On Thu, Nov 14, 2019 at 01:50:46PM -0800, Radhakrishna Sripada wrote:
> Disable VS Unit Clockgating.
>
> v2: Fix VSUNIT instead of VFUNIT(Ville)
The VSUNIT bit (bit 3) isn't supposed to exist on gen12 according to the
bspec. However there's a separate programming note indicating that the
(suppos
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/69546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15291
On Fri, 2019-11-15 at 22:25 +0200, Ville Syrjälä wrote:
> On Fri, Nov 15, 2019 at 12:04:30PM -0800, José Roberto de Souza wrote:
> > When the connector has VCPI allocated and is being moved to another
> > pipe it causes drm_dp_atomic_release_vcpi_slots() and
> > drm_dp_atomic_find_vcpi_slots() to b
On Mon, Nov 11, 2019 at 12:50:25PM -0800, Lucas De Marchi wrote:
> When we call intel_dsb_get(), the dsb initialization may fail for
> various reasons. We already log the error message in that path, making
> it unnecessary to trigger a warning that refcount == 0 when calling
> intel_dsb_put().
>
>
On Mon, Nov 11, 2019 at 12:50:24PM -0800, Lucas De Marchi wrote:
> The current dsb API is not really prepared to handle multithread access.
> I was debugging an issue that ended up fixed by commit a096883dda2c
> ("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA") and was
> puzzled how the
On Fri, Nov 15, 2019 at 12:04:30PM -0800, José Roberto de Souza wrote:
> When the connector has VCPI allocated and is being moved to another
> pipe it causes drm_dp_atomic_release_vcpi_slots() and
> drm_dp_atomic_find_vcpi_slots() to be called in the same atomic check
> causing the error bellow.
>
On Thu, Nov 14, 2019 at 02:24:49PM +0200, Stanislav Lisovskiy wrote:
> Also implemented algorithm for choosing DBuf slice configuration
> based on active pipes, pipe ratio as stated in BSpec 12716.
>
> Now pipe allocation still stays proportional to pipe width as before,
> however within allowed D
== Series Details ==
Series: drm/i915/gem: Exercise the per-batch whitelist from the context (rev2)
URL : https://patchwork.freedesktop.org/series/69527/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15290
Reviewed-by: Lyude Paul
On Fri, 2019-11-15 at 12:04 -0800, José Roberto de Souza wrote:
> When the connector has VCPI allocated and is being moved to another
> pipe it causes drm_dp_atomic_release_vcpi_slots() and
> drm_dp_atomic_find_vcpi_slots() to be called in the same atomic check
> causing t
When the connector has VCPI allocated and is being moved to another
pipe it causes drm_dp_atomic_release_vcpi_slots() and
drm_dp_atomic_find_vcpi_slots() to be called in the same atomic check
causing the error bellow.
This happens because at this point Intel's hw.enable(and all other
flags in the s
The gen12 bspec indicates we should disable display interrupts via
DISPLAY_INT_CTL during the display interrupt handler and re-enable them
again at the end. This isn't technically required on gen11, but is
still safe (confirmed internally with hardware architects).
Bspec: 49212
Cc: Aditya Swarup
== Series Details ==
Series: SNA: fix PRIME output support since xserver 1.20 (rev2)
URL : https://patchwork.freedesktop.org/series/48140/
State : failure
== Summary ==
Applying: SNA: fix PRIME output support since xserver 1.20
error: sha1 information is lacking or useless (src/sna/sna_accel.c
From: Ville Syrjälä
Currently setplane grabs all modeset locks, which seems a bit
excessive. Let's reduce that to just the locks we really need
on atomic drivers. For non-atomic drivers let's stick to the
current scheme for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_plane.c | 56
From: Ville Syrjälä
I found this random pile of stuff lying around. Dusted it off
and tossed in the new selftests.
Ville Syrjälä (7):
drm: Move page_flip fb lookup earlier
drm: Allocate the page flip event earlier
drm: Extract page_flip_{internal,atomic}()
drm: Simplify the setplane old_
From: Ville Syrjälä
No reason that I can see to delay the fb lookup this late. Moving it
earlier allows us to keep it outside of the lock retry loop. This
makes error handling and whatnot simpler.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_plane.c | 29 +++--
From: Ville Syrjälä
Can't see why we need to delay the page flip event allocation until the
last moment. Move it earlier to simplify error handling.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_plane.c | 45 +++--
1 file changed, 23 insertions(+), 22 del
From: Ville Syrjälä
Yank out the code for the plane->fb/old_fb/crtc handling from
the page flip path into page_flip_internal(), and provide a
simpler variant for atomic drivers.
We'll also move the fb vs. src viewport checks into the new
functions as they are slightly different between the two p
From: Ville Syrjälä
Test the basics of drm_atomic_set_mode_for_crtc(), and in particular
verify that the function doesn't take the shortcut incorrectly.
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/selftests/Makefile| 3 +-
.../gpu/drm/selftests/drm_modeset
From: Ville Syrjälä
The early return in drm_atomic_set_mode_for_crtc() isn't quite
right. It would mistakenly return and fail to update
crtc_state->enable if someone actually tried to set a zeroed
mode on a currently disabled crtc. That should never actually
happen in response to any userspace re
From: Ville Syrjälä
Instead of doing the things in a convoluted way with the failure and
success paths mixed up let's just clear old_fb when we encounter an
error and bail out immediately. We already did this for the pageflip
path.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_plane.c |
== Series Details ==
Series: DP Phy compliace auto test
URL : https://patchwork.freedesktop.org/series/69541/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/
On Fri, Nov 15, 2019 at 10:18:26AM +0100, Daniel Vetter wrote:
> On Fri, Nov 15, 2019 at 10:04 AM Jean Delvare wrote:
> >
> > Hi Chris,
> >
> > On Thu, 14 Nov 2019 20:44:13 +, Chris Wilson wrote:
> > > An old display with no audio may not have an EDID with a CEA block, or
> > > it may simply b
== Series Details ==
Series: drm/i915/dsi: enable DSC
URL : https://patchwork.freedesktop.org/series/69540/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7354 -> Patchwork_15287
Summary
---
**SUCCESS**
No regressi
Quoting Chris Wilson (2019-11-15 18:41:56)
> +unsigned long igt_request_timeout(struct intel_engine_cs *engine,
> + unsigned int factor)
> +{
> + unsigned long base;
> +
> + if (is_power_of_2(engine->mask)) {
> + base = ewma_delay_read(&engi
Not all HW is made equal, and so one timeout for a test on one may fail
on another. Now that we measure a baseline for the latency of an engine,
we can provide a more precise estimate for how long a test will run and
after applying some safety factors, provide an accurate timeout for the
test.
Sig
== Series Details ==
Series: drm/i915/dsi: enable DSC
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dc583bcee91e drm/i915/bios: pass devdata to parse_ddi_port
b567762a0b2a drm/i915/bios: parse compression parameters block
-:
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the GuC suspend/resume entirely as we do
not need to
On Fri, Nov 15, 2019 at 04:32:47PM +0100, Peter Wu wrote:
> Since "Make PixmapDirtyUpdateRec::src a DrawablePtr" in xserver, the
> "src" pointer might point to the root window (created by the server)
> instead of a pixmap (as created by xf86-video-intel). Use
> get_drawable_pixmap to handle both ca
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Flush retire.work timer object
on unload
URL : https://patchwork.freedesktop.org/series/69536/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7353 -> Patchwork_15286
==
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev11)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7353 -> Patchwork_15285
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [01/11] HAX to make DSC work on the icelake test
system
URL : https://patchwork.freedesktop.org/series/69478/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7344_full -> Patchwork_15263_full
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Flush retire.work timer object
on unload
URL : https://patchwork.freedesktop.org/series/69536/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
94cbdef4257c drm/i915/selftests: Disable heartbeat around context b
On Fri, Nov 15, 2019 at 07:40:15PM +0200, Ville Syrjälä wrote:
On Fri, Nov 08, 2019 at 01:13:53PM -0800, Lucas De Marchi wrote:
When we map the VBT through pci_map_rom() we may not be allowed
to simply discard the address space and go on reading the memory.
That doesn't work on my test system, b
On Fri, Nov 08, 2019 at 01:13:53PM -0800, Lucas De Marchi wrote:
> When we map the VBT through pci_map_rom() we may not be allowed
> to simply discard the address space and go on reading the memory.
> That doesn't work on my test system, but by dumping the rom via
> sysfs I can can get the correct
Hi Stuart/Chris,
> From: Chris Wilson
> Sent: Friday, November 15, 2019 9:20 AM
> To: Hiatt, Don ; Summers, Stuart
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Skip suspend/resume GuC
> action on platforms w/o GuC submission
>
> Quoting Summers, Stuart
> From: Tomas Janousek
> Sent: Friday, November 15, 2019 9:29 AM
> To: Chris Wilson
> Cc: Hiatt, Don ; Summers, Stuart
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/i915/guc: Skip suspend/resume GuC action on
> platforms w/o GuC submission
>
> Don, Chris,
>
> Also, as men
Don, Chris,
On Fri, Nov 15, 2019 at 05:19:59PM +, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-11-15 17:12:58)
> > On Thu, 2019-11-14 at 17:11 -0800, don.hi...@intel.com wrote:
> > > From: Don Hiatt
> > >
> > > On some platforms (e.g. KBL) that do not support GuC submission, but
> > >
> From: Chris Wilson
> Sent: Friday, November 15, 2019 9:20 AM
> To: Hiatt, Don ; Summers, Stuart
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Skip suspend/resume GuC
> action on platforms w/o GuC submission
>
> Quoting Summers, Stuart (2019-11-15 17:
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev11)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:4419:27: wa
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev11)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1294bb4306ba drm/i915: Refactor intel_can_enable_sagv
-:254: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match
> From: Summers, Stuart
> Sent: Friday, November 15, 2019 9:13 AM
>
> On Thu, 2019-11-14 at 17:11 -0800, don.hi...@intel.com wrote:
> > From: Don Hiatt
> >
> > On some platforms (e.g. KBL) that do not support GuC submission, but
> > the user enabled the GuC communication (e.g for HuC authenticat
Quoting Summers, Stuart (2019-11-15 17:12:58)
> On Thu, 2019-11-14 at 17:11 -0800, don.hi...@intel.com wrote:
> > From: Don Hiatt
> >
> > On some platforms (e.g. KBL) that do not support GuC submission, but
> > the user enabled the GuC communication (e.g for HuC authentication)
> > calling the Gu
On Fri, Nov 15, 2019 at 04:08:45PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Intel-gfx On Behalf Of Ville
> >Syrjala
> >Sent: Thursday, October 24, 2019 5:52 PM
> >To: intel-gfx@lists.freedesktop.org
> >Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay
== Series Details ==
Series: series starting with [1/5] drm/i915/gt: Wait for new requests in
intel_gt_retire_requests() (rev2)
URL : https://patchwork.freedesktop.org/series/69497/
State : failure
== Summary ==
Applying: drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
Using
== Series Details ==
Series: drm/i915: Simplify NEEDS_WaRsDisableCoarsePowerGating
URL : https://patchwork.freedesktop.org/series/69529/
State : failure
== Summary ==
Applying: drm/i915: Simplify NEEDS_WaRsDisableCoarsePowerGating
error: sha1 information is lacking or useless (drivers/gpu/drm/
On Thu, 2019-11-14 at 17:11 -0800, don.hi...@intel.com wrote:
> From: Don Hiatt
>
> On some platforms (e.g. KBL) that do not support GuC submission, but
> the user enabled the GuC communication (e.g for HuC authentication)
> calling the GuC EXIT_S_STATE action results in lose of ability to
> ente
On Thu, Oct 24, 2019 at 03:21:37PM +0300, Ville Syrjälä wrote:
From: Ville Syrjälä
Add CHICKEN_TRANS definition for transcoder D.
Signed-off-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
1 file changed, 3 insertions(+), 1 del
On Thu, Oct 24, 2019 at 03:21:36PM +0300, Ville Syrjälä wrote:
From: Ville Syrjälä
Make CHICKEN_TRANS() a bit less special looking by using _PICK().
Signed-off-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
This died many years ago as we now use i915_vma first and foremost.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
Restore the flags | PIN_GLOBAL.
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 36 +++---
drivers/gpu/drm/i915/i91
== Series Details ==
Series: drm/i915/gt: Mention which device failed
URL : https://patchwork.freedesktop.org/series/69528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7352 -> Patchwork_15282
Summary
---
**SUCCESS*
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
old LFP panel mode data in block 42. Let's start parsing this block to
fill in the panel fixed mode on devices with a >=229 VBT.
v2:
* Update according to the recent updates:
- DTD size is now 16 bits instead of 24
- p
Newer VBT versions will add an alternate way to read panel DTD
information, so let's split parsing of the general panel information
from the timing data in preparation.
Cc: Jani Nikula
Signed-off-by: Matt Roper
Reviewed-by: Jesse Barnes
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/displa
VBT revision 229 introduces a new "Generic DTD" block to define monitor
timing information and deprecates the old LFP panel mode data we've been
using until now.
v5: Incorporate minor feedback from Jani. Both patches have r-b now, so
one more pass for CI.
Matt Roper (2):
drm/i915/vbt: Pars
Quoting Tvrtko Ursulin (2019-11-15 16:09:00)
>
> On 15/11/2019 15:08, Chris Wilson wrote:
> > We need to wait until the timer object is marked as deactivated before
> > unloading, so follow up our gentle cancel_delayed_work() with the
> > synchronous variant to ensure it is flushed off a remote cp
On 15/11/2019 15:08, Chris Wilson wrote:
As the heartbeat has the effect of flushing context barriers, this
interferes with the context barrier tests that are trying to observe
them directly. Disable the heartbeat so that the barriers are as
predictable as the test demands.
Signed-off-by: Chris
On 15/11/2019 15:08, Chris Wilson wrote:
We need to wait until the timer object is marked as deactivated before
unloading, so follow up our gentle cancel_delayed_work() with the
synchronous variant to ensure it is flushed off a remote cpu before we
mark the memory as freed.
Bugzilla: https://bu
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Thursday, October 24, 2019 5:52 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
>
>From: Ville Syrjälä
>
>Currently we're blindly poking at the
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
include/uapi
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen
Signed-off-by: Chris Wilson
Cc:
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 21 -
drivers/gpu/drm/i915/selftests/i915_active.c | 46 +
On Fri, Nov 15, 2019 at 04:32:47PM +0100, Peter Wu wrote:
> Since "Make PixmapDirtyUpdateRec::src a DrawablePtr" in xserver, the
> "src" pointer might point to the root window (created by the server)
> instead of a pixmap (as created by xf86-video-intel). Use
> get_drawable_pixmap to handle both ca
One does not lightly add a new hidden struct_mutex dependency deep within
the execbuf bowels! The immediate suspicion in seeing the whitelist
cached on the context, is that it is intended to be preserved between
batches, as the kernel is quite adept at caching small allocations
itself. But no, it's
== Series Details ==
Series: drm/i915/gem: Exercise the per-batch whitelist from the context
URL : https://patchwork.freedesktop.org/series/69527/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7352 -> Patchwork_15281
Summar
Since "Make PixmapDirtyUpdateRec::src a DrawablePtr" in xserver, the
"src" pointer might point to the root window (created by the server)
instead of a pixmap (as created by xf86-video-intel). Use
get_drawable_pixmap to handle both cases.
When built with -fsanitize=address, the following test on a
== Series Details ==
Series: drm/i915: Restore GT coarse power gating workaround
URL : https://patchwork.freedesktop.org/series/69477/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7344_full -> Patchwork_15262_full
Summary
On Tue, Nov 12, 2019 at 10:03 AM Daniel Vetter wrote:
>
> Hi all,
>
> Dave and me chatted about this last week on irc. Essentially we have:
>
> $ git grep SPDX.*GPL -- ':(glob)drivers/gpu/drm/*c'
> drivers/gpu/drm/drm_client.c:// SPDX-License-Identifier: GPL-2.0
> drivers/gpu/drm/drm_damage_helper
set pattern in DP_COMP_CTL.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a2b860cf3b93..df31278a1619
1 - 100 of 216 matches
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