Re: [Intel-gfx] [PATCH] drm/i915: Reduce nested prepare_remote_context() to a trylock

Quoting Chris Wilson (2019-11-26 06:55:21) > On context retiring, we may invoke the kernel_context to unpin this > context. Elsewhere, we may use the kernel_context to modify this > context. This currently leads to an AB-BA lock inversion, so we need to > back-off from the contended lock, and

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reduce nested prepare_remote_context() to a trylock

== Series Details == Series: drm/i915: Reduce nested prepare_remote_context() to a trylock URL : https://patchwork.freedesktop.org/series/70008/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15434 Summary

[Intel-gfx] [PATCH] drm/i915: Reduce nested prepare_remote_context() to a trylock

On context retiring, we may invoke the kernel_context to unpin this context. Elsewhere, we may use the kernel_context to modify this context. This currently leads to an AB-BA lock inversion, so we need to back-off from the contended lock, and repeat. Bugzilla:

[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_shared: Use a spinner to keep the fence alive while querying

Once the fence is retired, we discard its references to the context state, including its timeline name. So the timeline query is only accurate before being signaled, so keep the fence alive until after the query. Signed-off-by: Chris Wilson --- tests/i915/gem_ctx_shared.c | 32

[Intel-gfx] ✓ Fi.CI.BAT: success for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4) URL : https://patchwork.freedesktop.org/series/69980/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15433 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4) URL : https://patchwork.freedesktop.org/series/69980/ State : warning == Summary == $ dim checkpatch origin/drm-tip 529f5590d903 drm/i915: Get active pending request for given context ccb5ba29f346 drm/i915: set

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [V2,1/2] drm/edid: Add aspect ratios to HDMI 4K modes

== Series Details == Series: series starting with [V2,1/2] drm/edid: Add aspect ratios to HDMI 4K modes URL : https://patchwork.freedesktop.org/series/69993/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7418_full -> Patchwork_15428_full

[Intel-gfx] [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS.

[Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu

High resolution timer is used for predictive governor to control eu/slice/subslice based on workloads. param is provided to enable/disable/update timer configuration V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum

[Intel-gfx] [PATCH v6 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase.

[Intel-gfx] [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration

[Intel-gfx] ✓ Fi.CI.BAT: success for Dynamic EU configuration of Slice/Sub-slice/EU (rev3)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev3) URL : https://patchwork.freedesktop.org/series/69980/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15432 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev3)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev3) URL : https://patchwork.freedesktop.org/series/69980/ State : warning == Summary == $ dim checkpatch origin/drm-tip f552a3f6fc86 drm/i915: Get active pending request for given context 97da0e00344a drm/i915: set

[Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu

High resolution timer is used for predictive governor to control eu/slice/subslice based on workloads. param is provided to enable/disable/update timer configuration V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum

[Intel-gfx] [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration

[Intel-gfx] [PATCH v6 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase.

[Intel-gfx] [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Support more QGV points (rev4)

== Series Details == Series: drm/i915: Support more QGV points (rev4) URL : https://patchwork.freedesktop.org/series/69886/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7418_full -> Patchwork_15426_full Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context

== Series Details == Series: series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context URL : https://patchwork.freedesktop.org/series/69988/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7418_full -> Patchwork_15425_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+

== Series Details == Series: series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+ URL : https://patchwork.freedesktop.org/series/69982/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7418_full -> Patchwork_15423_full

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915/psr: Add bits per pixel limitation

== Series Details == Series: series starting with [v2,1/5] drm/i915/psr: Add bits per pixel limitation URL : https://patchwork.freedesktop.org/series/70002/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15431

[Intel-gfx] ✓ Fi.CI.BAT: success for Clear Color Support for TGL Render Decompression (rev10)

== Series Details == Series: Clear Color Support for TGL Render Decompression (rev10) URL : https://patchwork.freedesktop.org/series/66814/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15430 Summary

[Intel-gfx] [PATCH v2 2/5] drm/i915/psr: Refactor psr short pulse handler

eDP spec states that when sink enconters a problem that prevents it to keep PSR running it should set PSR status to internal error and set the reason why it happen to PSR_ERROR_STATUS but it is not how it was implemented. But also I don't want to change this behavior, who knows if there is a panel

[Intel-gfx] [PATCH v2 5/5] drm/i915/vbt: Parse power conservation features block

Since VBT 228 is from this block that PSR and other power saving features configuration should be read from. This new block have a DRRS field but block 40 is not obsolete and it have information about what DRRS mode is supported so not using the information on this new block. v2: Added

[Intel-gfx] [PATCH v2 4/5] drm/i915/psr: Check if sink PSR capability changed

eDP specification states that sink can have its PSR capability changed, I have never found any panel doing that but lets add that for completeness. For now it is not reading back the PSR capabilities and if possible re-enabling PSR, this will be added if a panel is found using this feature. Cc:

[Intel-gfx] [PATCH v2 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption

When this error happens sink link is not stable after the required FW_EXIT_LATENCY period so it will miss the selective update. As the other PSR errors, for now we are not trying to recover from it. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza ---

[Intel-gfx] [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation

PSR2 HW only support a limited number of bits per pixel, if mode has more than supported PSR2 should not be enabled. BSpec: 50422 BSpec: 7713 Cc: Gwan-gyeong Mun Cc: Matt Roper Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 11

Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

On Tue, 2019-11-12 at 23:56 +, Souza, Jose wrote: > On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote: > > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza > > wrote: > > > Since VBT 228 is from this block that PSR and other power saving > > > features configuration should be

Re: [Intel-gfx] [PATCH 05/15] drm/armada: Delete dma_buf->k(un)map implemenation

On Mon, Nov 25, 2019 at 10:44:43PM +0100, Daniel Vetter wrote: > On Mon, Nov 18, 2019 at 11:35:26AM +0100, Daniel Vetter wrote: > > It's a dummy anyway. > > > > Signed-off-by: Daniel Vetter > > Cc: Russell King > > I merged the entire series except this one and the final patch, sill > waiting

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev10)

== Series Details == Series: Clear Color Support for TGL Render Decompression (rev10) URL : https://patchwork.freedesktop.org/series/66814/ State : warning == Summary == $ dim checkpatch origin/drm-tip d2bc012f7c24 drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Intel-gfx] [PATCH v7 4/7] drm/i915/tgl: Gen-12 render decompression

From: Dhinakaran Pandiyan Gen-12 display decompression operates on Y-tiled compressed main surface. The CCS is linear and has 4 bits of metadata for each main surface cache line pair, a size ratio of 1:256. Gen-12 display decompression is incompatible with buffers compressed by earlier GPUs, so

[Intel-gfx] [PATCH v7 5/7] drm/i915: Extract framebufer CCS offset checks into a function

From: Dhinakaran Pandiyan intel_fill_fb_info() has grown quite large and wrapping the offset checks into a separate function makes the loop a bit easier to follow. Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 69

[Intel-gfx] [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression

From: Dhinakaran Pandiyan Gen-12 has a new compression format, add a new modifier to indicate that. Cc: Ville Syrjälä Cc: Matt Roper Cc: Nanley G Chery Cc: Jason Ekstrand Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Lucas De Marchi --- include/uapi/drm/drm_fourcc.h | 11 +++

[Intel-gfx] [PATCH v7 2/7] drm/i915: Use intel_tile_height() instead of re-implementing

From: Dhinakaran Pandiyan intel_tile_dims() computes tile height using size and width, when there is already a function to do just that - intel_tile_height() Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file

[Intel-gfx] [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix

[Intel-gfx] [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

From: Dhinakaran Pandiyan Easier to read if all the alignment changes are in one place and contained within a function. Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 31 ++-- 1 file changed, 16

[Intel-gfx] [PATCH v7 0/7] Clear Color Support for TGL Render Decompression

Support for Clear Color is contained in the last two patches submitted by Radhakrishna Sripada. The first 5 patches are currently undergoing review/revision changes. The first 5 patches are cherry-picked from the series https://patchwork.freedesktop.org/series/67078/ Expecting feedback for the

[Intel-gfx] [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

Render Decompression is supported with Y-Tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Additional Clear Color information is passed from the user-space through an offset in the GEM BO. Add a new modifier to identify and parse

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Force the state compute phase once to enable PSR

== Series Details == Series: drm/i915/display: Force the state compute phase once to enable PSR URL : https://patchwork.freedesktop.org/series/7/ State : success == Summary == CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15429

[Intel-gfx] [PATCH] drm/i915/display: Force the state compute phase once to enable PSR

Recent improvements in the state tracking in i915 caused PSR to not be enabled when reusing firmware/BIOS modeset, this is due to all initial commits returning ealier in intel_atomic_check() as needs_modeset() is always false. To fix that here forcing the state compute phase in CRTC that is

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame

== Series Details == Series: drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame URL : https://patchwork.freedesktop.org/series/69981/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7417_full -> Patchwork_15422_full

Re: [Intel-gfx] [PATCH] drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling

Hi Gaurav As we already talked, on upstream for now we do not want to recovery of PSR runtime errors, so not merging this patch. But if you want comments in this patch to merge in your kernel tree...I would change the commit title to: "Do not mark as sink as not reliable to PSR runtime errors"

Re: [Intel-gfx] [PATCH 05/15] drm/armada: Delete dma_buf->k(un)map implemenation

On Mon, Nov 18, 2019 at 11:35:26AM +0100, Daniel Vetter wrote: > It's a dummy anyway. > > Signed-off-by: Daniel Vetter > Cc: Russell King I merged the entire series except this one and the final patch, sill waiting a bit more for an ack on this perhaps. -Daniel > --- >

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Mon, Nov 25, 2019 at 11:33:27AM -0500, Jerome Glisse wrote: On Fri, Nov 22, 2019 at 11:33:12PM +, Jason Gunthorpe wrote: On Fri, Nov 22, 2019 at 12:57:27PM -0800, Niranjana Vishwanathapura wrote: [...] > +static int > +i915_range_fault(struct i915_svm *svm, struct hmm_range *range) >

Re: [Intel-gfx] [PATCH] Revert "drm/fbdev: Fallback to non tiled mode if all tiles not present"

On Mon, Nov 25, 2019 at 05:07:26PM +0200, Jani Nikula wrote: > On Sat, 23 Nov 2019, Uma Shankar wrote: > > This reverts commit f25c7a006cd1c07254780e3406e45cee4842b933. > > > > 2p2c display configuration blows up dmesg when one connector is > > disconnected, causing issues in CI. > > > > Below

Re: [Intel-gfx] [PATCH i-g-t 5/9] i915/gem_ctx_isolation: Check engine relative registers

Chris, I applied your patches and tested on DG1 hardware. This new code works well, except there are still two issues to this test (gem_ctx_isloation.c) 1. the test loops over all possible engines (..ccs0, ccs1, ccs2,). the legacy interface is used to check if an engine is

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: opregion: set opregion chpd value to indicate the driver handles hotplug

Hi all, On 22-11-2019 21:45, Patchwork wrote: == Series Details == Series: drm/i915: opregion: set opregion chpd value to indicate the driver handles hotplug URL : https://patchwork.freedesktop.org/series/69902/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7409 ->

Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_param: Keep the engine active while peeking at vm layout

On Sun, 2019-11-24 at 11:27 +, Chris Wilson wrote: > The implicit soft-pinning we use to probe the vm layout using > execbuf, > depends on the batch remaining active (not retired) between execbufs. > Naturally, if the background retire worker runs the batch is retired > and > the implicit

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [V2,1/2] drm/edid: Add aspect ratios to HDMI 4K modes

== Series Details == Series: series starting with [V2,1/2] drm/edid: Add aspect ratios to HDMI 4K modes URL : https://patchwork.freedesktop.org/series/69993/ State : success == Summary == CI Bug Log - changes from CI_DRM_7418 -> Patchwork_15428

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Default to more lenient force preempt timeout

== Series Details == Series: drm/i915: Default to more lenient force preempt timeout URL : https://patchwork.freedesktop.org/series/69992/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7418 -> Patchwork_15427 Summary

Re: [Intel-gfx] [PATCH 3/3] drm/i915/i915: assume vbt is 4-byte aligned into oprom

On Fri, Nov 22, 2019 at 03:55:32PM +0200, Ville Syrjälä wrote: On Thu, Nov 21, 2019 at 10:54:29AM -0800, Lucas De Marchi wrote: On Thu, Nov 21, 2019 at 03:09:03PM +0200, Jani Nikula wrote: >On Wed, 20 Nov 2019, Lucas De Marchi wrote: >> The unaligned ioread32() will make us read byte by byte

Re: [Intel-gfx] [PATCH 3/7] drm: Extract page_flip_{internal, atomic}()

On Mon, Nov 25, 2019 at 4:05 PM Ville Syrjälä wrote: > > On Mon, Nov 25, 2019 at 10:02:38AM +0100, Daniel Vetter wrote: > > On Fri, Nov 22, 2019 at 08:35:13PM +0200, Ville Syrjälä wrote: > > > On Tue, Nov 19, 2019 at 11:14:43AM +0100, Daniel Vetter wrote: > > > > On Fri, Nov 15, 2019 at

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Support more QGV points (rev4)

== Series Details == Series: drm/i915: Support more QGV points (rev4) URL : https://patchwork.freedesktop.org/series/69886/ State : success == Summary == CI Bug Log - changes from CI_DRM_7418 -> Patchwork_15426 Summary ---

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, Daniel, Here are a few lates fixes for drm-misc-fixes. Obviously, it's not going to make it into 5.4, but it'd be great if they were in the upcoming PR. Thanks! Maxime drm-misc-fixes-2019-11-25: - A fix for a memory leak in the dma-buf support - One in mcde DSI support that leads to

[Intel-gfx] [PATCH V2 2/2] drm/edid: Add alternate clock for SMPTE 4K

[Why] In hdmi_mode_alternate_clock(), it adds an exception for VIC 4 mode (4096x2160@24) due to there is no alternate clock defined for that mode in HDMI1.4b. But HDMI2.0 adds 23.98Hz for that mode. [How] Remove the exception v2: Adjust the comment description of hdmi_mode_alternate_clock() due

[Intel-gfx] [PATCH V2 1/2] drm/edid: Add aspect ratios to HDMI 4K modes

[Why] HDMI 2.0 adds aspect ratio attribute to distinguish different 4k modes. According to Appendix E of HDMI 2.0 spec, source should use VSIF to indicate video mode only when the mode is one defined in HDMI 1.4b 4K modes. Otherwise, use AVI infoframes to convey VIC. Current code doesn't take

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Support more QGV points (rev4)

== Series Details == Series: drm/i915: Support more QGV points (rev4) URL : https://patchwork.freedesktop.org/series/69886/ State : warning == Summary == $ dim checkpatch origin/drm-tip d993a329d475 drm/i915: Support more QGV points -:45: CHECK:BRACES: braces {} should be used on all arms of

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context

== Series Details == Series: series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context URL : https://patchwork.freedesktop.org/series/69988/ State : success == Summary == CI Bug Log - changes from CI_DRM_7418 -> Patchwork_15425

Re: [Intel-gfx] [RFC 03/13] drm/i915/svm: Runtime (RT) allocator support

On Mon, Nov 25, 2019 at 09:59:37AM +, Chris Wilson wrote: Quoting Niranjana Vishwanathapura (2019-11-22 20:57:24) Shared Virtual Memory (SVM) runtime allocator support allows binding a shared virtual address to a buffer object (BO) in the device page table through an ioctl call. The ioctl

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Mon, Nov 25, 2019 at 01:24:18PM +, Jason Gunthorpe wrote: On Sun, Nov 24, 2019 at 01:12:47PM -0800, Niranjan Vishwanathapura wrote: > > > Using a temporary range is the pattern from nouveau, is it really > > > necessary in this driver? > > > > Yah, not required. In my local build I

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context

== Series Details == Series: series starting with [1/2] drm/i915/gem: Excise the per-batch whitelist from the context URL : https://patchwork.freedesktop.org/series/69988/ State : warning == Summary == $ dim checkpatch origin/drm-tip b54dfcdb21c6 drm/i915/gem: Excise the per-batch whitelist

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Mon, Nov 25, 2019 at 01:24:18PM +, Jason Gunthorpe wrote: > On Sun, Nov 24, 2019 at 01:12:47PM -0800, Niranjan Vishwanathapura wrote: > > > > > > Using a temporary range is the pattern from nouveau, is it really > > > > > necessary in this driver? > > > > > > > > Yah, not required. In my

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Fri, Nov 22, 2019 at 11:33:12PM +, Jason Gunthorpe wrote: > On Fri, Nov 22, 2019 at 12:57:27PM -0800, Niranjana Vishwanathapura wrote: [...] > > +static int > > +i915_range_fault(struct i915_svm *svm, struct hmm_range *range) > > +{ > > + long ret; > > + > > + range->default_flags =

[Intel-gfx] [PATCH] drm/i915: Default to more lenient force preempt timeout

Based on a sampling of a number of benchmarks across platforms, by default opt for a more much lenient timeout so that we should not adversely affect existing clients. 640ms ought to be enough for anyone. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112169 Fixes: 3a7a92aba8fb

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev2)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev2) URL : https://patchwork.freedesktop.org/series/69980/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+

== Series Details == Series: series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+ URL : https://patchwork.freedesktop.org/series/69982/ State : success == Summary == CI Bug Log - changes from CI_DRM_7418 -> Patchwork_15423

[Intel-gfx] [PATCH v3] drm/i915: Support more QGV points

According to BSpec 53998, there is a mask of max 8 SAGV/QGV points we need to support. Bumping this up to keep the CI happy(currently preventing tests to run), until all SAGV changes land. v2: Fix second plane where QGV points were hardcoded as well. v3: Change the naming of

Re: [Intel-gfx] [PATCH v2] drm/i915: Support more QGV points

On Mon, 2019-11-25 at 16:03 +, Saarinen, Jani wrote: > Hi, > > > -Original Message- > > From: Lisovskiy, Stanislav > > Sent: maanantai 25. marraskuuta 2019 17.55 > > To: ville.syrj...@linux.intel.com > > Cc: Saarinen, Jani ; > > intel-gfx@lists.freedesktop.org; > > Roper, Matthew D

Re: [Intel-gfx] [PATCH v2] drm/i915: Support more QGV points

Hi, > -Original Message- > From: Lisovskiy, Stanislav > Sent: maanantai 25. marraskuuta 2019 17.55 > To: ville.syrj...@linux.intel.com > Cc: Saarinen, Jani ; intel-gfx@lists.freedesktop.org; > Roper, Matthew D ; jani.nik...@linux.intel.com; > Sarvela, Tomi P > Subject: Re: [PATCH v2]

Re: [Intel-gfx] [PATCH v2] drm/i915: Support more QGV points

On Mon, 2019-11-25 at 17:31 +0200, Ville Syrjälä wrote: > On Fri, Nov 22, 2019 at 04:10:49PM +0200, Stanislav Lisovskiy wrote: > > According to BSpec 53998, there is a mask of > > max 8 SAGV/QGV points we need to support. > > > > Bumping this up to keep the CI happy(currently > > preventing tests

Re: [Intel-gfx] [PATCH v2] drm/i915: Support more QGV points

On Fri, Nov 22, 2019 at 04:10:49PM +0200, Stanislav Lisovskiy wrote: > According to BSpec 53998, there is a mask of > max 8 SAGV/QGV points we need to support. > > Bumping this up to keep the CI happy(currently > preventing tests to run), until all SAGV > changes land. > > Fixes:

[Intel-gfx] [PATCH 1/2] drm/i915/gem: Excise the per-batch whitelist from the context

One does not lightly add a new hidden struct_mutex dependency deep within the execbuf bowels! The immediate suspicion in seeing the whitelist cached on the context, is that it is intended to be preserved between batches, as the kernel is quite adept at caching small allocations itself. But no,

[Intel-gfx] [PATCH 2/2] Revert "drm/i915: use a separate context for gpu relocs"

Since commit c45e788d95b4 ("drm/i915/tgl: Suspend pre-parser across GTT invalidations"), we now disable the advanced preparser on Tigerlake for the invalidation phase at the start of the batch, we no longer need to emit the GPU relocations from a second context as they are now flushed inlined.

Re: [Intel-gfx] [PATCH] Revert "drm/fbdev: Fallback to non tiled mode if all tiles not present"

On Sat, 23 Nov 2019, Uma Shankar wrote: > This reverts commit f25c7a006cd1c07254780e3406e45cee4842b933. > > 2p2c display configuration blows up dmesg when one connector is > disconnected, causing issues in CI. > > Below are the sample errors thrown in logs: > > [IGT] core_getversion: executing >

Re: [Intel-gfx] [PATCH 3/7] drm: Extract page_flip_{internal, atomic}()

On Mon, Nov 25, 2019 at 10:02:38AM +0100, Daniel Vetter wrote: > On Fri, Nov 22, 2019 at 08:35:13PM +0200, Ville Syrjälä wrote: > > On Tue, Nov 19, 2019 at 11:14:43AM +0100, Daniel Vetter wrote: > > > On Fri, Nov 15, 2019 at 09:42:00PM +0200, Ville Syrjala wrote: > > > > From: Ville Syrjälä > > >

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame

On 25/11/2019 12:48, Chris Wilson wrote: An i915_vma struct on the stack may push the frame over the limit, if set conservatively, so move it to the heap. Signed-off-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame

== Series Details == Series: drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame URL : https://patchwork.freedesktop.org/series/69981/ State : success == Summary == CI Bug Log - changes from CI_DRM_7417 -> Patchwork_15422

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/execlists: Fixup cancel_port_requests()

== Series Details == Series: drm/i915/execlists: Fixup cancel_port_requests() URL : https://patchwork.freedesktop.org/series/69978/ State : failure == Summary == Applying: drm/i915/execlists: Fixup cancel_port_requests() Using index info to reconstruct a base tree... M

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Optimized CTB writes and reads

On Fri, 22 Nov 2019 02:29:59 +0100, Matthew Brost wrote: On Thu, Nov 21, 2019 at 07:56:07AM -0800, Matthew Brost wrote: On Thu, Nov 21, 2019 at 12:58:50PM +0100, Michal Wajdeczko wrote: On Thu, 21 Nov 2019 00:56:03 +0100, wrote: From: Matthew Brost CTB writes are now in the path of

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Add non blocking CTB send function

On Fri, 22 Nov 2019 02:34:22 +0100, Matthew Brost wrote: On Thu, Nov 21, 2019 at 04:13:25PM -0800, Matthew Brost wrote: On Thu, Nov 21, 2019 at 12:43:26PM +0100, Michal Wajdeczko wrote: On Thu, 21 Nov 2019 00:56:02 +0100, wrote: From: Matthew Brost Add non blocking CTB send fuction,

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Serialise with engine-pm around requests on the kernel_context

== Series Details == Series: series starting with [CI,1/3] drm/i915: Serialise with engine-pm around requests on the kernel_context URL : https://patchwork.freedesktop.org/series/69975/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7416 -> Patchwork_15420

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Sun, Nov 24, 2019 at 01:12:47PM -0800, Niranjan Vishwanathapura wrote: > > > > Using a temporary range is the pattern from nouveau, is it really > > > > necessary in this driver? > > > > > > Yah, not required. In my local build I tried with proper default_flags > > > and set pfn_flags_mask to

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Add non blocking CTB send function

On Fri, 22 Nov 2019 01:13:25 +0100, Matthew Brost wrote: On Thu, Nov 21, 2019 at 12:43:26PM +0100, Michal Wajdeczko wrote: On Thu, 21 Nov 2019 00:56:02 +0100, wrote: From: Matthew Brost Add non blocking CTB send fuction, intel_guc_send_nb. In order to support a non blocking CTB send

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Fixup cancel_port_requests()

Hi Chris, > /* Mark the end of active before we overwrite *active */ > - WRITE_ONCE(execlists->active, execlists->pending); > - > - for (port = execlists->active; (rq = *port); port++) > - execlists_schedule_out(rq); > - execlists->active = > -

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Fixup cancel_port_requests()

On 25/11/2019 11:25, Chris Wilson wrote: I rushed a last minute correction to cancel_port_requests() to prevent the snooping of *execlists->active as the inflight array was being updated, without noticing we iterated the inflight array starting from active! Oops. Fixes: 331bf9059157

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915: Serialise with engine-pm around requests on the kernel_context

== Series Details == Series: series starting with [CI,1/3] drm/i915: Serialise with engine-pm around requests on the kernel_context URL : https://patchwork.freedesktop.org/series/69975/ State : warning == Summary == $ dim checkpatch origin/drm-tip a349dbb29dc7 drm/i915: Serialise with

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+

Hi, On Fri, 22 Nov 2019, Ville Syrjälä wrote: > > - if (IS_G4X(dev_priv) || port == PORT_A) > > + if (IS_G4X(dev_priv) || (INTEL_GEN(dev_priv) < 12 && port == PORT_A)) > > Getting a bit messy. > > Hoovering that into something like > static bool intel_dp_port_has_audio(struct intel_encoder

[Intel-gfx] [PATCH v2 1/2] drm/i915/dp: fix DP audio for PORT_A on gen12+

Starting with gen12, PORT_A can be connected to a transcoder with audio support. Modify the existing logic that disabled audio on PORT_A unconditionally. Signed-off-by: Kai Vehmanen --- drivers/gpu/drm/i915/display/intel_dp.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-)

[Intel-gfx] [PATCH v2 2/2] drm/i915/dp: fix DP infoframe init for PORT_A on gen12+

Starting with gen12, PORT_A can be also connected to DP transcoder. Update code in intel_dp_init() to take this into account. Signed-off-by: Kai Vehmanen --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Update bug URL to point at gitlab issues

== Series Details == Series: drm/i915: Update bug URL to point at gitlab issues URL : https://patchwork.freedesktop.org/series/69974/ State : success == Summary == CI Bug Log - changes from CI_DRM_7416 -> Patchwork_15419 Summary ---

[Intel-gfx] [PATCH] drm/i915/selftests: Move mock_vma to the heap to reduce stack_frame

An i915_vma struct on the stack may push the frame over the limit, if set conservatively, so move it to the heap. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff

[Intel-gfx] ✓ Fi.CI.BAT: success for consistently use dma_resv locking wrappers

== Series Details == Series: consistently use dma_resv locking wrappers URL : https://patchwork.freedesktop.org/series/69970/ State : success == Summary == CI Bug Log - changes from CI_DRM_7416 -> Patchwork_15417 Summary ---

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2) URL : https://patchwork.freedesktop.org/series/69546/ State : failure == Summary == Applying: drm/i915: Flush idle barriers when waiting Applying: drm/i915: Allow userspace to specify

[Intel-gfx] [PATCH v6 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase.

[Intel-gfx] [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration

[Intel-gfx] [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS.

[Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu

High resolution timer is used for predictive governor to control eu/slice/subslice based on workloads. param is provided to enable/disable/update timer configuration V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for consistently use dma_resv locking wrappers

== Series Details == Series: consistently use dma_resv locking wrappers URL : https://patchwork.freedesktop.org/series/69970/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7776c394b6e2 drm/etnaviv: Use dma_resv locking wrappers -:49: WARNING:NO_AUTHOR_SIGN_OFF: Missing

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Mark the execlists->active as the primary volatile access (rev5)

== Series Details == Series: drm/i915/gt: Mark the execlists->active as the primary volatile access (rev5) URL : https://patchwork.freedesktop.org/series/69928/ State : failure == Summary == Applying: drm/i915/gt: Mark the execlists->active as the primary volatile access Using index info to

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Switch kunmap() to take the page not vaddr

== Series Details == Series: drm/i915: Switch kunmap() to take the page not vaddr URL : https://patchwork.freedesktop.org/series/69967/ State : failure == Summary == Applying: drm/i915: Switch kunmap() to take the page not vaddr Using index info to reconstruct a base tree... M

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