== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev8)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7558_full -> Patchwork_15742_full
Summary
== Series Details ==
Series: drm/i915/display: Read DP link status with DRM helper function
URL : https://patchwork.freedesktop.org/series/70878/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7558_full -> Patchwork_15741_full
===
== Series Details ==
Series: drm/i915/selftests: remove a condition
URL : https://patchwork.freedesktop.org/series/70877/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7557_full -> Patchwork_15740_full
Summary
---
**
On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > In case of tiled displays, all the tiles are linke dto each other
> > for transcoder port sync. So in intel_atomic_check() we need to make
> > sure that we add all the
== Series Details ==
Series: drm/i915/gem: Serialise object before changing cache-level
URL : https://patchwork.freedesktop.org/series/70917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15758
Summary
---
== Series Details ==
Series: Some debugfs enhancements (rev5)
URL : https://patchwork.freedesktop.org/series/70658/
State : failure
== Summary ==
Applying: drm/i915/rps: Add frequency translation helpers
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_rps.c
== Series Details ==
Series: drm/i915/gem: Serialise object before changing cache-level
URL : https://patchwork.freedesktop.org/series/70917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30034c200ed3 drm/i915/gem: Serialise object before changing cache-level
-:8: ERROR:GIT_COM
== Series Details ==
Series: series starting with [1/5] drm/i915: Call hsw_fdi_link_train()
directly()
URL : https://patchwork.freedesktop.org/series/70905/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15755
=
== Series Details ==
Series: drm/i915/svm: Add SVM support (rev2)
URL : https://patchwork.freedesktop.org/series/69908/
State : failure
== Summary ==
Applying: drm/i915/svm: Add SVM documentation
Applying: drm/i915/svm: Runtime (RT) allocator support
error: sha1 information is lacking or usele
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
URL : https://patchwork.freedesktop.org/series/70906/
State : failure
== Summary ==
Applying: drm/i915/perf: Register sysctl path globally
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev3)
URL : https://patchwork.freedesktop.org/series/63554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15754
Summary
---
**SUC
== Series Details ==
Series: drm/i915/dsi: fix pipe D readout for DSI transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/70752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7545_full -> Patchwork_15696_full
On Fri, Dec 13, 2019 at 03:02:28PM +0200, Stanislav Lisovskiy wrote:
> Added proper DBuf slice mapping to correspondent
> pipes, depending on pipe configuration as stated
> in BSpec.
>
> v2:
> - Remove unneeded braces
> - Stop using macro for DBuf assignments as
> it seems to reduce
On Fri, Dec 13, 2019 at 5:24 PM Niranjan Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
> >
> > +/**
> > + * struct drm_i915_gem_vm_bind
> > + *
> > + * Bind an object in a vm's page table.
> >
> > F
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev3)
URL : https://patchwork.freedesktop.org/series/63554/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f65c5faeb690 drm/edid: Abstract away cea_edid_modes[]
-:122: CHECK:COMPARISON_TO_NULL: Comparison to NU
On Thu, Dec 12, 2019 at 05:52:49PM +0200, Ville Syrjälä wrote:
On Wed, Dec 11, 2019 at 10:45:21AM -0800, José Roberto de Souza wrote:
intel_connector_needs_modeset() will be used outside of
intel_display.c in a future patch so it would only be necessary to
remove the state and add the prototype
On Mon, Nov 25, 2019 at 10:43:54AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Aside: We m
On Fri, Dec 13, 2019 at 10:52:03PM +, Li, Juston wrote:
> On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> > On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > > From: Daniel Stone
> > >
> > > getfb2 allows us to pass multiple planes and modifiers, just like
> > > addfb2
On Thu, Nov 07, 2019 at 04:24:13PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Annoyingly __drm_atomic_helper_crtc_reset() does two
totally separate things:
a) reset the state to defaults values
b) assign the crtc->state pointer
I just want a) without the b) so let's split out part
a) into
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
URL : https://patchwork.freedesktop.org/series/70871/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7556_full -> Patchwork_15738_full
==
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_rps_read_cagf: reads the frequency and returns it not
normalized
- intel_rps_read_actual_frequency: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-o
On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
+/**
+ * struct drm_i915_gem_vm_bind
+ *
+ * Bind an object in a vm's page table.
First off, this is something I've wanted for a while for Vulkan, it's just
never made its way high enough up the priority list.
On Wed, Dec 11, 2019 at 05:55:23PM +, Jose Souza wrote:
On Wed, 2019-12-11 at 13:08 +0200, Jani Nikula wrote:
Commit 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
added pipe D support for DSI, but failed to update the state readout.
Reviewed-by: José Roberto de Souza
pu
On Fri, Dec 13, 2019 at 4:07 PM Niranjana Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> Shared Virtual Memory (SVM) runtime allocator support allows
> binding a shared virtual address to a buffer object (BO) in the
> device page table through an ioctl call.
>
> Cc: Joonas Lahtine
On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > From: Daniel Stone
> >
> > getfb2 allows us to pass multiple planes and modifiers, just like
> > addfb2
> > over addfb.
> >
> > Changes since v1:
> > - unused modifiers set t
== Series Details ==
Series: drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
URL : https://patchwork.freedesktop.org/series/70893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7563 -> Patchwork_15753
Summar
Wait for the object to be idle before changing its cache-level and
unbinding. This was dropped as supposedly superfluous from commit
8b1c78e06e61 ("drm/i915: Avoid calling i915_gem_object_unbind holding
object lock"), but it turns out to prevent some cache dirt escaping.
Smells like papering over a
== Series Details ==
Series: drm/i915: Add device name to display tracepoints
URL : https://patchwork.freedesktop.org/series/70886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7563 -> Patchwork_15750
Summary
---
**
Add support function to blitter copy SVM VAs without requiring any
gem objects. Also add function to wait for completion of the copy.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Makefile
Use blitter engine to copy pages during migration.
As blitter context virtual address space is shared with other flows,
ensure virtual address are allocated properly from that address space.
Also ensure completion of blitter copy by waiting on the fence of the
issued request.
Cc: Joonas Lahtinen
Add SVM as a capability and allow user to enable/disable SVM
functionality on a per context basis.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_g
Add Shared Virtual Memory (SVM) support information.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/i915.rst | 29 +
1 file changed, 29 insertions(+)
diff --git a/Documentati
Add support to dump page table for debug purpose.
Here is an example dump. Format is,
[] :
Page Table dump start 0x0 len 0x
[0x0fe] 0x7f000: 0x6b0003
[0x1e6] 0x7f798: 0x6c0003
[0x16d] 0x7f79ada00: 0x5f0003
Use HMM page table mirroring support to build device page table.
Implement the bind ioctl and bind the process address range in the
specified context's ppgtt.
Handle invalidation notifications by unbinding the address range.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Du
Plugin device memory through HMM as DEVICE_PRIVATE.
Add support functions to allocate pages and free pages from device memory.
Implement ioctl to prefetch pages from host to device memory.
For now, only support migrating pages from host memory to device memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfi
As PCIe is non-coherent link, do not allow direct memory access across
PCIe link. Handle CPU fault by migrating pages back to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devme
Shared Virtual Memory (SVM) allows the programmer to use a single virtual
address space which will be shared between threads executing on CPUs and GPUs.
It abstracts away from the user the location of the backing memory, and hence
simplifies the user programming model.
SVM supports two types of vir
Copy the pages duing SVM migration using memcpy().
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devmem.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/driv
From: Venkata Sandeep Dhanalakota
As PCIe is non-coherent link, do not allow direct access to buffer
objects across the PCIe link for SVM case. Upon CPU accesses (mmap, pread),
migrate buffer object to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Cc:
For Shared Virtual Memory (SVM) system (SYS) allocator, there is no
backing buffer object (BO). Add support to bind a VA to PA mapping
in the device page table.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/d
Shared Virtual Memory (SVM) runtime allocator support allows
binding a shared virtual address to a buffer object (BO) in the
device page table through an ioctl call.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/
== Series Details ==
Series: drm/i915: Use EAGAIN for trylock failures
URL : https://patchwork.freedesktop.org/series/70891/
State : failure
== Summary ==
Applying: drm/i915: Use EAGAIN for trylock failures
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_ti
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
URL : https://patchwork.freedesktop.org/series/70888/
State : failure
== Summary ==
Applying: drm/i915/perf: Register sysctl path globally
Using index info to reconstruct a base tree...
M
On Fri, Dec 13, 2019 at 12:08 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_m
On Fri, Dec 13, 2019 at 12:10 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_m
Quoting Andi Shyti (2019-12-13 21:17:36)
> > > The GT system is becoming more and more a stand-alone system in
> > > i915 and it's fair to assign it its own debugfs directory.
> > >
> > > rc6, rps and llc debugfs files are gt related, move them into the
> > > gt debugfs directory.
> > >
> > > Sig
On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> From: Daniel Stone
>
> getfb2 allows us to pass multiple planes and modifiers, just like addfb2
> over addfb.
>
> Changes since v1:
> - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> - update ioctl number
>
> Signed-o
== Series Details ==
Series: drm/i915: Add device name to display tracepoints
URL : https://patchwork.freedesktop.org/series/70886/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
78e6434185eb drm/i915: Add device name to display tracepoints
-:113: WARNING:LONG_LINE: line over 10
On Fri, Dec 13, 2019 at 01:05:48PM -0800, Manasi Navare wrote:
> On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > > In case of tiled displays, all the tiles are linke dto each other
> > > for transcoder port sync.
> > The GT system is becoming more and more a stand-alone system in
> > i915 and it's fair to assign it its own debugfs directory.
> >
> > rc6, rps and llc debugfs files are gt related, move them into the
> > gt debugfs directory.
> >
> > Signed-off-by: Andi Shyti
> > ---
> > drivers/gpu/drm/i9
Quoting Andi Shyti (2019-12-13 21:00:50)
> From: Andi Shyti
>
> The GT system is becoming more and more a stand-alone system in
> i915 and it's fair to assign it its own debugfs directory.
>
> rc6, rps and llc debugfs files are gt related, move them into the
> gt debugfs directory.
>
> Signed-o
On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > In case of tiled displays, all the tiles are linke dto each other
> > for transcoder port sync. So in intel_atomic_check() we need to make
> > sure that we add all the
From: Andi Shyti
Hi,
this two patches are few debugfs improvements. The first adds
some helpers for reading the GT frequency, while the second patch
moves all the power management debufs functions into gt/
Thanks Chris and Michal for the reviews.
Thanks,
Andi
Changelog:
==
v4-v5: (v4:
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile
On Fri, Dec 13, 2019 at 10:28:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> > Add an extra check before making master slave assignments for tiled
> > displays to make sure we make these assignments only if all tiled
> > connectors are present. I
Hi Michal,
> > @@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
> > # "Graphics Technology" (aka we talk to the gpu)
> > obj-y += gt/
> > gt-y += \
> > + gt/debugfs_gt.o \
> > + gt/debugfs_pm.o \
>
> hm, maybe this should be:
> gt/intel_gt_debugfs.o
> and
> gt/intel_p
On Thu, Dec 12, 2019 at 10:44:29PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 10:45:22AM -0800, José Roberto de Souza wrote:
> > On TGL the blending of all the streams have moved from DDI to
> > transcoder, so now every transcoder working over the same MST port must
> > send its stream t
On Fri, Dec 13, 2019 at 10:28:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> > Add an extra check before making master slave assignments for tiled
> > displays to make sure we make these assignments only if all tiled
> > connectors are present. I
>-Original Message-
>From: dri-devel On Behalf Of
>Daniel Vetter
>Sent: Friday, December 13, 2019 3:08 PM
>To: DRI Development
>Cc: Daniel Vetter ; Intel Graphics Development
>; etna...@lists.freedesktop.org; Russell
>King ; Vetter, Daniel
>
>Subject: Re: [PATCH 1/4] drm/etnaviv: Use dma_
On Fri, Dec 13, 2019 at 12:40:13PM -0800, Manasi Navare wrote:
> On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > > While clearing the Ports ync mode enable and master select bits
> > > we need to make sure that we
== Series Details ==
Series: series starting with [1/2] drm: Handle connector tile support only for
modes that match tile size
URL : https://patchwork.freedesktop.org/series/70790/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7545_full -> Patchwork_15701_full
===
On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > While clearing the Ports ync mode enable and master select bits
> > we need to make sure that we perform a RMW for disable else
> > it sets the other bits casuing unwa
On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> Add an extra check before making master slave assignments for tiled
> displays to make sure we make these assignments only if all tiled
> connectors are present. If not then initialize the state to defaults
> so it does a normal non t
== Series Details ==
Series: series starting with [1/8] drm/print: introduce new struct drm_device
based logging macros (rev3)
URL : https://patchwork.freedesktop.org/series/70685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7561 -> Patchwork_15749
=
On Fri, Dec 13, 2019 at 06:55:06PM +, Patchwork wrote:
> == Series Details ==
>
> Series: AUX power well fixes (rev4)
> URL : https://patchwork.freedesktop.org/series/70857/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7554_full -> Patchwork_15737_full
> ===
On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
On Fri, Dec 13, 2019 at 10:06:01AM -0800, Lucas De Marchi wrote:
> On Thu, Dec 12, 2019 at 05:06:00PM -0800, Matt Roper wrote:
> > Now that the combo PHY aux power well handlers are used exclusively on
> > Icelake, we can drop a bunch of the extra tests.
> >
> > v2: Don't try to use intel_uncore_r
On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
On Mon, Nov 25, 2019 at 10:43:53AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> While clearing the Ports ync mode enable and master select bits
> we need to make sure that we perform a RMW for disable else
> it sets the other bits casuing unwanted sideeffects.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/int
On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> In case of tiled displays, all the tiles are linke dto each other
> for transcoder port sync. So in intel_atomic_check() we need to make
> sure that we add all the tiles to the modeset and if one of the
> tiles needs a full modeset th
We do not require to register the sysctl paths per instance,
so making registration global.
v2: make sysctl path register and unregister function driver
specific (Tvrtko and Lucas).
v3: remove the NULL-check as unregister_sysctl_table is null
safe. (Chris and Lucas)
Cc: Sudeep Dutt
Cc:
New macros ENGINE_TRACE(), CE_TRACE(), RQ_TRACE() and
GT_TRACE() are introduce to tag device name and engine
name with contexts and requests tracing in i915.
v2: Addressed CI checkpatch issues.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Reviewed-by: C
From: Ville Syrjälä
Remove the pointless vfunc detour for hsw_fdi_link_train()
and just call it directly. Also pass the encoder in so we
can nuke the silly encoder loop within.
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt
From: Ville Syrjälä
Move all of haswell_crtc_disable() into the encoder
.post_disable() hooks. Now we're left with just
calling the .disable() and .post_disable() hooks
back to back.
I chose to move the code into the .post_disable() hook instead
of the .enable() hook as most of the sequence is c
From: Ville Syrjälä
To make life easier in the future let's pass the old crtc state
to intel_crtc_vblank_off() just like we already do for its
counterpart intel_crtc_vblank_on().
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_d
From: Ville Syrjälä
To make life easier in the future let's pass the old crtc state
to skylake_scaler_disable() just like we already do for
for its ancestor ironlake_pfit_disable().
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/inte
From: Ville Syrjälä
HSW+ platforms call encoder .post_disable() and .post_pll_disable()
back to back. And since we don't even disable the PLL in between
let's just move everything into .post_disable().
intel_dp_mst does forward the .post_disable() call to intel_ddi at
the very end of its own .po
Quoting Andi Shyti (2019-12-13 19:41:29)
> Hi Michal,
>
> > > @@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
> > > # "Graphics Technology" (aka we talk to the gpu)
> > > obj-y += gt/
> > > gt-y += \
> > > + gt/debugfs_gt.o \
> > > + gt/debugfs_pm.o \
> >
> > hm, maybe this shou
== Series Details ==
Series: series starting with [1/8] drm/print: introduce new struct drm_device
based logging macros (rev3)
URL : https://patchwork.freedesktop.org/series/70685/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ccbb2bd92a4 drm/print: introduce new struct drm_d
On Fri, Dec 13, 2019 at 03:59:02PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:20 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > On HDCP disable, clear the repeater bit. This ensures if we connect a
> > non-repeater sink after a repeater, the bit is in the state we expect.
> >
> > F
On Fri, 13 Dec 2019 19:37:36 +0100, Andi Shyti wrote:
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-of
On Fri, Dec 13, 2019 at 04:40:33PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:25 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch adds some protection against connectors being destroyed
> > before the HDCP workers are finished.
> >
> > For check_work, we do a synchronous c
On Fri, Dec 13, 2019 at 05:28:25PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:26 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch is required for HDCP over MST. If a port is being used for
> > multiple HDCP streams, we don't want to fully disable HDCP on a port if
> > one o
== Series Details ==
Series: drm/i915/execlists: Select arb on/off around batches based on preemption
URL : https://patchwork.freedesktop.org/series/70885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7560 -> Patchwork_15748
===
On Fri, Dec 13, 2019 at 03:02:27PM +0200, Stanislav Lisovskiy wrote:
> Start manipulating DBuf slices as a mask,
> but not as a total number, as current approach
> doesn't give us full control on all combinations
> of slices, which we might need(like enabling S2
> only can't enabled by setting enab
== Series Details ==
Series: AUX power well fixes (rev4)
URL : https://patchwork.freedesktop.org/series/70857/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7554_full -> Patchwork_15737_full
Summary
---
**FAILURE**
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_rps_read_cagf: reads the frequency and returns it not
normalized
- intel_rps_read_actual_frequency: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-o
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile
From: Andi Shyti
Hi,
this two patches are few debugfs improvements. The first adds
some helpers for reading the GT frequency, while the second patch
moves all the power management debufs functions into gt/
Thanks Chris for the reviews.
Thanks,
Andi
Changelog:
==
v3-v4: (v3:
https://l
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev14)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7560 -> Patchwork_15747
Summary
---
**SUCCESS**
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev14)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
455914397efd drm/i915: Refactor intel_can_enable_sagv
-:728: WARNING:LONG_LINE: line over 100 characters
#728: F
On Thu, Dec 12, 2019 at 05:06:00PM -0800, Matt Roper wrote:
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need
On Thu, Dec 12, 2019 at 04:15:10PM -0800, Matt Roper wrote:
The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it. In fact Swati just discovered that applying this workaround
is the root cause of some p
On Thu, Dec 12, 2019 at 04:15:09PM -0800, Matt Roper wrote:
Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL. And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is act
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
v2: Improve the comment for cea_modes_*[] to indicate
that one should always use cea_mode_for_vic() (Tom)
Cc: Hans Verkuil
Reviewed-by: Manasi Navare
Reviewed-by: Thomas Anderson
Signed-off-by: Ville Syrjälä
---
d
From: Ville Syrjälä
Review feedback addressed. I considered changing the approach
based on Tom's comments but in the end decided that probably
better to go with this for now. We can massage it later if
required.
Cc: Hans Verkuil
Cc: Manasi Navare
Cc: Thomas Anderson
Ville Syrjälä (4):
drm/
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
v2: Rebase
Cc: Tom Anderson
Cc: Hans Verkuil
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 12
From: Ville Syrjälä
We depend on a specific relationship between the VIC number and the
index in the CEA mode arrays. Assert that the arrays have the expected
size to make sure we've not accidentally left holes in them.
v2: Pimp the BUILD_BUG_ON()s
v3: Fix typos (Manasi)
Cc: Hans Verkuil
Revie
From: Ville Syrjälä
We're going to need two cea mode tables (one for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] to indicate how it's to be
indexed.
v2: Fix typos (Tom)
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