On 27-Dec-19 2:39 AM, Lucas De Marchi wrote:
On Wed, Dec 25, 2019 at 10:07 AM Swati Sharma wrote:
Increase the log level if DSB engine gets busy. If dsb engine
is busy, it should be an error condition to indicate there might be
some difficulty with the hardware.
If DSB engine gets busy, load
== Series Details ==
Series: drm/i915/display: nuke skl workaround for pre-production hw (rev2)
URL : https://patchwork.freedesktop.org/series/71230/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7630_full -> Patchwork_15906_full
On Thu, Dec 26, 2019 at 02:23:49PM -0800, Lucas De Marchi wrote:
> On Tue, Dec 24, 2019 at 03:15:21PM -0800, Matt Roper wrote:
> > Our usual i915 convention is to assume that future platforms will follow
> > the same behavior as the latest platform of today. The VDBOX/SFC
> > capabilities
On Tue, Dec 24, 2019 at 03:15:21PM -0800, Matt Roper wrote:
Our usual i915 convention is to assume that future platforms will follow
the same behavior as the latest platform of today. The VDBOX/SFC
capabilities described here don't seem like something that should be
specific to TGL, so let's
== Series Details ==
Series: drm/i915/gt: Apply sanitiization just before resume
URL : https://patchwork.freedesktop.org/series/71334/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7630_full -> Patchwork_15905_full
Summary
On Wed, Dec 25, 2019 at 10:07 AM Swati Sharma wrote:
>
> Increase the log level if DSB engine gets busy. If dsb engine
> is busy, it should be an error condition to indicate there might be
> some difficulty with the hardware.
>
> If DSB engine gets busy, load luts will fail and as per current
>
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> During phy compliance auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
>
> v2: As per
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_dp.c:4950:1-33: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_dp.c:4906:1-33: WARNING: Assignment of 0/1
to bool variable
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
---
Fixes coccicheck warning:
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to
bool
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
>
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
>
> Cc: Harry Wentland
> Cc: Alex Deucher
> Signed-off-by: Animesh Manna
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_crt.c:1066:1-28: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:928:2-29: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:443:2-29: WARNING: Assignment of 0/1
== Series Details ==
Series: drm/i915/gt: Ignore incomplete engines after init failure
URL : https://patchwork.freedesktop.org/series/71404/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7637 -> Patchwork_15930
Summary
== Series Details ==
Series: drm/i915: Add Wa_1407352427:icl,ehl (rev2)
URL : https://patchwork.freedesktop.org/series/71403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7637 -> Patchwork_15929
Summary
---
Do not expose incomplete engines to the user after we fail to setup the
GT.
Fixes: e6ba76480299 ("drm/i915: Remove i915->kernel_context")
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 4
drivers/gpu/drm/i915/gt/intel_gt.h | 7 ++-
The workaround database now indicates we need to disable psdunit clock
gating as well.
Bspec: 32354
Bspec: 33450
Bspec: 33451
Suggested-by: Lionel Landwerlin
Cc: sta...@vger.kernel.org
Cc: Lionel Landwerlin
Cc: Lucas De Marchi
Cc: Matt Atwood
Signed-off-by: Matt Roper
Acked-by: Lionel
On Thu, Dec 26, 2019 at 08:09:04PM +0200, Lionel Landwerlin wrote:
> On 26/12/2019 19:39, Matt Roper wrote:
> > On Wed, Dec 25, 2019 at 09:31:29PM +0200, Lionel Landwerlin wrote:
> > > On 24/12/2019 03:20, Matt Roper wrote:
> > > > A quick drive-by update for some workarounds I noticed that were
>
== Series Details ==
Series: drm/i915: Add Wa_1407352427:icl,ehl
URL : https://patchwork.freedesktop.org/series/71403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7637 -> Patchwork_15928
Summary
---
**FAILURE**
On 26/12/2019 19:46, Matt Roper wrote:
The workaround database now indicates we need to disable psdunit clock
gating as well.
Bspec: 32354
Bspec: 33450
Bspec: 33451
Suggested-by: Lionel Landwerlin
Cc: Lionel Landwerlin
Cc: Lucas De Marchi
Cc: Matt Atwood
Signed-off-by: Matt Roper
On 26/12/2019 19:39, Matt Roper wrote:
On Wed, Dec 25, 2019 at 09:31:29PM +0200, Lionel Landwerlin wrote:
On 24/12/2019 03:20, Matt Roper wrote:
A quick drive-by update for some workarounds I noticed that were
added/extended to additional platforms.
Cc: Lucas De Marchi
Cc: Matt Atwood
Cc:
== Series Details ==
Series: drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability
(rev2)
URL : https://patchwork.freedesktop.org/series/71371/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7637 -> Patchwork_15927
The workaround database now indicates we need to disable psdunit clock
gating as well.
Bspec: 32354
Bspec: 33450
Bspec: 33451
Suggested-by: Lionel Landwerlin
Cc: Lionel Landwerlin
Cc: Lucas De Marchi
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
On Wed, Dec 25, 2019 at 09:31:29PM +0200, Lionel Landwerlin wrote:
> On 24/12/2019 03:20, Matt Roper wrote:
> > A quick drive-by update for some workarounds I noticed that were
> > added/extended to additional platforms.
> >
> > Cc: Lucas De Marchi
> > Cc: Matt Atwood
> > Cc: Radhakrishna
On Tue, Dec 24, 2019 at 11:53:33PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Assume future platforms will inherit TGL's SFC
> capability
> URL : https://patchwork.freedesktop.org/series/71371/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Wed, Dec 25, 2019 at 12:05 AM Ebrahim Byagowi wrote:
>
>
> Clang raises
>
> drivers/gpu/drm/i915/i915_perf.c:2474:50: warning: operator '?:' has lower
> precedence than '|'; '|' will be evaluated first
> [-Wbitwise-conditional-parentheses]
>
== Series Details ==
Series: drm/i915/gt: Flush other retirees inside intel_gt_retire_requests()
URL : https://patchwork.freedesktop.org/series/71333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7630_full -> Patchwork_15904_full
== Series Details ==
Series: drm/i915/gt: Apply sanitiization just before resume (rev2)
URL : https://patchwork.freedesktop.org/series/71334/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7636 -> Patchwork_15926
Summary
Bring sanitization completely underneath the umbrella of intel_gt, and
perform it exclusively after suspend and before the next resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.c| 6 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 31 ++-
== Series Details ==
Series: series starting with [1/2] drm/i915: Add spaces before compound
GEM_TRACE
URL : https://patchwork.freedesktop.org/series/71331/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7630_full -> Patchwork_15903_full
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