== Series Details ==
Series: drm/i915/huc: Fix error reported by I915_PARAM_HUC_STATUS (rev2)
URL : https://patchwork.freedesktop.org/series/72419/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7984 -> Patchwork_16665
== Series Details ==
Series: drm/i915: Fix kbuild test robot build error
URL : https://patchwork.freedesktop.org/series/73990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8012 -> Patchwork_16728
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/i915: Replace the hardcoded
I915_FENCE_TIMEOUT
URL : https://patchwork.freedesktop.org/series/73914/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008_full -> Patchwork_16706_full
On Tue, 25 Feb 2020, Chris Wilson wrote:
> Quoting Jani Nikula (2020-02-25 11:15:09)
>> The implicit "dev_priv" local variable use has been a long-standing pain
>> point in the register access macros I915_READ(), I915_WRITE(),
>> POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
>>
>> Replace
On Thu, 27 Feb 2020, Anshuman Gupta wrote:
> Fix kbuild test robot build error for below commit
> .
The proper format to reference other commits is
d54c1a513c48 ("drm/i915: Fix broken transcoder err state")
If you put this magic spell in your ~/.gitconfig under [alias]:
cite =
== Series Details ==
Series: drm/i915: Skip barriers inside waits
URL : https://patchwork.freedesktop.org/series/73984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8012 -> Patchwork_16727
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Introduce i915 based i915_MISSING_CASE macro and us it in i915
URL : https://patchwork.freedesktop.org/series/73908/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008_full -> Patchwork_16705_full
Hi Chris,
> -Original Message-
> From: Chris Wilson
> Sent: 25 February 2020 19:32
> To: David Airlie ; Joonas Lahtinen
> ; Laxminarayan Bharadiya, Pankaj
> ; Vivi, Rodrigo
> ; dan...@ffwll.ch; dri-de...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org;
On Thu, 27 Feb 2020, "Souza, Jose" wrote:
> On Wed, 2020-02-26 at 16:02 -0800, Lucas De Marchi wrote:
>> On Tue, Feb 25, 2020 at 5:45 PM José Roberto de Souza
>> wrote:
>> > Spliting GT and display revisions id to correctly apply workarounds
>> > because we have some issues that were fixed in
On Tue, 25 Feb 2020, José Roberto de Souza wrote:
> Spliting GT and display revisions id to correctly apply workarounds
> because we have some issues that were fixed in display B0 but no
> hardware was made with B0 stepping, so to keep consistent with BSpec
> splitting it from GT and adding this
Fix kbuild test robot build error for below commit
.
has_transcoder() was unused because function which was using it
intel_display_capture_error_state() defined under
CONFIG_DRM_I915_CAPTURE_ERROR.
Moving has_transcoder() to under CONFIG_DRM_I915_CAPTURE_ERROR.
No functional change.
Cc: Ville
On Wed, Feb 26, 2020 at 4:43 PM Souza, Jose wrote:
>
> On Wed, 2020-02-26 at 16:02 -0800, Lucas De Marchi wrote:
> > On Tue, Feb 25, 2020 at 5:45 PM José Roberto de Souza
> > wrote:
> > > Spliting GT and display revisions id to correctly apply workarounds
> > > because we have some issues that
Hi Dave & Daniel -
Switching gen7 back to aliasing-ppgtt seems to be the main highlight
here.
BR,
Jani.
drm-intel-fixes-2020-02-27:
drm/i915 fixes for v5.6-rc4:
- downgrade gen7 back to aliasing-ppgtt to avoid GPU hangs
- shrinker fix
- pmu leak and double free fixes
- gvt user after free and
Hi all -
The following commits have been marked as Cc: stable or fixing something
in v5.6-rc3 or earlier, but failed to cherry-pick to
drm-intel-fixes. Please see if they are worth backporting, and please do
so if they are.
Failed to cherry-pick:
837b63e60878 ("drm/i915: Program MBUS with rmw
== Series Details ==
Series: series starting with [1/3] drm/i915/perf: Mark up the racy use of
perf->exclusive_stream
URL : https://patchwork.freedesktop.org/series/73978/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8011 -> Patchwork_16726
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16725
Summary
---
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Fix bounds check in intel_get_shared_dpll_id()
Okay!
Commit:
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ad933d04ce1 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
649c52ce9987 drm/i915: Move
== Series Details ==
Series: drm/i915/ggtt: do not set bits 1-11 in gen12 ptes
URL : https://patchwork.freedesktop.org/series/73969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16724
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/i915/gem: Consolidate ctx->engines[]
release
URL : https://patchwork.freedesktop.org/series/73966/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16723
== Series Details ==
Series: series starting with [1/3] drm/i915: Fix 400 MHz FSB readout on elk
URL : https://patchwork.freedesktop.org/series/73965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16722
== Series Details ==
Series: 3 display pipes combination system support (rev5)
URL : https://patchwork.freedesktop.org/series/72468/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16721
Summary
---
== Series Details ==
Series: drm/i915: Set up PIPE_MISC truncate bit on tgl+
URL : https://patchwork.freedesktop.org/series/73960/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16719
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/i915: HDCP: fix Ri prime check done
during link check
URL : https://patchwork.freedesktop.org/series/73961/
State : failure
== Summary ==
Applying: drm/i915: HDCP: fix Ri prime check done during link check
Using index info to
== Series Details ==
Series: drm/i915/selftests: Disable heartbeat around manual pulse tests
URL : https://patchwork.freedesktop.org/series/73958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16718
On Wed, 2020-02-26 at 16:02 -0800, Lucas De Marchi wrote:
> On Tue, Feb 25, 2020 at 5:45 PM José Roberto de Souza
> wrote:
> > Spliting GT and display revisions id to correctly apply workarounds
> > because we have some issues that were fixed in display B0 but no
> > hardware was made with B0
tree: git://anongit.freedesktop.org/drm-intel for-linux-next
head: 7a0a6ee731508b770f3ee198af7b0c87a20ebb80
commit: d54c1a513c487ac6d6b3c4595e93e3625b461cc3 [3/6] drm/i915: Fix broken
transcoder err state
config: x86_64-randconfig-b003-20200226 (attached as .config)
compiler: gcc-7 (Debian
On Tue, Feb 25, 2020 at 5:45 PM José Roberto de Souza
wrote:
>
> Spliting GT and display revisions id to correctly apply workarounds
> because we have some issues that were fixed in display B0 but no
> hardware was made with B0 stepping, so to keep consistent with BSpec
> splitting it from GT and
On Wed, 2020-02-26 at 18:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to
> PIPE_MISC on tgl. Frob the new location.
>
> Bspec does still document the old bits as well, so I left the code
> for them as is until we get
On Tue, Feb 25, 2020 at 05:45:51PM -0800, José Roberto de Souza wrote:
> This workaround is only fixed in C0 stepping to extend it to B0 too.
>
> BSpec: 52890
> Cc: Radhakrishna Sripada
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: José Roberto de Souza
> ---
>
Hi Hans
Just commenting in the "[3.309061] [drm:intel_dump_pipe_config
[i915]] MST master transcoder: " message, it is the expected
behaviour for anything older than Tigerlake, from TGL+ this will be set
in MST mode.
On Wed, 2020-02-26 at 18:52 +0100, Hans de Goede wrote:
> Hi,
>
> On
Attaching to the i915_active barrier is a two stage process, and a flush
is only effective when the barrier is activation. Thus it is possible
for us to see a barrier, and attempt to flush, only for our flush to
have no effect. As such, before attempting to activate signaling on the
fence we need
On Wed, Feb 26, 2020 at 02:47:24PM -0800, Souza, Jose wrote:
> On Mon, 2020-02-24 at 14:36 -0800, Matt Roper wrote:
> > From: Matt Atwood
> >
> > On Tiger Lake we do not support source keying in the pixel formats
> > P010,
> > P012, P016.
> >
> > v2: Move WA to end of function. Create helper
On Wed, Feb 26, 2020 at 02:19:52PM -0800, Souza, Jose wrote:
> On Thu, 2020-02-20 at 15:18 -0800, Matt Roper wrote:
> > On gen12, we no longer need to disable DC5/DC6 when when PG2 is in
> > use
> > (which translates to cases where we're using VDSC on pipe A).
> >
> > Bspec: 49193
>
>
On Wed, Feb 26, 2020 at 06:38:40PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-next pull. Mostly for cleanup and kvmgt specific struct
> has been moved to its own module, also enable VFIO edid for all platform
> including CML. Pls see details below.
pulled, thanks
>
> Thanks
> --
> The
On Mon, 2020-02-24 at 14:36 -0800, Matt Roper wrote:
> From: Matt Atwood
>
> On Tiger Lake we do not support source keying in the pixel formats
> P010,
> P012, P016.
>
> v2: Move WA to end of function. Create helper function for format
> check. Less verbose debugging messaging.
>
> v3:
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16717
Summary
---
**FAILURE**
On Thu, 2020-02-20 at 15:18 -0800, Matt Roper wrote:
> On gen12, we no longer need to disable DC5/DC6 when when PG2 is in
> use
> (which translates to cases where we're using VDSC on pipe A).
>
> Bspec: 49193
Reviewed-by: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
== Series Details ==
Series: drm/i915: significantly reduce the use of (rev2)
URL : https://patchwork.freedesktop.org/series/73902/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8005_full -> Patchwork_16704_full
Summary
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!
Commit: drm/i915: Introduce
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9bdbd2c7c9d drm/i915: Start passing latency as parameter
c0db4cbaa46c drm/i915: Introduce skl_plane_wm_level
On Wed, 26 Feb 2020, Zhenyu Wang wrote:
> Hi,
>
> Here's gvt-fixes for 5.6-rc with two fixes. One to resolve virtual
> display reset and another one for use-after-free in dmabuf destroy
> function.
Pulled, thanks.
BR,
Jani.
>
> Thanks
> --
> The following changes since commit
Wait for the last request (and so waits for all context updates) when
disabling OA. This prevents a rather bizarre error seen on Skylake
where the context is subsequently corrupted. Let's play safe and assume
it may impact all.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc:
The engine->kernel_context is a special case for request emission. Since
it is used as the barrier within the engine's wakeref, we must acquire the
wakeref before submitting a request to the kernel_context.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
Inside the general i915_oa_init_reg_state() we avoid using the
perf->mutex. However, we rely on perf->exclusive_stream being valid to
access at that point, and for that we have to control the race with
disabling perf. This relies on the disabling being a heavy barrier that
inspects all active
== Series Details ==
Series: drm/i915: Use intel_plane_data_rate for min_cdclk calculation (rev4)
URL : https://patchwork.freedesktop.org/series/73718/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16716
For consistency with the WRPLL/LCPLL parameter calculation functions,
split out the SPLL specific logic to its own function.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 36 +++
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git
For clarity keep the SKL DPLL ref clock in a variable instead of
open-coding it. Store the value in kHZ units as done on other platforms.
This allows us in a later patch to keep track of the DPLL ref clock in a
more unified way across all platforms.
Signed-off-by: Imre Deak
---
Move all the DPLL params->DPLL frequency conversion functions to
intel_dpll_mgr.c where the corresponding inverse conversions are.
The GEN11+ TBT PLL outputs multiple frequencies and for selecting the
one in use we need to check the DDI CLK mux. As part of the DDI clock
logic this selection is
Split out the PLL parameter->frequency conversion logic for each type of
PLL for symmetry with their corresponding inverse conversion functions.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
Move the per-platform DPLL and DPLL-manager vfunc initializations right
after the corresponding function definitions.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 120 +-
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git
The types of PLLs used for HDMI/DP on HSW are WRPLL/LCPLL accordingly,
so use these names to align better with the rest of WRPLL/LCPLL function
names elsewhere.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +-
1 file changed, 5 insertions(+), 5
This patchset moves the platforms specific functions calculating the
DPLL frequency next to the counterpart functions calculating DPLL params
from a given frequency.
It also adds a way to track the DPLL reference clock frequencies in a
unified way across platforms.
Imre Deak (13):
drm/i915:
For clarity add a new DPLL specific struct to the i915 device struct and
move all DPLL fields into it. Accordingly remove the dpll_ prefixes, as
the new struct already provides the required namespacing.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c| 12 ++--
Move the HW readout/sanitize functions to intel_dpll_mgr.c which
contains the rest of shared DPLL functionality.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 +++
Instead of converting DPLL ID to CLK_SEL to identify the DPLL use the
DPLL ID directly for this.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
Instead of reading out the WRPLL/SPLL control values from HW, we can use
the DPLL state that was already read out, or swapped-to.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
All platforms using the shared DPLL framework use 3 reference clocks for
their DPLLs: SSC, non-SSC and DSI. For a more unified way across
platforms store the frequency of these ref clocks as part of the DPLL
global state. This also allows us to keep the HW access reading out the
ref clock value
Fix an off-by-one error in the upper-bound check and while at it clear
up a bit the function.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
Split out the PLL parameter->frequency conversion logic for each type of
PLL for symmetry with their corresponding inverse conversion functions.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 91 ---
1 file changed, 56 insertions(+), 35 deletions(-)
== Series Details ==
Series: drm/i915/display: conversion to drm_device based logging macros (rev3)
URL : https://patchwork.freedesktop.org/series/72760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16715
== Series Details ==
Series: drm/i915/display: conversion to drm_device based logging macros (rev3)
URL : https://patchwork.freedesktop.org/series/72760/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72e7872cdf57 drm/i915/dsb: convert to drm_device based logging macros.
== Series Details ==
Series: series starting with [01/17] drm/i915/gt: Reset queue_priority_hint
after wedging
URL : https://patchwork.freedesktop.org/series/73947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16714
== Series Details ==
Series: series starting with [01/17] drm/i915/gt: Reset queue_priority_hint
after wedging
URL : https://patchwork.freedesktop.org/series/73947/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aa291c2295eb drm/i915/gt: Reset queue_priority_hint after wedging
== Series Details ==
Series: series starting with [v2,01/14] drm/i915/tgl: Split GT and display
workarounds
URL : https://patchwork.freedesktop.org/series/73934/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16713
On TGL, bits 2-4 in the GGTT PTE are not ignored anymore and are
instead used for some extra VT-d capabilities. We don't (yet?) have
support for those capabilities, but, given that we shared the pte_encode
function betweed GGTT and PPGTT, we still set those bits to the PPGTT
PPAT values. The DMA
== Series Details ==
Series: series starting with [v2,01/14] drm/i915/tgl: Split GT and display
workarounds
URL : https://patchwork.freedesktop.org/series/73934/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
78f68ec9e707 drm/i915/tgl: Split GT and display workarounds
-:98:
== Series Details ==
Series: drm/i915/selftests: Add request throughput measurement to perf
URL : https://patchwork.freedesktop.org/series/73930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16712
== Series Details ==
Series: drm/i915/gt: Autotune idle timeouts
URL : https://patchwork.freedesktop.org/series/73919/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16709
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/selftests: Add request throughput measurement to perf
URL : https://patchwork.freedesktop.org/series/73930/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0ab87e3fd76b drm/i915/selftests: Add request throughput measurement to perf
-:90:
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/73927/
State : failure
== Summary ==
Applying: drm/i915: Flush idle barriers when waiting
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915: Proper dbuf global state (rev2)
URL : https://patchwork.freedesktop.org/series/73421/
State : failure
== Summary ==
Applying: drm/i915: Handle some leftover s/intel_crtc/crtc/
Applying: drm/i915: Remove garbage WARNs
Applying: drm/i915: Add missing
== Series Details ==
Series: drm: Replace zero-length array with flexible-array member
URL : https://patchwork.freedesktop.org/series/73916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16708
Summary
== Series Details ==
Series: series starting with [1/3] drm/i915: Replace the hardcoded
I915_FENCE_TIMEOUT
URL : https://patchwork.freedesktop.org/series/73914/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16706
Hi,
On 2/26/20 5:05 PM, Alex Deucher wrote:
On Wed, Feb 26, 2020 at 10:43 AM Hans de Goede wrote:
Hi,
On 2/26/20 4:29 PM, Alex Deucher wrote:
On Wed, Feb 26, 2020 at 10:16 AM Hans de Goede wrote:
Hi Lyude and everyone else,
Lyude I'm mailing you about this because you have done a lot
If a context is banned even before we submit our first request to it,
report the failure before we attempt to allocate any resources for the
context.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
1 file changed, 5 insertions(+)
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson
As setup takes a long time, the user may close the context during the
construction of the execbuf. In order to make sure we correctly track
all outstanding work with non-persistent contexts, we need to serialise
the submission with the context closure and mop up any leaks.
Signed-off-by: Chris
From: Ville Syrjälä
I've checked a bunch of gen3/4 machines and all seem to have
consistent FSB frequency information in the CLKCFG register.
So let's read out hrawclk on all gen3+ machines. Although
apart from g4x/pnv aux/pps dividers we only really need this
for for i965g/gm cs timestamp
From: Ville Syrjälä
Looks like elk redefines some of the CLKCFG FSB values to
make room for 400 MHz FSB. The setting overlaps with one of
the 266MHz settings (which is even documented in the ctg docs,
and cofirmed to be correct on my ctg). So we limit the special
case to elk only.
Though it
From: Ville Syrjälä
Document the fact that we aren't reading out the actual FSB
frequency but rather just the state of the FSB straps.
Some BIOSen allow you to configure the two independently.
So if someone sets the two up in an inconsistent manner
we'll get the wrong answer here and thus will
== Series Details ==
Series: drm/i915/gt: Autotune idle timeouts
URL : https://patchwork.freedesktop.org/series/73919/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
251374a10d4d drm/i915/gt: Autotune idle timeouts
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description
On Wed, Feb 26, 2020 at 08:54:08PM +0530, Anshuman Gupta wrote:
> On 2020-02-26 at 17:09:43 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 25, 2020 at 05:06:39PM +0200, Ville Syrjälä wrote:
> > > On Mon, Feb 24, 2020 at 06:10:01PM +0530, Anshuman Gupta wrote:
> > > > As a disabled pipe in pipe_mask
== Series Details ==
Series: drm/i915: Introduce i915 based i915_MISSING_CASE macro and us it in i915
URL : https://patchwork.freedesktop.org/series/73908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16705
== Series Details ==
Series: drm: Replace zero-length array with flexible-array member
URL : https://patchwork.freedesktop.org/series/73916/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bdffb4ce0539 drm: Replace zero-length array with flexible-array member
-:171:
Quoting Tvrtko Ursulin (2020-02-26 16:41:03)
>
> On 25/02/2020 08:22, Chris Wilson wrote:
> > Use the same engine_idle_release() routine for cleaning all old
> > ctx->engine[] state, closing any potential races with concurrent execbuf
> > submission.
> >
> > Closes:
== Series Details ==
Series: series starting with [01/20] drm/i915: Drop inspection of execbuf flags
during evict
URL : https://patchwork.freedesktop.org/series/73915/
State : failure
== Summary ==
Applying: drm/i915: Drop inspection of execbuf flags during evict
Applying: drm/i915/gem:
As a disabled pipe in pipe_mask is not having a valid intel crtc,
driver wrongly populates the possible_crtcs mask while initializing
the plane for a CRTC. Fixing up the plane possible_crtcs mask.
changes since RFC:
- Simplify the possible_crtcs initialization. [Ville]
v2:
- Removed the
A single Ri mismatch doesn't automatically mean that the
link integrity is broken. Update and check of Ri and Ri'
are done asynchronously. In case an update happens just
between the read of Ri' and the check against Ri there will
be a mismatch even if the link integrity is fine otherwise.
A
Including HDCP_STATUS_ENC bit in the checks is pointless.
It is simply not set at this point.
Signed-off-by: Oliver Barta
Fixes: ee5e5e7a5e0f ("drm/i915: Add HDCP framework + base implementation")
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++--
1 file changed, 2 insertions(+), 2
The check was always succeeding even in case of a mismatch
due to the HDCP_STATUS_ENC bit being set. Make sure both
bits are actually set.
Signed-off-by: Oliver Barta
Fixes: 2320175feb74 ("drm/i915: Implement HDCP for HDMI")
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
1 file changed,
On 25/02/2020 08:22, Chris Wilson wrote:
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson
---
Reorder
== Series Details ==
Series: series starting with [1/3] drm/i915: Replace the hardcoded
I915_FENCE_TIMEOUT
URL : https://patchwork.freedesktop.org/series/73914/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a337f6ea6d33 drm/i915: Replace the hardcoded I915_FENCE_TIMEOUT
On Tue, Feb 25, 2020 at 6:16 PM Daniel Vetter wrote:
>
> On Mon, Feb 24, 2020 at 07:46:59PM +0100, Christian König wrote:
> > Am 23.02.20 um 17:54 schrieb Thomas Hellström (VMware):
> > > On 2/23/20 4:45 PM, Christian König wrote:
> > > > Am 21.02.20 um 18:12 schrieb Daniel Vetter:
> > > > >
From: Ville Syrjälä
Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to
PIPE_MISC on tgl. Frob the new location.
Bspec does still document the old bits as well, so I left the code
for them as is until we get clarification from the hw folks on
whether the old bits still do
== Series Details ==
Series: drm/i915/perf: Mark up the racy use of perf->exclusive_stream
URL : https://patchwork.freedesktop.org/series/73905/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8004_full -> Patchwork_16703_full
On Wed, Feb 26, 2020 at 10:43 AM Hans de Goede wrote:
>
> Hi,
>
> On 2/26/20 4:29 PM, Alex Deucher wrote:
> > On Wed, Feb 26, 2020 at 10:16 AM Hans de Goede wrote:
> >>
> >> Hi Lyude and everyone else,
> >>
> >> Lyude I'm mailing you about this because you have done a lot of
> >> work on DP MST,
== Series Details ==
Series: drm/i915: Introduce i915 based i915_MISSING_CASE macro and us it in i915
URL : https://patchwork.freedesktop.org/series/73908/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f04e32590e91 drm/i915: Add i915 device based MISSING_CASE macro
-:23:
Hi,
On 2/26/20 4:29 PM, Alex Deucher wrote:
On Wed, Feb 26, 2020 at 10:16 AM Hans de Goede wrote:
Hi Lyude and everyone else,
Lyude I'm mailing you about this because you have done a lot of
work on DP MST, but if this rings a bell to anyone else feel
free to weigh in on this.
Might be a
On 2020-02-26 at 17:09:43 +0200, Ville Syrjälä wrote:
> On Tue, Feb 25, 2020 at 05:06:39PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 24, 2020 at 06:10:01PM +0530, Anshuman Gupta wrote:
> > > As a disabled pipe in pipe_mask is not having a valid intel crtc,
> > > driver wrongly populates the
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