[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74738/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16977_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for DP Phy compliance auto test (rev7)

== Series Details == Series: DP Phy compliance auto test (rev7) URL : https://patchwork.freedesktop.org/series/71121/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16976_full Summary ---

Re: [Intel-gfx] [PATCH v7 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

Hi Ankit, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip next-20200316] [cannot apply to v5.6-rc6] [if your patch is applied to the wrong git tree, please drop us a note to help improve

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)

== Series Details == Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3) URL : https://patchwork.freedesktop.org/series/74100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16974_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8139 -> Patchwork_16988 Summary

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup URL : https://patchwork.freedesktop.org/series/74759/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error:

[Intel-gfx] ✓ Fi.CI.BAT: success for Consider DBuf bandwidth when calculating CDCLK (rev2)

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16987 Summary ---

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Consider DBuf bandwidth when calculating CDCLK (rev2)

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Restore check for invalid vma for fencing

== Series Details == Series: drm/i915/gt: Restore check for invalid vma for fencing URL : https://patchwork.freedesktop.org/series/74758/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16985 Summary

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Cast remain to unsigned long in eb_relocate_vma (rev2)

== Series Details == Series: drm/i915: Cast remain to unsigned long in eb_relocate_vma (rev2) URL : https://patchwork.freedesktop.org/series/73440/ State : failure == Summary == Applying: drm/i915: Cast remain to unsigned long in eb_relocate_vma error: git diff header lacks filename

Re: [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register

On Mon, Mar 16, 2020 at 04:07:58PM +0530, Animesh Manna wrote: > DP_COMP_CTL and DP_COMP_PAT register used to program DP > compliance pattern. > > v1: Initial patch. > v2: used pipe instead of port in macro definition. [Manasi] > > Reviewed-by: Manasi Navare > Signed-off-by: Animesh Manna >

Re: [Intel-gfx] [PATCH 4/4] drm/i915/perf: add new open param to configure polling of OA buffer

On Thu, 12 Mar 2020 16:05:02 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > This new parameter let's the application choose how often the OA > buffer should be checked on the CPU side for data availability. Longer > polling period tend to reduce CPU overhead if the

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Restore check for invalid vma for fencing

== Series Details == Series: drm/i915/gt: Restore check for invalid vma for fencing URL : https://patchwork.freedesktop.org/series/74758/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: convert to struct drm_device based logging macros.

== Series Details == Series: drm/i915/gt: convert to struct drm_device based logging macros. URL : https://patchwork.freedesktop.org/series/74707/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16973_full

Re: [Intel-gfx] [PATCH v1 3/3] drm/i915: Remove unneeded hack now for CDCLK

On Mon, Mar 16, 2020 at 01:37:44PM +0200, Stanislav Lisovskiy wrote: > No need to bump up CDCLK now, as it is now correctly > calculated, accounting for DBuf BW as BSpec says. > > Signed-off-by: Stanislav Lisovskiy Logic looks good, Reviewed-by: Manasi Navare Manasi > --- >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16984

Re: [Intel-gfx] [PATCH v1 1/3] drm/i915: Decouple cdclk calculation from modeset checks

On Mon, Mar 16, 2020 at 01:37:42PM +0200, Stanislav Lisovskiy wrote: > We need to calculate cdclk after watermarks/ddb has been calculated > as with recent hw CDCLK needs to be adjusted accordingly to DBuf > requirements, which is not possible with current code organization. > > Setting CDCLK

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Try allocating va from free space

== Series Details == Series: drm/i915/gem: Try allocating va from free space URL : https://patchwork.freedesktop.org/series/74748/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16983 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : warning == Summary == $ dim checkpatch origin/drm-tip a3c39e8196a9 drm/i915/gem: Check for a closed context when looking up an engine

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v6,1/3] drm/i915/perf: remove generated code

== Series Details == Series: series starting with [v6,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74702/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16971_full

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Try allocating va from free space

== Series Details == Series: drm/i915/gem: Try allocating va from free space URL : https://patchwork.freedesktop.org/series/74748/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open

[Intel-gfx] [PATCH] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

As we store the handle lookup inside a radix tree, we do not need the gem_context->mutex except until we need to insert our lookup into the common radix tree. This takes a small bit of rearranging to ensure that the lut we insert into the tree is ready prior to actually inserting it (as soon as it

[Intel-gfx] [PATCH v2 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs

According to BSpec max BW per slice is calculated using formula Max BW = CDCLK * 64. Currently when calculating min CDCLK we account only per plane requirements, however in order to avoid FIFO underruns we need to estimate accumulated BW consumed by all planes(ddb entries basically) residing on

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/edp: Ignore short pulse when panel powered off (rev2)

== Series Details == Series: drm/i915/edp: Ignore short pulse when panel powered off (rev2) URL : https://patchwork.freedesktop.org/series/74265/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16970_full

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16982 Summary ---

Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: only append status when data is available

On Thu, 12 Mar 2020 16:05:01 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > The only bit of the status register we currently report in the > i915-perf stream is the "report loss" bit. Only report this when we > have some data to report with it. There was a kind of

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/dsi: Configure transcoder operation for command mode. Okay! Commit:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim checkpatch origin/drm-tip 006bc864d36a drm/i915/dsi: Configure transcoder operation for command mode. 01f67de3b52d drm/i915/dsi: Add

Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma

On Fri, Feb 14, 2020 at 7:36 AM Michel Dänzer wrote: > > On 2020-02-14 12:49 p.m., Jani Nikula wrote: > > On Fri, 14 Feb 2020, Chris Wilson wrote: > >> Quoting Jani Nikula (2020-02-14 06:36:15) > >>> On Thu, 13 Feb 2020, Nathan Chancellor wrote: > A recent commit in clang added

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev7)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev7) URL : https://patchwork.freedesktop.org/series/69980/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev3)

== Series Details == Series: drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev3) URL : https://patchwork.freedesktop.org/series/57989/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: DisplayID parser fixes

== Series Details == Series: drm/edid: DisplayID parser fixes URL : https://patchwork.freedesktop.org/series/74689/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16968_full Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74740/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16979

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74740/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file

[Intel-gfx] [CI] drm/i915/gt: Restore check for invalid vma for fencing

Apparently we do try and attach a fence to an invalid vma (during execbuf) so we cannot simply assert it never happens and report EINVAL instead. Fixes: dec9cf9ee8cb ("drm/i915/gt: Pull restoration of GGTT fences underneath the GT") Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala ---

Re: [Intel-gfx] [PATCH 02/10] drm/i915: Adjust PM QoS response frequency based on GPU load.

Francisco Jerez writes: > Tvrtko Ursulin writes: >[...] >> Some time ago we entertained the idea of GPU "load average", where that >> was defined as a count of runnable requests (so batch buffers). How >> that, more generic metric, would behave here if used as an input signal >> really

[Intel-gfx] ✗ Fi.CI.BAT: failure for Consider DBuf bandwidth when calculating CDCLK

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK URL : https://patchwork.freedesktop.org/series/74739/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16978 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74740/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2bf8a0072a07 drm/i915: Move GGTT fence registers under gt/ -:47:

Re: [Intel-gfx] [PATCH 2/4] drm/i915/perf: move pollin setup to non hw specific code

On Thu, 12 Mar 2020 16:05:00 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > This isn't really gen specific stuff, so just move it to the common > code. It seems pollin is not the only member which is not gen specific but is initialized in gen specific code. Anyway any other

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ dim checkpatch origin/drm-tip 70a984e1e806 drm/i915: Decouple cdclk calculation from modeset checks 01a1b24738fd drm/i915: Adjust

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74738/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16977

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74738/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74738/ State : warning == Summary == $ dim checkpatch origin/drm-tip 24d226d21d96 drm/i915: Move GGTT fence registers under gt/ -:47:

[Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7)

== Series Details == Series: DP Phy compliance auto test (rev7) URL : https://patchwork.freedesktop.org/series/71121/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16976 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH 1/4] drm/i915/perf: rework aging tail workaround

On Thu, 12 Mar 2020 16:04:59 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > We're about to introduce an options to open the perf stream, giving > the user ability to configure how often it wants the kernel to poll > the OA registers for available data. > > Right now the

[Intel-gfx] ✗ Fi.CI.BUILD: failure for tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests

== Series Details == Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests URL : https://patchwork.freedesktop.org/series/74730/ State : failure == Summary == Applying: tests/gem_userptr_blits: Refresh readonly-mmap-unsync exercise error: sha1 information is lacking

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915/perf: remove generated code

Looks good. Thanks for cleaning this up. With s/mutex_lock/mutex_unlock/ below: Reviewed-by: Umesh Nerlige Ramappa Thanks, Umesh On Sat, Mar 14, 2020 at 12:33:29PM +0200, Lionel Landwerlin wrote: A little bit of history : Back when i915-perf was introduced (4.13), there was no way to

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)

== Series Details == Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3) URL : https://patchwork.freedesktop.org/series/74100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16974

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)

== Series Details == Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3) URL : https://patchwork.freedesktop.org/series/74100/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3d21f79cfaf6 drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (v3)

Re: [Intel-gfx] [PATCH 2/2] drm/i915: move audio CDCLK constraint setup to bind/unbind

Hey Ville and others, On Fri, 13 Mar 2020, Kai Vehmanen wrote: > On Fri, 13 Mar 2020, Ville Syrjälä wrote: > Now thinking of another possibility, is it possible to hook code to > power-up of power domains? E.g. can I hook custom code which is executed [...] > If we could reprogram

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: convert to struct drm_device based logging macros.

== Series Details == Series: drm/i915/gt: convert to struct drm_device based logging macros. URL : https://patchwork.freedesktop.org/series/74707/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16973

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74703/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16972

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: convert to struct drm_device based logging macros.

== Series Details == Series: drm/i915/gt: convert to struct drm_device based logging macros. URL : https://patchwork.freedesktop.org/series/74707/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6cfa7991dd93 drm/i915/ggtt: convert to drm_device based logging macros. -:84:

[Intel-gfx] [PATCH] drm/i915/gem: Check for a closed context when looking up an engine

Beware that the context may already be closed as we try to lookup an engine. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1389 Fixes: 130a95e9098e ("drm/i915/gem: Consolidate ctx->engines[] release") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala ---

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74703/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74703/ State : warning == Summary == $ dim checkpatch origin/drm-tip cfd159dc30dd drm/i915: Move GGTT fence registers under gt/ -:6:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/3] drm/i915/perf: remove generated code

== Series Details == Series: series starting with [v6,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74702/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16971

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/3] drm/i915/perf: remove generated code

== Series Details == Series: series starting with [v6,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74702/ State : warning == Summary == $ dim checkpatch origin/drm-tip e31b72062fe2 drm/i915/perf: remove generated code -:24:

Re: [Intel-gfx] [RFC][PATCH 1/5] drm: Introduce scaling filter property

On Mon, Mar 16, 2020 at 09:31:32AM +0100, Daniel Vetter wrote: > On Tue, Mar 10, 2020 at 06:01:06PM +0200, Ville Syrjälä wrote: > > On Tue, Feb 25, 2020 at 12:35:41PM +0530, Pankaj Bharadiya wrote: > > > Introduce new scaling filter property to allow userspace to select > > > the driver's default

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: Ignore short pulse when panel powered off (rev2)

== Series Details == Series: drm/i915/edp: Ignore short pulse when panel powered off (rev2) URL : https://patchwork.freedesktop.org/series/74265/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16970

[Intel-gfx] [PATCH] drm/i915/gem: Try allocating va from free space

If the current node/entry location is occupied, and the object is not pinned, try assigning it some free space. We cannot wait here, so if in doubt, we unreserve and try to grab all at once. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 +++-- 1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: DisplayID parser fixes

== Series Details == Series: drm/edid: DisplayID parser fixes URL : https://patchwork.freedesktop.org/series/74689/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16968 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Port sync for skl+

== Series Details == Series: drm/i915: Port sync for skl+ URL : https://patchwork.freedesktop.org/series/74691/ State : failure == Summary == Applying: drm/i915/mst: Use .compute_config_late() to compute master transcoder Applying: drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it

Re: [Intel-gfx] [PATCH 1/6] lib/scatterlist: add sg_set_dma_addr() function

On Mon, Mar 16, 2020 at 10:41:42AM +0100, Christian König wrote: > Well I would prefer if the drivers can somehow express their requirements > and get IOVA structures already in the form they need. > > Converting the IOVA data from one form to another is sometimes quite costly. > Especially when

Re: [Intel-gfx] [PATCH 1/6] lib/scatterlist: add sg_set_dma_addr() function

On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote: > The non-page scatterlist is also a big concern for RDMA as we have > drivers that want the page list, so even if we did as this series > contemplates I'd have still have to split the drivers and create the > notion of a dma-only

Re: [Intel-gfx] [PATCH 1/6] lib/scatterlist: add sg_set_dma_addr() function

On Fri, Mar 13, 2020 at 09:17:42AM -0300, Jason Gunthorpe wrote: > On Fri, Mar 13, 2020 at 04:21:39AM -0700, Christoph Hellwig wrote: > > On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote: > > > The non-page scatterlist is also a big concern for RDMA as we have > > > drivers that

Re: [Intel-gfx] [PATCH] drm/i915/dp/mst : Get clock rate from sink's available PBN

On Wed, 2020-03-11, Lyude Paul wrote: >On Tue, 2020-01-07 at 01:41 +0800, Lee Shawn C wrote: >> Driver report physcial bandwidth for max dot clock rate. >> It would caused compatibility issue sometimes when physical bandwidth >> exceed MST hub output ability. >> >> For example, here is a MST

Re: [Intel-gfx] [PATCH v7 1/3] drm/i915: Get active pending request for given context

Quoting Ankit Navik (2020-03-16 13:29:49) > This patch gives us the active pending request count which is yet > to be submitted to the GPU. > > V2: > * Change 64-bit to atomic for request count. (Tvrtko Ursulin) > > V3: > * Remove mutex for request count. > * Rebase. > * Fixes hitting

[Intel-gfx] [PATCH v7 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration

[Intel-gfx] [PATCH v7 3/3] drm/i915: Predictive governor to control slice/subslice/eu

Load classification is used for predictive governor to control eu/slice/subslice based on workloads. sysfs is provided to enable/disable the feature V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum config. (Tvrtko

[Intel-gfx] [PATCH v7 0/3] Dynamic EU configuration of Slice/Sub-slice/EU

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS.

[Intel-gfx] [PATCH v7 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase.

[Intel-gfx] [PATCH v7 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration

[Intel-gfx] [PATCH v7 0/3] drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel

This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS. ---| App /KPI| % Power Benefit (mW)

[Intel-gfx] [PATCH v7 3/3] drm/i915: Predictive governor to control slice/subslice/eu

Load classification is used for predictive governor to control eu/slice/subslice based on workloads. sysfs is provided to enable/disable the feature V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum config. (Tvrtko

[Intel-gfx] [PATCH v7 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase.

Re: [Intel-gfx] Fixes that failed to apply to v5.6-rc3

On Thu, 27 Feb 2020, Jani Nikula wrote: > Hi all - > > The following commits have been marked as Cc: stable or fixing something > in v5.6-rc3 or earlier, but failed to cherry-pick to > drm-intel-fixes. Please see if they are worth backporting, and please do > so if they are. New ones for -rc6:

Re: [Intel-gfx] [PATCH i-g-t 1/2] intel-ci: Tweak blacklist for very long running stability tests

On Mon, Mar 16, 2020 at 10:54:26AM +, Chris Wilson wrote: > To exclude yynamic tests just use their group name? Yes, the igt_subtest_with_dynamic("somename") macro creates a subtest entry point just like igt_subtest, for the purposes of testlists and blacklists. > > Signed-off-by: Chris

[Intel-gfx] [PATCH 12/15] drm/i915/gem: Split eb_vma into its own allocation

Use a separate array allocation for the execbuf vma, so that we can track their lifetime independently from the copy of the user arguments. With luck, this has a secondary benefit of splitting the malloc size to within reason and avoid vmalloc. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 04/15] drm/i915/gt: Allocate i915_fence_reg array

Since the number of fence regs can vary dramactically between platforms, allocate the array on demand so we don't waste as much space. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 --

[Intel-gfx] [PATCH 03/15] drm/i915: Remove manual save/resume of fence register state

Since we always reload the fence register state on runtime resume, having it explicitly in the S0ix resume code is redundant. Indeed, it is not even being used! Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 1 - 1 file changed, 1 deletion(-) diff

[Intel-gfx] [PATCH 02/15] drm/i915/gt: Pull restoration of GGTT fences underneath the GT

Make the GT responsible for restoring its fence when it wakes up from suspend. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 + drivers/gpu/drm/i915/i915_drv.c | 4

[Intel-gfx] [PATCH 14/15] drm/i915/gem: Asynchronous GTT unbinding

It is reasonably common for userspace (even modern drivers like iris) to reuse an active address for a new buffer. This would cause the application to stall under its mutex (originally struct_mutex) until the old batches were idle and it could synchronously remove the stale PTE. However, we can

[Intel-gfx] [PATCH 13/15] drm/i915/gem: Separate the ww_mutex walker into its own list

In preparation for making eb_vma bigger and heavy to run inn parallel, we need to stop apply an in-place swap() to reorder around ww_mutex deadlocks. Keep the array intact and reorder the locks using a dedicated list. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c

[Intel-gfx] [PATCH 07/15] drm/i915/gt: Make fence revocation unequivocal

If we must revoke the fence because the VMA is no longer present, or because the fence no longer applies, ensure that we do and convert it into an error if we try but cannot. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 21 +++-

[Intel-gfx] [PATCH 01/15] drm/i915: Move GGTT fence registers under gt/

Since the fence registers control HW detiling through the GGTT aperture, make them a part of the intel_ggtt under gt/ Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-

[Intel-gfx] [PATCH 05/15] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence

Only GPU activity via the GGTT fence is asynchronous, we know that we control the CPU access directly, so we only need to wait for the GPU to stop using the fence before we relinquish it. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 12

[Intel-gfx] [PATCH 08/15] drm/i915/gem: Drop cached obj->bind_count

We cached the number of vma bound to the object in order to speed up shrinker decisions. This has been superseded by being more proactive in removing objects we cannot shrink from the shrinker lists, and so we can drop the clumsy attempt at atomically counting the bind count and comparing it to

[Intel-gfx] [PATCH 06/15] drm/i915/gt: Store the fence details on the fence

Make a copy of the object tiling parameters at the point of grabbing the fence. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 93 +++- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 4 + 2 files changed, 37 insertions(+), 60 deletions(-) diff

[Intel-gfx] [PATCH 11/15] drm/i915: Export a preallocate variant of i915_active_acquire()

Sometimes we have to be very careful not to allocate underneath a mutex (or spinlock) and yet still want to track activity. Enter i915_active_acquire_for_context(). This raises the activity counter on i915_active prior to use and ensures that the fence-tree contains a slot for the context.

[Intel-gfx] [PATCH 15/15] drm/i915/gem: Bind the fence async for execbuf

It is illegal to wait on an another vma while holding the vm->mutex, as that easily leads to ABBA deadlocks (we wait on a second vma that waits on us to release the vm->mutex). So while the vm->mutex exists, move the waiting outside of the lock into the async binding pipeline. Signed-off-by:

[Intel-gfx] [PATCH 09/15] drm/i915: Immediately execute the fenced work

If the caller allows and we do not have to wait for any signals, immediately execute the work within the caller's process. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_sw_fence_work.c | 6 +-

[Intel-gfx] [PATCH 10/15] drm/i915/gem: Assign context id for async work

Allocate a few dma fence context id that we can use to associate async work [for the CPU] launched on behalf of this context. For extra fun, we allow a configurable concurrency width. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4

[Intel-gfx] [PATCH v1 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs

According to BSpec max BW per slice is calculated using formula Max BW = CDCLK * 64. Currently when calculating min CDCLK we account only per plane requirements, however in order to avoid FIFO underruns we need to estimate accumulated BW consumed by all planes(ddb entries basically) residing on

[Intel-gfx] [PATCH v1 0/3] Consider DBuf bandwidth when calculating CDCLK

We need to calculate cdclk after watermarks/ddb has been calculated as with recent hw CDCLK needs to be adjusted accordingly to DBuf requirements, which is not possible with current code organization. Setting CDCLK according to DBuf BW requirements and not just rejecting if it doesn't satisfy BW

[Intel-gfx] [PATCH v1 3/3] drm/i915: Remove unneeded hack now for CDCLK

No need to bump up CDCLK now, as it is now correctly calculated, accounting for DBuf BW as BSpec says. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_cdclk.c | 12 1 file changed, 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c

[Intel-gfx] [PATCH v1 1/3] drm/i915: Decouple cdclk calculation from modeset checks

We need to calculate cdclk after watermarks/ddb has been calculated as with recent hw CDCLK needs to be adjusted accordingly to DBuf requirements, which is not possible with current code organization. Setting CDCLK according to DBuf BW requirements and not just rejecting if it doesn't satisfy BW

[Intel-gfx] [CI 2/4] drm/i915/gt: Pull restoration of GGTT fences underneath the GT

Make the GT responsible for restoring its fence when it wakes up from suspend. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 + drivers/gpu/drm/i915/i915_drv.c | 4

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