Re: [Intel-gfx] [PATCH v4] drm/i915: Synchronize active and retire callbacks

Chris, Could you please take a look at this? This really is quite an important fix. Thanks, Sultan ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev18)

== Series Details == Series: SAGV support for Gen12+ (rev18) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8289_full -> Patchwork_17276_full Summary --- **SUCCESS

Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Reduce cpu overhead for blocking perf OA reads

On Mon, 13 Apr 2020 08:48:20 -0700, Umesh Nerlige Ramappa wrote: > > A condition in wait_event_interruptible seems to be checked twice before > waiting on the event to occur. These checks are redundant when hrtimer > events will call oa_buffer_check_unlocked to update the oa_buffer tail > pointers.

[Intel-gfx] [PATCH v4 2/3] drm/i915/dp: Attach and set drm connector VRR property

From: Aditya Swarup This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (M

[Intel-gfx] [PATCH v4 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD

DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate t

[Intel-gfx] [PATCH v4 3/3] drm/i915/dp: Expose connector VRR info via debugfs

From: Bhanuprakash Modem [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "i915_vrr_info". Example usage: cat /sys/kernel/debug/dri/0/DP-1/i915_vrr_info v3: * Remove the unnecessary de

Re: [Intel-gfx] [PATCH 3/6] i915/gvt: remove unused xen bits

On 2020.04.13 15:08:06 +0200, Christoph Hellwig wrote: > On Wed, Apr 08, 2020 at 09:44:37AM +0800, Zhenyu Wang wrote: > > On 2020.04.04 11:40:58 +0200, Christoph Hellwig wrote: > > > No Xen support anywhere here. Remove a dead declaration and an unused > > > include. > > > > > > Signed-off-by: Ch

[Intel-gfx] [drm-tip:drm-tip 6/8] drivers/rtc/rtc-cmos.c:655:16: error: redefinition of 'flags'

tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip head: 636ab52e6d1d7aced9620f16da90d4c3c5fcadf5 commit: 213a0a26eba646607e88120c3fd27dc32b03e1f0 [6/8] Merge remote-tracking branch 'drm-intel/topic/core-for-CI' into drm-tip config: x86_64-defconfig (attached as .config) compiler: clang v

Re: [Intel-gfx] [PATCH 2/6] i915/gvt/kvm: a NULL ->mm does not mean a thread is a kthread

On Mon, Apr 13, 2020 at 03:27:30PM +0200, Christoph Hellwig wrote: > On Mon, Apr 06, 2020 at 11:08:46PM -0400, Yan Zhao wrote: > > hi > > we were removing this code. see > > https://lore.kernel.org/kvm/20200313031109.7989-1-yan.y.z...@intel.com/ > > This didn't make 5.7-rc1. > > > The implementat

[Intel-gfx] [PATCH 2/2] Revert "rtc/cmos: Protect rtc_lock from interrupts"

Fix build. This reverts commit 5b39064d452ac9739d59c5183c8a7c90a5982acb. Signed-off-by: José Roberto de Souza --- drivers/rtc/rtc-cmos.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index df5ff7e78a14..3718386a9f0e 1006

[Intel-gfx] [PATCH 1/2] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it

Right now dp.regs.dp_tp_ctl/status are only set during the encoder pre_enable() hook, what is causing all reads and writes to those registers to go to offset 0x0 before pre_enable() is executed. So if i915 takes the BIOS state and don't do a modeset any following link retraing will fail. In the c

Re: [Intel-gfx] [PATCH v5 3/4] drm/i915/perf: prepare driver to receive multiple ctx handles

On Thu, Apr 09, 2020 at 12:17:05PM +0300, Lionel Landwerlin wrote: Make all the internal necessary changes before we flip the switch. v2: Use an unlimited number of intel contexts (Chris) v3: Handle GEM context with multiple RCS0 logical contexts (Chris) Signed-off-by: Lionel Landwerlin --- d

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/perf: break OA config buffer object in 2

Hi Lionel, What's the implication of using separate contexts for 3d and compute on perf OA? Is it only context-filtering? If so, have you considered disabling context filtering with a parameter instead of actually filtering for specific contexts? Is this privileged use case? Thanks, Umesh O

Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers

On Wed, Apr 08, 2020 at 04:42:01PM -0700, Ashutosh Dixit wrote: > It is wrong to block the user thread in the next poll when OA data is > already available which could not fit in the user buffer provided in > the previous read. In several cases the exact user buffer size is not > known. Blocking us

[Intel-gfx] [PATCH] drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam

Looks like I accidentally made it so you couldn't force DPCD backlight support on, whoops. Fix that. Signed-off-by: Lyude Paul Fixes: 17f5d57915be ("drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel") Cc: Adam Jackson Cc: Jani Nikula Cc: Joonas Lahtinen Cc: "Ville Syrj

Re: [Intel-gfx] [PATCH] drm/i915/ehl: extended Wa_2006604312 to ehl

On Mon, Apr 13, 2020 at 01:53:22PM -0400, Matt Atwood wrote: > Reflect recent bspec changes. > > Bspec: 33451 > > Signed-off-by: Matt Atwood Matches the updated spec. Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 > 1 file changed, 4 insertions(+)

[Intel-gfx] [PATCH] drm/i915/ehl: extended Wa_2006604312 to ehl

Reflect recent bspec changes. Bspec: 33451 Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_display.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7

Re: [Intel-gfx] [PATCH] drm/i915/gvt: Use ARRAY_SIZE instead of hardcoded size

On Mon, 2020-04-13 at 22:32 +0800, Jason Yan wrote: > Fix the following coccicheck warning: > > drivers/gpu/drm/i915/gvt/vgpu.c:127:30-31: WARNING: Use ARRAY_SIZE > > Signed-off-by: Jason Yan > --- > drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > di

[Intel-gfx] [PATCH 05/26] capabilities: Introduce CAP_PERFMON to kernel and user space

From: Alexey Budankov Introduce the CAP_PERFMON capability designed to secure system performance monitoring and observability operations so that CAP_PERFMON can assist CAP_SYS_ADMIN capability in its governing role for performance monitoring and observability subsystems. CAP_PERFMON hardens syst

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix ref->mutex deadlock in i915_active_wait()

On Fri, Apr 10, 2020 at 11:08:38AM +0200, Greg KH wrote: > On Tue, Apr 07, 2020 at 12:18:09AM -0700, Sultan Alsawaf wrote: > > From: Sultan Alsawaf > > > > The following deadlock exists in i915_active_wait() due to a double lock > > on ref->mutex (call chain listed in order from top to bottom): >

[Intel-gfx] [PATCH 11/26] powerpc/perf: open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the pri

[Intel-gfx] [PATCH 16/26] doc/admin-guide: update kernel.rst with CAP_PERFMON information

From: Alexey Budankov Update the kernel.rst documentation file with the information related to usage of CAP_PERFMON capability to secure performance monitoring and observability operations in system. Signed-off-by: Alexey Budankov Cc: Alexei Starovoitov Cc: Andi Kleen Cc: Igor Lubashev Cc: J

[Intel-gfx] [PATCH 09/26] drm/i915/perf: Open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to i915_perf monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implement

[Intel-gfx] [PATCH] drm/i915/gvt: Use ARRAY_SIZE instead of hardcoded size

Fix the following coccicheck warning: drivers/gpu/drm/i915/gvt/vgpu.c:127:30-31: WARNING: Use ARRAY_SIZE Signed-off-by: Jason Yan --- drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vg

[Intel-gfx] [PATCH 14/26] drivers/oprofile: Open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the pri

[Intel-gfx] [PATCH 10/26] trace/bpf_trace: Open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to bpf_trace monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implement

[Intel-gfx] [PATCH 07/26] perf/core: open access to probes for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring via kprobes and uprobes and eBPF tracing for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix ref->mutex deadlock in i915_active_wait()

On Fri, Apr 10, 2020 at 11:08:38AM +0200, Greg KH wrote: > On Tue, Apr 07, 2020 at 12:18:09AM -0700, Sultan Alsawaf wrote: > > From: Sultan Alsawaf > > > > The following deadlock exists in i915_active_wait() due to a double lock > > on ref->mutex (call chain listed in order from top to bottom): >

[Intel-gfx] [PATCH 06/26] perf/core: Open access to the core for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring of kernel code, CPUs, tracepoints and namespaces data for a CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes

[Intel-gfx] [PATCH 15/26] doc/admin-guide: Update perf-security.rst with CAP_PERFMON information

From: Alexey Budankov Update perf-security.rst documentation file with the information related to usage of CAP_PERFMON capability to secure performance monitoring and observability operations in system. Committer notes: While testing 'perf top' under cap_perfmon I noticed that it needs some mor

[Intel-gfx] [PATCH 08/26] perf tools: Support CAP_PERFMON capability

From: Alexey Budankov Extend error messages to mention CAP_PERFMON capability as an option to substitute CAP_SYS_ADMIN capability for secure system performance monitoring and observability operations. Make perf_event_paranoid_check() and __cmd_ftrace() to be aware of CAP_PERFMON capability. CAP_

[Intel-gfx] [PATCH 13/26] drivers/perf: Open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the pri

[Intel-gfx] [PATCH 12/26] parisc/perf: open access for CAP_PERFMON privileged process

From: Alexey Budankov Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the pri

[Intel-gfx] [PATCH v4 5/9] drm/i915/tc: Skip ref held check for TC legacy aux power wells

As part of ICL TC cold exit sequences we need to request aux power well before lock the access to TC ports, so skiping the intel_tc_port_ref_held() check for TC legacy ports. Reviewed-by: Imre Deak Tested-by: You-Sheng Yang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/

[Intel-gfx] [PATCH v4 7/9] drm/i915/tc: Catch TC users accessing FIA registers without enable aux

As described in "drm/i915/tc/icl: Implement TC cold sequences" users of TC functions should held aux power well during access to avoid read garbage due HW in TC cold state. v3: - renamed is_tc_cold_blocked() to assert_tc_cold_blocked() - restored the removed 0x checks Reviewed-by: Imre De

[Intel-gfx] [PATCH v4 9/9] drm/i915: Add missing deinitialization cases of load failure

The intel_display_power_put_async() used in TC cold sequences made easy to hit the missing deinitialization of driver in case of load failure as seen in the stack trace bellow. intel_modeset_driver_remove_noirq() had to be removed from i915_driver_modeset_remove_noirq() as those are different init

[Intel-gfx] [PATCH v4 2/9] drm/i915/display: Add intel_legacy_aux_to_power_domain()

This is a similar function to intel_aux_power_domain() but it do not care about TBT ports, this will be needed by ICL TC sequences. v2: - renamed to intel_legacy_aux_to_power_domain() Cc: Imre Deak Cc: Cooper Chiou Cc: Kai-Heng Feng Reviewed-by: Imre Deak Tested-by: You-Sheng Yang Signed-off

[Intel-gfx] [PATCH v4 3/9] drm/i915/display: Split hsw_power_well_enable() into two

This is a preparation for ICL TC cold exit sequences. v2: - renamed new functions to hsw_power_well_enable_prepare()/complete() Signed-off-by: José Roberto de Souza Reviewed-by: Imre Deak Tested-by: You-Sheng Yang --- .../drm/i915/display/intel_display_power.c| 39 +++ 1 f

[Intel-gfx] [PATCH v4 4/9] drm/i915/tc/icl: Implement TC cold sequences

This is required for legacy/static TC ports as IOM is not aware of the connection and will not trigger the TC cold exit. Just request PCODE to exit TCCOLD is not enough as it could enter again before driver makes use of the port, to prevent it BSpec states that aux powerwell should be held. So he

[Intel-gfx] [PATCH v4 1/9] drm/i915/display: Move out code to return the digital_port of the aux ch

Moving the code to return the digital port of the aux channel also removing the intel_phy_is_tc() to make it generic. digital_port will be needed in icl_tc_phy_aux_power_well_enable() so adding it as a parameter to icl_tc_port_assert_ref_held(). While at at removing the duplicated call to icl_tc_p

[Intel-gfx] [PATCH v4 6/9] drm/i915/tc/tgl: Implement TC cold sequences

TC ports can enter in TCCOLD to save power and is required to request to PCODE to exit this state before use or read to TC registers. For TGL there is a new MBOX command to do that with a parameter to ask PCODE to exit and block TCCOLD entry or unblock TCCOLD entry. So adding a new power domain t

[Intel-gfx] [PATCH v4 8/9] drm/i915/tc: Do not warn when aux power well of static TC ports timeout

This is a expected timeout of static TC ports not conneceted, so not throwing warnings that would taint CI. v3: - moved checks to tc_phy_aux_timeout_expected() v4: - moved and add comments to tc_phy_aux_timeout_expected() Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_disp

[Intel-gfx] [PATCH 1/3] drm/i915/perf: Reduce cpu overhead for blocking perf OA reads

A condition in wait_event_interruptible seems to be checked twice before waiting on the event to occur. These checks are redundant when hrtimer events will call oa_buffer_check_unlocked to update the oa_buffer tail pointers. The redundant checks add cpu overhead. Simplify the check to reduce cpu ov

[Intel-gfx] [PATCH 3/3] drm/i915/perf: add interrupt enabling parameter

From: Lionel Landwerlin This let's the application choose to be driven by the interrupt mechanism of the HW. In conjunction with long periods for checks for the availability of data on the CPU, this can reduce the CPU load when doing capture of OA data. v2: Version the new parameter (Joonas) v3:

[Intel-gfx] [PATCH 0/3] drm/i915/perf: add OA interrupt support

Hi all, This is a revival of an earlier patch series submitted by Lionel Landwerlin - https://patchwork.freedesktop.org/series/54280/ The patches enable interrupt support for the perf OA unit in i915, further details can be found in the orignal series linked above. This series was split into 2.

[Intel-gfx] [PATCH 2/3] drm/i915: handle interrupts from the OA unit

From: Lionel Landwerlin The OA unit can notify that its circular buffer is half full through an interrupt and we would like to give the application the ability to make use of this interrupt to get rid of CPU checks on the OA buffer. This change wires up the interrupt to the i915-perf stream and

Re: [Intel-gfx] [PATCH 2/6] i915/gvt/kvm: a NULL ->mm does not mean a thread is a kthread

On Mon, Apr 06, 2020 at 11:08:46PM -0400, Yan Zhao wrote: > hi > we were removing this code. see > https://lore.kernel.org/kvm/20200313031109.7989-1-yan.y.z...@intel.com/ This didn't make 5.7-rc1. > The implementation of vfio_dma_rw() has been in vfio next tree. > https://github.com/awilliam/linu

Re: [Intel-gfx] [PATCH 3/6] i915/gvt: remove unused xen bits

On Wed, Apr 08, 2020 at 09:44:37AM +0800, Zhenyu Wang wrote: > On 2020.04.04 11:40:58 +0200, Christoph Hellwig wrote: > > No Xen support anywhere here. Remove a dead declaration and an unused > > include. > > > > Signed-off-by: Christoph Hellwig > > --- > > We'll keep that off-tree. > > Acked-

[Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges

Some workarounds are not sticking across suspend resume cycles. The forcewake ranges table has been updated and would reflect the hardware appropriately. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222 Cc: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/int

[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev18)

== Series Details == Series: SAGV support for Gen12+ (rev18) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8289 -> Patchwork_17276 Summary --- **SUCCESS** No r

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for SAGV support for Gen12+ (rev18)

Yes, we have a bug. I have re-reported the series. Hopefully this goes successful. Lakshmi. -Original Message- From: Lisovskiy, Stanislav Sent: Monday, April 13, 2020 10:19 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana ; Peres, Martin Subject: Re: ✗ Fi.CI.BAT: failure

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for SAGV support for Gen12+ (rev18)

self_test is broken, not related to SAGV anyhow - do we have a bug? Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Patchwork Sent: Saturday, April 11, 2020 10:26:05 AM To: Lisovskiy,

[Intel-gfx] [PATCH v6] drm/i915: Add Plane color encoding support for YCBCR_BT2020

Currently the plane property doesn't have support for YCBCR_BT2020, which enables the corresponding color conversion mode on plane CSC. Enabling the plane property for the planes for GLK & ICL+ platforms. Also as per spec, update the Plane Color CSC from YUV601_TO_RGB709 to YUV601_TO_RGB601. V2: E