On Wed, May 20, 2020 at 9:05 PM Daniel Vetter wrote:
>
> On Thu, May 14, 2020 at 02:38:38PM +0300, Oded Gabbay wrote:
> > On Tue, May 12, 2020 at 9:12 AM Daniel Vetter
> > wrote:
> > >
> > > On Tue, May 12, 2020 at 4:14 AM Dave Airlie wrote:
> > > >
> > > > On Mon, 11 May 2020 at 19:37, Oded Ga
On Wed, 2020-05-20 at 11:45 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Wa_22010271021 (rev2)
> URL : https://patchwork.freedesktop.org/series/77428/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17716_full
> ==
From: Sean Paul
If userspace sets the CP property to DESIRED while it's already ENABLED,
the driver will try to re-enable HDCP. On some displays, this will
result in R0' mismatches. I'm guessing this is because the display is
still sending back Ri instead of re-authenticating.
At any rate, we ca
On Wed, May 20, 2020 at 9:08 AM Sean Paul wrote:
>
> From: Sean Paul
>
> We're seeing some R0' mismatches in the field, particularly with
> repeaters. I'm guessing the (already lenient) 300ms wait time isn't
> enough for some setups. So add an additional wait when R0' is
> mismatched.
>
I think
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev15)
URL : https://patchwork.freedesktop.org/series/74739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17718_full
Summa
We have traces for the semaphore and the error, but not the far more
frequent CS interrupts. This is likely to be too much, but for the
purpose of live_unlite_preempt it may answer a question or two.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
drivers/gpu/d
== Series Details ==
Series: drm/i915/hdcp: Avoid duplicate HDCP enables
URL : https://patchwork.freedesktop.org/series/77487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17734
Summary
---
**SUCCE
Since the worker may rearm, we currently are only guaranteed to flush
the work if we cancel the timer. If the work was running at the time we
try and cancel it, we will wait for it to complete, but it may leave
items in the pool and requeue the work. If we rearrange the immediate
discard of the poo
== Series Details ==
Series: series starting with [01/22] drm/i915/gem: Suppress some random warnings
URL : https://patchwork.freedesktop.org/series/77459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17724_full
=
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev5)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17735
Summary
---
**SUCCES
== Series Details ==
Series: drm/i915/gt: Cancel the flush worker more thoroughly
URL : https://patchwork.freedesktop.org/series/77490/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3dd258ba778 drm/i915/gt: Cancel the flush worker more thoroughly
-:13: WARNING:COMMIT_LOG_LONG_
== Series Details ==
Series: drm/i915/gt: Cancel the flush worker more thoroughly
URL : https://patchwork.freedesktop.org/series/77490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17736
Summary
---
This parameter is meant to be used when PSR issues are found as some
issues in the past was due wrong values set in VBT so this would be
a quick and easy way to ask users or for us to check if the issue is
due VBT values.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev6)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17737
Summary
---
**SUCCES
== Series Details ==
Series: drm/i915: Add psr_safest_params
URL : https://patchwork.freedesktop.org/series/77491/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7f3095d8f257 drm/i915: Add psr_safest_params
-:98: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthes
== Series Details ==
Series: drm/i915: Add psr_safest_params
URL : https://patchwork.freedesktop.org/series/77491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17738
Summary
---
**SUCCESS**
No r
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev7)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17739
Summary
---
**SUCCES
== Series Details ==
Series: drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
URL : https://patchwork.freedesktop.org/series/77462/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17726_full
=
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is used all across the code
base to rather signify a range of gens. So add a fake one for DG1 to be
used where needed.
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/d
From: Aditya Swarup
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/d
RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of view, but
that does not happ
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the inde
From: Matthew Auld
Gen 12 dgfx devices are coherent with system memory even over PCIe.
Therefore supporting coherent userptr should be possible.
Cc: Stuart Summers
Signed-off-by: Matthew Auld
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
drivers/gpu/
From: Matt Roper
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Stuart Summers
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions
From: Matt Atwood
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper
Signed-off-by: Matt Atwood
Signed-off-by: Lucas De Marchi
---
From: Matt Roper
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
From: Fernando Pacheco
Correctable and uncorrectable Shared Local Memory (SLM)
ECC errors will be counted in two different Thread Dispatch
Logic (TDL) registers. GuC will receive a message
from TDL when the first correctable/uncorrectable error is
detected by SLM (first after a reset or register
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather and we don't need to read
fuse straps like on CNP+. frequencies on CNP+. Note that register bits
associated with this frequency confusingly use 37 for the divider field
rather than 38 as you might expect.
For simplicity, let's just assum
Return the old value read so some places of the code can still do the
rmw but add warnings/errors about the value it read.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_de.h | 4 ++--
drivers/gpu/drm/i915/intel_uncore.h | 10 +++---
2 files changed, 9 insertions(
From: Venkata Sandeep Dhanalakota
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio
Cc: Michael J. Ruhl
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4 insertions
From: Matt Roper
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
Bspec: 49189
Bspec: 53707
Cc:
From: Abdiel Janulgue
Bspec: 44463
Cc: Matthew Auld
Cc: James Ausmus
Cc: Joonas Lahtinen
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
include/drm/i915_pciids.h | 4
2 files changed, 6 insertions(+), 1
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.
While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it coul
From: Abdiel Janulgue
Bspec: 33617, 33617
Cc: José Roberto de Souza
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Vanshidhar Konda
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_d
From: Matt Roper
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Rev
From: Aditya Swarup
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
driver
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
>From spec we have registers GPIO_CTL[1-4], so we should not do t
From: Matt Roper
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/i
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshak
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 57 +
drivers/gpu/drm/i915/i915_reg.h |
From: Matt Roper
Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register. Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.
Bsp
From: Fernando Pacheco
The error detection and correction capability
for GRF and instruction cache (IC) will utilize
the new interrupt and error handling infrastructure
for dgfx products. The GFX device can generate
a number of classes of error under the new
infrastructure: correctable, non-fatal
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functio
From: Stuart Summers
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
Cc: Matt Atwood
Cc: Matt Roper
Cc: Radhakrishna Sripada
Cc: José Roberto
From: Aditya Swarup
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display
From: Anusha Srivatsa
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed, 2
From: Matt Roper
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
log
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
Cc: Radhakrishna Sripada
Cc: Daniele Spurio Ceraolo
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56 ++
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Matt Roper
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-23-matthew.d.ro...@intel.com
---
drivers/gp
From: Matt Roper
RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
Bspec: 49181
Cc: Imre Deak
Cc: Aditya Swarup
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-14-matthew.d.ro...@intel.com
---
dri
From: Uma Shankar
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB
From: Aditya Swarup
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
driver
From: Clinton A Taylor
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 4
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 8 inse
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eb8bcc051bcb drm/i915/rkl: Add DPLL4 support
8eb7430370e7 drm/i915/rkl: Add DDC pin mapping
470f943d8711 drm/i915/rkl: Setup ports/phys
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/77496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17740
Summary
---
**SUCCESS**
No regressions found.
== Series Details ==
Series: series starting with [1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/77366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17728_full
=
== Series Details ==
Series: drm: Replace deprecated function in drm_crtc_helper
URL : https://patchwork.freedesktop.org/series/77467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17729_full
Summary
On 2020-05-20 at 15:47:44 -0400, Sean Paul wrote:
> From: Sean Paul
>
> If userspace sets the CP property to DESIRED while it's already ENABLED,
> the driver will try to re-enable HDCP. On some displays, this will
> result in R0' mismatches. I'm guessing this is because the display is
> still sen
On 2020-05-20 at 15:50:15 -0400, Sean Paul wrote:
> On Wed, May 20, 2020 at 9:08 AM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > We're seeing some R0' mismatches in the field, particularly with
> > repeaters. I'm guessing the (already lenient) 300ms wait time isn't
> > enough for some setups.
== Series Details ==
Series: drm/i915/hdcp: Avoid duplicate HDCP enables (rev2)
URL : https://patchwork.freedesktop.org/series/77487/
State : failure
== Summary ==
Applying: drm/i915/hdcp: Avoid duplicate HDCP enables
error: patch failed: drivers/gpu/drm/drm_atomic_uapi.c:746
error: drivers/gp
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait (rev2)
URL : https://patchwork.freedesktop.org/series/77439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17731_full
Summary
--
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10)
URL : https://patchwork.freedesktop.org/series/73036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17732_full
This is a permanent w/a for JSL/EHL.This is to be applied to the
PCH types on JSL/EHL ie JSP/MCC
Bspec: 52888
v2: Fixed the wrong usage of logical OR(ville)
v3: Removed extra braces, changed the check(jose)
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/i915_irq.c | 6 --
1 fil
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev18)
URL : https://patchwork.freedesktop.org/series/74739/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17733_full
Summa
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