== Series Details ==
Series: drm/i915: Restore DP-E to VBT mapping table
URL : https://patchwork.freedesktop.org/series/78060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8595_full -> Patchwork_17896_full
Summary
---
== Series Details ==
Series: Remaining RKL patches (rev2)
URL : https://patchwork.freedesktop.org/series/77971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8595_full -> Patchwork_17895_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Restore DP-E to VBT mapping table
URL : https://patchwork.freedesktop.org/series/78060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8595 -> Patchwork_17896
Summary
---
== Series Details ==
Series: Remaining RKL patches (rev2)
URL : https://patchwork.freedesktop.org/series/77971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8595 -> Patchwork_17895
Summary
---
**SUCCESS**
No
On Fri, Jun 05, 2020 at 11:11:23PM +0100, Chris Wilson wrote:
> Quoting Matt Roper (2020-06-04 17:39:16)
> > On Thu, Jun 04, 2020 at 08:34:04AM +, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: Remaining RKL patches
> > > URL :
We accidentally dropped matching for DVO_PORT_DPE from the VBT mapping
table when we refactored the function. Restore it.
Fixes: 4628142aeccc ("drm/i915/rkl: provide port/phy mapping for vbt")
Cc: Lucas De Marchi
Cc: Matt Roper
Cc: Ville Syrjälä
Cc: Chris Wilson
Signed-off-by: Matt Roper
== Series Details ==
Series: Remaining RKL patches (rev2)
URL : https://patchwork.freedesktop.org/series/77971/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
v2:
- Fix minor checkpatch warnings
Bspec:
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18
From: Aditya Swarup
RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
transcoder registers.
v2(MattR):
- Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask
against the platform's cpu_transcoder_mask to filter out the ones
that don't exist on a given
HPD pin handling for RKL+TGP is a special case; we effectively select
the HPD pin based on the DDI (A,B,D,E) rather than the PHY (A,B,C,D).
This differs from the regular behavior of RKL+CMP (and also TGL+TGP).
v2:
- Rather than providing a custom hpd_pin mapping table, just assign
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.
v2:
-
Key deltas from v3:
- Squashed ABOX_CTL and BW_BUDDY patches into a single patch that uses
a single abox_mask field in the device_info structure. A special
case is added to also program the abox0 instance of ABOX_CTL on
gen12, even on platforms that use abox1+abox2 instead.
- Fixed DSI
Rocket Lake uses the same 'abox0' mechanism to handle pixel data
transfers from memory that gen11 platforms used, rather than the
abox1/abox2 interfaces used by TGL/DG1. For the most part this is a
hardware implementation detail that's transparent to driver software,
but we do have to program a
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +
2 files
== Series Details ==
Series: drm/i915/gem: Delete unused code
URL : https://patchwork.freedesktop.org/series/78055/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8594_full -> Patchwork_17894_full
Summary
---
== Series Details ==
Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2)
URL : https://patchwork.freedesktop.org/series/77964/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8593_full -> Patchwork_17893_full
Quoting Matt Roper (2020-06-04 17:39:16)
> On Thu, Jun 04, 2020 at 08:34:04AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: Remaining RKL patches
> > URL : https://patchwork.freedesktop.org/series/77971/
> > State : success
> >
> > == Summary ==
> >
> > CI Bug Log - changes
== Series Details ==
Series: drm/i915: Correct discard i915_vma_compare assertion
URL : https://patchwork.freedesktop.org/series/78053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8593_full -> Patchwork_17892_full
== Series Details ==
Series: drm/i915/gem: Delete unused code
URL : https://patchwork.freedesktop.org/series/78055/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8594 -> Patchwork_17894
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/gem: Delete unused code
URL : https://patchwork.freedesktop.org/series/78055/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b2f658eb02d drm/i915/gem: Delete unused code
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit
== Series Details ==
Series: drm/i915: Discard a misplaced GGTT vma (rev2)
URL : https://patchwork.freedesktop.org/series/77786/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8592_full -> Patchwork_17891_full
Summary
On Fri, 5 Jun 2020 at 21:04, Chris Wilson wrote:
>
> Unused as of commit 9e0f9464e2ab ("drm/i915/gem: Async GPU relocations
> only"), but left behind.
>
> >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused
> >> function 'unmask_page' [-Werror,-Wunused-function]
> static
Unused as of commit 9e0f9464e2ab ("drm/i915/gem: Async GPU relocations
only"), but left behind.
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused
>> function 'unmask_page' [-Werror,-Wunused-function]
static inline void *unmask_page(unsigned long p)
^
>>
Hi Eugeniy,
Thanks for testing. I looked at the second one (I hoped it would just
magically disappear) and I still don't understand what's going on
there. My patch series isn't touching that area at all, so really
confused.
I squashed in the bugfix from the previous round into the right
patches,
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 84d24cb5247a356a4310a25761f8aa56b8814538
commit: 9e0f9464e2ab36b864359a59b0e9058fdef0ce47 [1/7] drm/i915/gem: Async GPU
relocations only
config: x86_64-randconfig-a011-20200605 (attached as .config)
compiler: clang
== Series Details ==
Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2)
URL : https://patchwork.freedesktop.org/series/77964/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8593 -> Patchwork_17893
Quoting Matthew Auld (2020-06-05 20:05:03)
> On Fri, 5 Jun 2020 at 19:49, Chris Wilson wrote:
> >
> > As a last minute addition, I added an assertion to make sure that the
> > new i915_vma view would be equal to the discard. However, the positive
> > encouragement from CI only goes to show that
== Series Details ==
Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2)
URL : https://patchwork.freedesktop.org/series/77964/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
375207a3bd0b drm/mm: add ig_frag selftest
-:75: CHECK:BRACES: Blank lines aren't
== Series Details ==
Series: drm/i915: Correct discard i915_vma_compare assertion
URL : https://patchwork.freedesktop.org/series/78053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8593 -> Patchwork_17892
Summary
---
On 6/5/20 9:45 AM, Christian König wrote:
Am 03.06.20 um 12:32 schrieb Nirmoy Das:
This patch introduces fragmentation in the address range
and measures time taken by 10k and 20k insertions. ig_frag()
will fail if the time taken by 20k insertions takes more than
4 times of 10k insertions as we
This patch introduces fragmentation in the address range
and measures time taken by 10k and 20k insertions. ig_frag()
will fail if the time taken by 20k insertions takes more than
4 times of 10k insertions as we know that insertions should at
most scale quadratically.
v2:
introduce fragmentation
On Fri, 5 Jun 2020 at 19:49, Chris Wilson wrote:
>
> As a last minute addition, I added an assertion to make sure that the
> new i915_vma view would be equal to the discard. However, the positive
> encouragement from CI only goes to show that we rarely take this path,
> and it wasn't until the
As a last minute addition, I added an assertion to make sure that the
new i915_vma view would be equal to the discard. However, the positive
encouragement from CI only goes to show that we rarely take this path,
and it wasn't until the post-merge run did we hit the assert.
Fixes: 9bdcaa5e3a2f
On Fri, Jun 05, 2020 at 07:31:35PM +0200, Hans de Goede wrote:
> On 6/5/20 7:09 PM, Andy Shevchenko wrote:
> > On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote:
> > > On 6/2/20 5:23 PM, Andy Shevchenko wrote:
> > > > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote:
...
== Series Details ==
Series: drm/i915/gt: Include the engine's fw-domains in the debug info
URL : https://patchwork.freedesktop.org/series/78048/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17889_full
Hi,
On 6/5/20 7:09 PM, Andy Shevchenko wrote:
On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote:
On 6/2/20 5:23 PM, Andy Shevchenko wrote:
On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote:
The pins on the Bay Trail SoC have separate input-buffer and output-buffer
== Series Details ==
Series: drm/i915: Discard a misplaced GGTT vma (rev2)
URL : https://patchwork.freedesktop.org/series/77786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8592 -> Patchwork_17891
Summary
---
== Series Details ==
Series: drm/i915: Fix comments mentioning typo in IS_ENABLED()
URL : https://patchwork.freedesktop.org/series/78044/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17888_full
On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote:
> On 6/2/20 5:23 PM, Andy Shevchenko wrote:
> > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote:
> > > The pins on the Bay Trail SoC have separate input-buffer and output-buffer
> > > enable bits and a read of the level
== Series Details ==
Series: series starting with [1/5] drm/i915: Add
list_for_each_entry_safe_continue_reverse (rev2)
URL : https://patchwork.freedesktop.org/series/78031/
State : failure
== Summary ==
Applying: drm/i915: Add list_for_each_entry_safe_continue_reverse
Applying: drm/i915/gem:
Across the many users of the GGTT vma (internal objects, mmapings,
display etc), we may end up with conflicting requirements for the
placement. Currently, we try to resolve the conflict by unbinding the
vma and rebinding it to match the new constraints; over time we will end
up with a GGTT that
== Series Details ==
Series: drm/i915/gt: Include the engine's fw-domains in the debug info
URL : https://patchwork.freedesktop.org/series/78048/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17889
Over the next couple of patches, we will want to lock all the modified
vma for relocation processing under a single ww_mutex. We neither want
to have to include the vma that are skipped (due to no modifications
required) nor do we want those to be marked as written too. So separate
out the reloc
== Series Details ==
Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev2)
URL : https://patchwork.freedesktop.org/series/78019/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17887_full
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-06-05 16:33:19)
>> Chris Wilson writes:
>>
>> > If any engine asks for the tasklet to be kicked from the CS interrupt,
>> > do so.
>>
>> The why part is a bit thin. The plan is to use execlist tasklet
>> for move stuff from virtual rings to
On Fri, 2020-06-05 at 17:04 +0300, Gwan-gyeong Mun wrote:
> The IO buffer Wake and Fast Wake bit size and value have been changed from
> Gen12+. It programs the default value of IO buffer Wake and Fast Wake on
> Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12
> and
Quoting Mika Kuoppala (2020-06-05 16:33:19)
> Chris Wilson writes:
>
> > If any engine asks for the tasklet to be kicked from the CS interrupt,
> > do so.
>
> The why part is a bit thin. The plan is to use execlist tasklet
> for move stuff from virtual rings to real ones?
Yes. I thought that
== Series Details ==
Series: drm/i915: Fix comments mentioning typo in IS_ENABLED()
URL : https://patchwork.freedesktop.org/series/78044/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17888
Summary
Quoting Tvrtko Ursulin (2020-06-05 16:27:26)
>
> On 05/06/2020 10:58, Chris Wilson wrote:
> > Over the next couple of patches, we will want to lock all the modified
> > vma for relocation processing under a single ww_mutex. We neither want
> > to have to include the vma that are skipped (due to
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-06-05 16:20:34)
>> Chris Wilson writes:
>>
>> > We may choose not to submit for a number of reasons, yet not fill both
>> > ELSP. In which case we must start timeslicing (there will be no ACK
>> > event on which to hook the start) if the queue
Chris Wilson writes:
> If any engine asks for the tasklet to be kicked from the CS interrupt,
> do so.
The why part is a bit thin. The plan is to use execlist tasklet
for move stuff from virtual rings to real ones?
-Mika
>
> Signed-off-by: Chris Wilson
> ---
>
Chris Wilson writes:
> This was removed in commit 478ffad6d690 ("drm/i915: drop
> engine_pin/unpin_breadcrumbs_irq") as the last user had been removed,
> but now there is a promise of a new user in the next patch.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
>
Quoting Mika Kuoppala (2020-06-05 16:20:34)
> Chris Wilson writes:
>
> > We may choose not to submit for a number of reasons, yet not fill both
> > ELSP. In which case we must start timeslicing (there will be no ACK
> > event on which to hook the start) if the queue would benefit from the
> >
On 05/06/2020 10:58, Chris Wilson wrote:
Over the next couple of patches, we will want to lock all the modified
vma for relocation processing under a single ww_mutex. We neither want
to have to include the vma that are skipped (due to no modifications
required) nor do we want those to be
Quoting Matthew Auld (2020-06-05 16:00:49)
> On Fri, 5 Jun 2020 at 11:56, Chris Wilson wrote:
> >
> > Across the many users of the GGTT vma (internal objects, mmapings,
> > display etc), we may end up with conflicting requirements for the
> > placement. Currently, we try to resolve the conflict
Chris Wilson writes:
> Add engine->fw_domain/active to the pretty printer for debug dumps and
> debugfs.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Venkata Sandeep Dhanalakota
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++
> 1 file
Chris Wilson writes:
> We may choose not to submit for a number of reasons, yet not fill both
> ELSP. In which case we must start timeslicing (there will be no ACK
> event on which to hook the start) if the queue would benefit from the
> currently active context being evicted.
>
> Signed-off-by:
Imre, I have addressed and re-reported.
Lakshmi.
-Original Message-
From: Imre Deak
Sent: Friday, June 5, 2020 2:50 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for series starting with [RESEND,v3,1/3]
drm/i915/dp_mst: Fix
On Fri, 5 Jun 2020 at 11:56, Chris Wilson wrote:
>
> Across the many users of the GGTT vma (internal objects, mmapings,
> display etc), we may end up with conflicting requirements for the
> placement. Currently, we try to resolve the conflict by unbinding the
> vma and rebinding it to match the
On 05/06/2020 10:58, Chris Wilson wrote:
One more list iterator variant, for when we want to unwind from inside
one list iterator with the intention of restarting from the current
entry as the new head of the list.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_utils.h | 6
Chris Wilson writes:
> If we only submit the first port, leaving the second empty yet have
> ready requests pending in the queue, use that to set the timeslicing
> priority (i.e. the priority at which we will decided to enabling
s/decided/decide
> timeslicing and evict the currently active
== Series Details ==
Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev2)
URL : https://patchwork.freedesktop.org/series/78019/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17887
Add engine->fw_domain/active to the pretty printer for debug dumps and
debugfs.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Quoting Kees Cook (2020-06-05 15:19:53)
> This has no code changes, but the typo is clearly getting copy/pasted,
> so better to avoid this now and fix the typo. IS_ENABLED() takes full
> names, and must have the "CONFIG_" prefix.
>
> Reported-by: Joe Perches
> Link:
>
On 6/5/20 3:29 PM, Daniel Vetter wrote:
Design is similar to the lockdep annotations for workers, but with
some twists:
- We use a read-lock for the execution/worker/completion side, so that
this explicit annotation can be more liberally sprinkled around.
With read locks lockdep isn't
Hi,
On 6/2/20 5:23 PM, Andy Shevchenko wrote:
On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote:
The pins on the Bay Trail SoC have separate input-buffer and output-buffer
enable bits and a read of the level bit of the value register will always
return the value from the
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from
queue
URL : https://patchwork.freedesktop.org/series/78037/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17885_full
This has no code changes, but the typo is clearly getting copy/pasted,
so better to avoid this now and fix the typo. IS_ENABLED() takes full
names, and must have the "CONFIG_" prefix.
Reported-by: Joe Perches
Link:
== Series Details ==
Series: dma-fence lockdep annotations, round 2 (rev2)
URL : https://patchwork.freedesktop.org/series/77986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17886
Summary
---
The IO buffer Wake and Fast Wake bit size and value have been changed from
Gen12+. It programs the default value of IO buffer Wake and Fast Wake on
Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12
and Gen12+. And it aligns PSR2 definition macros.
v2: Fix macro
On Thu, 2020-06-04 at 18:51 -0700, Souza, Jose wrote:
> On Fri, 2020-06-05 at 03:23 +0300, Gwan-gyeong Mun wrote:
> > The IO buffer Wake and Fast Wake bit size and value have been
> > changed from
> > Gen12+.
> > It programs default value of IO buffer Wake and Fast Wake on
> > Gen12+.
> >
> > -
== Series Details ==
Series: dma-fence lockdep annotations, round 2 (rev2)
URL : https://patchwork.freedesktop.org/series/77986/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: dma-fence lockdep annotations, round 2 (rev2)
URL : https://patchwork.freedesktop.org/series/77986/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e78a321ad3b9 mm: Track mmu notifiers in fs_reclaim_acquire/release
-:12: ERROR:GIT_COMMIT_ID: Please
== Series Details ==
Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST
on a port (rev6)
URL : https://patchwork.freedesktop.org/series/77969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full
Design is similar to the lockdep annotations for workers, but with
some twists:
- We use a read-lock for the execution/worker/completion side, so that
this explicit annotation can be more liberally sprinkled around.
With read locks lockdep isn't going to complain if the read-side
isn't
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from
queue
URL : https://patchwork.freedesktop.org/series/78037/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17885
== Series Details ==
Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma
URL : https://patchwork.freedesktop.org/series/78033/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17884_full
On Fri, Jun 5, 2020 at 10:30 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> Hi Daniel,
>
> On 04/06/2020 10:12, Daniel Vetter wrote:
> [...]
> > @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct
> > drm_atomic_state *state,
> >* explicitly on fences instead
> >
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from
queue
URL : https://patchwork.freedesktop.org/series/78037/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from
queue
URL : https://patchwork.freedesktop.org/series/78037/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3a6921c1 drm/i915/gt: Set timeslicing priority from queue
A key prolem with legacy ring buffer submission is that it is an inheret
FIFO queue across all clients; if one blocks, they all block. A
scheduler allows us to avoid that limitation, and ensures that all
clients can submit in parallel, removing the resource contention of the
global ringbuffer.
Build a bare bones scheduler to sit on top the global legacy ringbuffer
submission. This virtual execlists scheme should be applicable to all
older platforms.
A key problem we have with the legacy ring buffer submission is that it
only allows for FIFO queuing. All clients share the global request
This was removed in commit 478ffad6d690 ("drm/i915: drop
engine_pin/unpin_breadcrumbs_irq") as the last user had been removed,
but now there is a promise of a new user in the next patch.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +
If we allow for per-client timelines, even with legacy ring submission,
we open the door to a world full of possiblities [scheduling and
semaphores].
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 21 +
1 file changed, 9 insertions(+), 12
We may choose not to submit for a number of reasons, yet not fill both
ELSP. In which case we must start timeslicing (there will be no ACK
event on which to hook the start) if the queue would benefit from the
currently active context being evicted.
Signed-off-by: Chris Wilson
---
To support legacy ring buffer scheduling, we want a virtual ringbuffer
for each client. These rings are purely for holding the requests as they
are being constructed on the CPU and never accessed by the GPU, so they
should not be bound into the GGTT, and we can use plain old WB mapped
pages.
As
If any engine asks for the tasklet to be kicked from the CS interrupt,
do so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 -
drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
Switch over from FIFO global submission to the priority-sorted
topographical scheduler. At the cost of more busy work on the CPU to
keep the GPU supplied with the next packet of requests, this allows us
to reorder requests around submission stalls.
This also enables the timer based RPS, with the
Couple up the context in/out accounting to record how long each engine
is busy handling requests. This is exposed to userspace for more accurate
measurements, and also enables our soft-rps timer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++
If we only submit the first port, leaving the second empty yet have
ready requests pending in the queue, use that to set the timeslicing
priority (i.e. the priority at which we will decided to enabling
timeslicing and evict the currently active context if the queue is of
equal priority after its
== Series Details ==
Series: series starting with [1/5] drm/i915: Add
list_for_each_entry_safe_continue_reverse
URL : https://patchwork.freedesktop.org/series/78031/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17883_full
On Thu, Jun 04, 2020 at 04:18:49PM -0700, Matt Roper wrote:
> On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote:
> > > When TGP is paired with RKL it uses a different HPD pin mapping than
> > > when paired with TGL.
> > >
On Fri, Jun 05, 2020 at 11:26:13AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling
> MST on a port (rev6)
> URL : https://patchwork.freedesktop.org/series/77969/
> State : failure
>
> == Summary ==
>
> CI Bug Log
On Thu, Jun 04, 2020 at 03:12:40PM -0700, Matt Roper wrote:
> On Thu, Jun 04, 2020 at 08:01:57PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> > > RKL uses the same BW_BUDDY programming table as TGL, but programs the
> > > values into a single set
== Series Details ==
Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma
URL : https://patchwork.freedesktop.org/series/78033/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17884
== Series Details ==
Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST
on a port (rev6)
URL : https://patchwork.freedesktop.org/series/77969/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full
== Series Details ==
Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma
URL : https://patchwork.freedesktop.org/series/78033/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5de23154206a drm/i915: Discard a misplaced GGTT vma
8f309332415b drm/i915/gem:
Rearrange the allocation of the mm_struct registration to avoid
allocating underneath the i915->mm_lock, so that we avoid tainting the
lock (and in turn many other locks that may be held as i915->mm_lock is
taken, and those locks we may want on the free [shrinker] paths). In
doing so, we convert
Across the many users of the GGTT vma (internal objects, mmapings,
display etc), we may end up with conflicting requirements for the
placement. Currently, we try to resolve the conflict by unbinding the
vma and rebinding it to match the new constraints; over time we will end
up with a GGTT that
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