> On Sep 1, 2020, at 03:48, Ville Syrjälä wrote:
>
> On Thu, Aug 27, 2020 at 01:04:54PM +0800, Kai Heng Feng wrote:
>> Hi Ville,
>>
>>> On Aug 27, 2020, at 12:24 AM, Ville Syrjälä
>>> wrote:
>>>
>>> On Wed, Aug 26, 2020 at 01:21:15PM +0800, Kai-Heng Feng wrote:
LSPCON only supports 8
Hi all,
On Wed, 26 Aug 2020 10:01:13 +1000 Stephen Rothwell
wrote:
>
> Hi all,
>
> Today's linux-next merge of the drm-misc tree got conflicts in:
>
> drivers/video/fbdev/arcfb.c
> drivers/video/fbdev/atmel_lcdfb.c
> drivers/video/fbdev/savage/savagefb_driver.c
>
> between commit:
>
>
Hi all,
On Wed, 26 Aug 2020 10:55:47 +1000 Stephen Rothwell
wrote:
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/qxl/qxl_display.c: In function
> 'qxl_display_read_client_monitors_config':
>
>-Original Message-
>From: Robin Murphy
>Sent: Tuesday, September 1, 2020 3:54 PM
>To: Ruhl, Michael J ; Marek Szyprowski
>; dri-de...@lists.freedesktop.org;
>io...@lists.linux-foundation.org; linaro-mm-...@lists.linaro.org; linux-
>ker...@vger.kernel.org
>Cc: Bartlomiej Zolnierkiewicz ;
On 2020-09-01 20:38, Ruhl, Michael J wrote:
-Original Message-
From: Intel-gfx On Behalf Of
Marek Szyprowski
Sent: Wednesday, August 26, 2020 2:33 AM
To: dri-de...@lists.freedesktop.org; io...@lists.linux-foundation.org;
linaro-mm-...@lists.linaro.org; linux-ker...@vger.kernel.org
Cc:
>-Original Message-
>From: Intel-gfx On Behalf Of
>Marek Szyprowski
>Sent: Wednesday, August 26, 2020 2:33 AM
>To: dri-de...@lists.freedesktop.org; io...@lists.linux-foundation.org;
>linaro-mm-...@lists.linaro.org; linux-ker...@vger.kernel.org
>Cc: Bartlomiej Zolnierkiewicz ; David Airlie
On Mon, Aug 31, 2020 at 06:09:21PM -0700, José Roberto de Souza wrote:
> For platforms without selective fetch this register is reserved so
> do not write 0 to it.
>
> Cc: Gwan-gyeong Mun
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Reviewed-by: Rodrigo Vivi
> ---
>
On Tue, Sep 01, 2020 at 11:27:58AM -0700, Anusha Srivatsa wrote:
> We currenty check for platform at multiple parts in the driver
> to grab the correct PLL. Let us begin to centralize it through a
> helper function.
>
> v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)
>
>
== Series Details ==
Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev2)
URL : https://patchwork.freedesktop.org/series/81150/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8951 -> Patchwork_18430
Summary
== Series Details ==
Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev2)
URL : https://patchwork.freedesktop.org/series/81150/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b838e80247e drm/i915/pll: Centralize PLL_ENABLE register lookup
-:30:
On 2020-08-26 07:32, Marek Szyprowski wrote:
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the
We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.
v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)
Suggested-by: Matt Roper
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by:
Super minor nitpicks:
On Tue, 2020-09-01 at 16:22 +1000, Sam McNally wrote:
> From: Hans Verkuil
>
> Signed-off-by: Hans Verkuil
> [sa...@chromium.org:
> - rebased
> - removed polling-related changes
> - moved the calls to drm_dp_cec_(un)set_edid() into the next patch
> ]
> Signed-off-by:
On Tue, 01 Sep 2020, Lyude Paul wrote:
> On Tue, 2020-09-01 at 15:32 +0300, Jani Nikula wrote:
>> In the future, we'll be needing more of the extended receiver capability
>> field starting at DPCD address 0x2200. (Specifically, we'll need main
>> link channel coding cap for DP 2.0.) Start using
On Tue, 2020-09-01 at 15:32 +0300, Jani Nikula wrote:
> In the future, we'll be needing more of the extended receiver capability
> field starting at DPCD address 0x2200. (Specifically, we'll need main
> link channel coding cap for DP 2.0.) Start using it now to not miss out
> later on.
>
> Cc:
On Tue, 2020-09-01 at 09:59 +, Patchwork wrote:
> Patch Details
> Series: series starting with [1/4] drm/i915/display: Ignore
> IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
> URL: https://patchwork.freedesktop.org/series/81201/
> State:failure
> Details:
>
Hi Mario,
Sorry to make you feel uncomfortable.
I think it is not setup guide problem, the main reason is the Xen code is very
old (We are upgrading GVT-g code on Linux kernel side and we haven’t upgraded
the Xen and Qemu source for XenGT for at least 2 years) but your GCC is new
(You are
== Series Details ==
Series: drm/i915: fix regression leading to display audio probe failure on GLK
URL : https://patchwork.freedesktop.org/series/81227/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8951 -> Patchwork_18429
On 01/09/2020 16:09, Tvrtko Ursulin wrote:
Hi,
On 26/08/2020 02:11, Lucas De Marchi wrote:
Hi,
Any update on this? It now conflicts in a few places so it needs a
rebase.
I don't see any previous email on the topic - what kind of update, where
and how, are you looking for? Rebase against
In commit 4f0b4352bd26 ("drm/i915: Extract cdclk requirements checking
to separate function") the order of force_min_cdclk_changed check and
intel_modeset_checks(), was reversed. This broke the mechanism to
immediately force a new CDCLK minimum, and lead to driver probe
errors for display audio on
Hi,
On 26/08/2020 02:11, Lucas De Marchi wrote:
Hi,
Any update on this? It now conflicts in a few places so it needs a rebase.
I don't see any previous email on the topic - what kind of update, where
and how, are you looking for? Rebase against drm-tip so you pull it in?
Rebase against
On Tue, Sep 1, 2020 at 8:22 AM Anshuman Gupta wrote:
>
Hi Anshuman,
Thank you for sending this along! I have a few comments below.
> Gen12 has measure changes with respect to HDCP display
> engine instaces lies in Trascoder insead of DDI as in Gen11.
*instances
*transcoder
*instead
>
> This
On Mon, 31 Aug 2020, Jani Nikula wrote:
> On Mon, 31 Aug 2020, Ville Syrjälä wrote:
>> On Fri, Aug 28, 2020 at 09:19:40AM +0300, Jani Nikula wrote:
>>> The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
>>> used for the embedded display. Add support for using it via the EDID
== Series Details ==
Series: drm/dp: start using more of the extended receiver caps
URL : https://patchwork.freedesktop.org/series/81223/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8951 -> Patchwork_18428
Summary
== Series Details ==
Series: drm/i915/hdcp: Gen12 HDCP 1.4 support over DP MST
URL : https://patchwork.freedesktop.org/series/81222/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
In the future, we'll be needing more of the extended receiver capability
field starting at DPCD address 0x2200. (Specifically, we'll need main
link channel coding cap for DP 2.0.) Start using it now to not miss out
later on.
Cc: Lyude Paul
Signed-off-by: Jani Nikula
---
I guess this can be
Gen12 has measure changes with respect to HDCP display
engine instaces lies in Trascoder insead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream trascoder for stream encryption
separately.
It also requires to validate the stream
Still (rc3) doesn't work without the three reverts.
I'm not sure how to proceed, I cannot capture any oops, and see nothing
obvious in any logs.
--
Hilsen Harald
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface
On Fri, Aug 07, 2020 at 03:05:49PM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
>
> Signed-off-by: Karthik B S
> Signed-off-by: Vandita
On Fri, Aug 07, 2020 at 03:05:48PM +0530, Karthik B S wrote:
> Since the flip done event will be sent in the flip_done_handler,
> no need to add the event to the list and delay it for later.
>
> v2: -Moved the async check above vblank_get as it
> was causing issues for PSR.
>
> v3: -No need
On Fri, Aug 07, 2020 at 03:05:47PM +0530, Karthik B S wrote:
> If flip is requested on any other plane, reject it.
>
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
>
> If any of these are modified, reject async flip.
>
> v2: -Replace
On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> v2: -Move the Async flip enablement to individual patch (Paulo)
>
> v3: -Rebased.
>
> v4: -Add separate plane hook for async flip case (Ville)
On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface
On Thu, Apr 30, 2020 at 02:50:52PM +0100, Emil Velikov wrote:
> Hi Ville
>
> I don't fully grok the i915 changes to provide meaningful review.
> There are couple of small comments below, but regardless of those
Sorry, forgot to reply to this in a timely manner.
>
> Patches 01-11 and 14-16 are:
== Series Details ==
Series: series starting with [1/4] drm/i915/display: Ignore
IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/81201/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8948_full -> Patchwork_18426_full
On Mon, Aug 31, 2020 at 07:57:30PM +0200, Hans de Goede wrote:
> On 8/31/20 3:15 PM, Thierry Reding wrote:
> > On Mon, Aug 31, 2020 at 01:46:28PM +0200, Hans de Goede wrote:
> > > On 8/31/20 1:10 PM, Thierry Reding wrote:
> > > > On Sun, Aug 30, 2020 at 02:57:42PM +0200, Hans de Goede wrote:
> > >
On 2020-08-18 at 11:38:48 -0400, Sean Paul wrote:
> From: Sean Paul
>
> Only one functional change, reversed the hdcp_1x/2x_present bits in the
> QUERY_STREAM_ENCRYPTION_STATUS parsing with a comment explaining my
> confusion.
>
> Other than that, lots of rebasing, the most notable being the
>
Hi Ben Skeggs,
Gentle Reminder, Can you please take a look at the patch and provide your ack.
Thanks
Jeevan B
>-Original Message-
>From: B, Jeevan
>Sent: Sunday, August 16, 2020 12:22 PM
>To: nouv...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
From: Hans Verkuil
Signed-off-by: Hans Verkuil
[sa...@chromium.org:
- rebased
- removed polling-related changes
- moved the calls to drm_dp_cec_(un)set_edid() into the next patch
]
Signed-off-by: Sam McNally
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
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